GS78116B BGA Commercial Temp Industrial Temp 512K x 16 8Mb Asynchronous SRAM Features • Fast access time: 10, 12, 15 ns • CMOS low power operation: 300/250/220/180 mA at minimum cycle time • Single 3.3 V ± 0.3 V power supply • All inputs and outputs are TTL-compatible • Fully static operation • Industrial Temperature Option: –40° to 85°C • 14 mm x 22 mm, 119-Bump, 1.27 mm Pitch Ball Grid Array package Pin Descriptions Symbol Description 10, 12, 15 ns 3.3 V VDD Description A0 to A18 Address input DQ1 to DQ16 Data input/output CE Chip enable input WE Write enable input OE Output enable input VDD +3.3 V power supply VSS Ground NC No connect The GS78116 is a high speed CMOS static RAM organized as 524,288-words by 16-bits. Static design eliminates the need for external clocks or timing strobes. The GS78116 operates on a single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS78116 is available in 14 mm x 22 mm BGA package. Block Diagram A0 Address Input Buffer Memory Array Column Decoder A18 CE WE OE Row Decoder I/O Buffer Control DQ1 Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 1/11 DQ16 © 1999, Giga Semiconductor, Inc. GS78116B 512K x 16 Async SRAM in 119-Bump, 14 mm x 22 mm Top View 1 2 3 4 5 6 7 A NC A15 A14 A16 A13 A12 NC B NC, VSS A11 A10 CE A9 A8 NC C NC NC VDD, NC A17 VSS, NC NC NC D NC VDD VSS VSS VSS VDD NC E DQ1 NC VDD VSS VDD NC DQ16 F DQ2 VDD VSS VSS VSS VDD DQ15 G DQ3 NC VDD VSS VDD NC DQ14 H DQ4 VDD VSS VSS VSS VDD DQ13 J VDD VSS VDD VSS VDD VSS VDD K DQ5 VDD VSS VSS VSS VDD DQ12 L DQ6 NC VDD VSS VDD NC DQ11 M DQ7 VDD VSS VSS VSS VDD DQ10 N DQ8 NC VDD VSS VDD NC DQ9 P NC VDD VSS VSS VSS VDD NC R NC NC NC A18 NC NC NC T NC A7 A6 WE A5 A4 NC, VSS U NC A3 A2 OE A1 A0 NC Note: Bumps 1B, 7T, 3C, and 5C are actually NC’s but should be wired 3C = VDD and 1B, 7T and 5C = VSS to assure compatibility with future versions. Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 2/11 © 1999, Giga Semiconductor, Inc. GS78116B Truth Table CE OE WE DQ1 to DQ8 VDD Current H X X Not Selected ISB1, ISB2 L L H Read L X L Write L H H High Z IDD Note: X: “H” or “L” Absolute Maximum Ratings Parameter Symbol Rating Unit Supply Voltage VDD –0.5 to +4.6 V Input Voltage VIN –0.5 to VDD +0.5 (≤ 4.6 V max.) V Output Voltage VOUT –0.5 to VDD+0.5 (≤ 4.6 V max.) V Allowable power dissipation PD 1.5 W Storage temperature TSTG –55 to 150 o C Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Unit Supply Voltage for -10/12/15 VDD 3.0 3.3 3.6 V Input High Voltage VIH 2.0 — VDD +0.3 V Input Low Voltage VIL –0.3 — 0.8 V Ambient Temperature, Commercial Range TAc 0 — 70 oC Ambient Temperature, Industrial Range TAi –40 — 85 oC Notes: 1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns. 2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns. Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 3/11 © 1999, Giga Semiconductor, Inc. GS78116B Capacitance Parameter Symbol Test Condition Max Unit Input Capacitance CIN VIN = 0 V 10 pF Output Capacitance COUT VOUT = 0 V 7 pF Notes: 1. Tested at TA = 25°C, f = 1 MHz 2. These parameters are sampled and are not 100% tested. DC I/O Pin Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current IIL VIN = 0 to VDD –2 uA 2 uA Output Leakage Current IOL Output High Z, VOUT = 0 to VDD –1 uA 1 uA Output High Voltage VOH IOH = –4 mA 2.4 Output Low Voltage VOL IOL = +4 mA 0.4 V Power Supply Currents Parameter Symbol Test Conditions 0 to 70°C –40 to 85°C 10 ns 12 ns 15 ns 10 ns 12 ns 15 ns IDD E ≤ VIL All other inputs ≥ VIH or ≤ VIL Min. cycle time IOUT = 0 mA 225 mA 220 mA 180 mA 270 mA 240 mA 200 mA Standby Current ISB1 E ≥ VIH All other inputs ≥ VIH or ≤VIL Min. cycle time 130 mA 120 mA 110 mA 150 mA 140 mA 130 mA Standby Current ISB2 E ≥ VDD – 0.2V All other inputs ≥ VDD – 0.2 V or ≤ 0.2 V Operating Supply Current Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 4/11 60 mA 80 mA © 1999, Giga Semiconductor, Inc. GS78116B AC Test Conditions Output Load 1 Parameter Conditions Input high level VIH = 2.4 V Input low level VIL = 0.4 V Input rise time tr = 1 V/ns Input fall time tf = 1 V/ns Input reference level 1.4 V Output Load 2 Output reference level 1.4 V 3.3 V Output load Fig. 1& 2 DQ 50Ω 30pF1 VT = 1.4 V 589Ω DQ Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted 3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ. 5pF1 434Ω AC Characteristics Read Cycle Parameter Symbol Read cycle time -10 -12 -15 Unit Min Max Min Max Min Max tRC 10 — 12 — 15 — ns Address access time tAA — 10 — 12 — 15 ns Chip enable access time (CE) tAC — 10 — 12 — 15 ns Output enable to output valid (OE) tOE — 4 — 5 — 6 ns Output hold from address change tOH 3 — 3 — 3 — ns Chip enable to output in low Z (CE) tLZ* 3 — 3 — 3 — ns Output enable to output in low Z (OE) tOLZ* 0 — 0 — 0 — ns Chip disable to output in High Z (CE) tHZ* — 5 — 6 — 7 ns Output disable to output in High Z (OE) tOHZ* — 4 — 5 — 6 ns Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 5/11 © 1999, Giga Semiconductor, Inc. GS78116B Read Cycle 1:CE = OE = VIL tRC Address tAA tOH Data Out Previous Data Data valid Read Cycle 2: WE = VIH tRC Address tAA CE tAC tHZ tLZ OE Data Out tOLZ High impedance Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 6/11 tOE tOHZ Data valid © 1999, Giga Semiconductor, Inc. GS78116B Write Cycle Parameter Symbol Write cycle time -10 -12 -15 Unit Min Max Min Max Min Max tWC 10 — 12 — 15 — ns Address valid to end of write tAW 7 — 8 — 10 — ns Chip enable to end of write tCW 7 — 8 — 10 — ns Data set up time tDW 5 — 6 — 7 — ns Data hold time tDH 0 — 0 — 0 — ns Write pulse width tWP 7 — 8 — 10 — ns Address set up time tAS 0 — 0 — 0 — ns Write recovery time (WE) tWR 0 — 0 — 0 — ns Write recovery time (CE) tWR1 0 — 0 — 0 — ns Output Low Z from end of write tWLZ* 3 — 3 — 3 — ns Write to output in High Z tWHZ* — 4 — 5 — 6 ns * These parameters are sampled and are not 100% tested. Write Cycle 1: WE Controlled tWC Address tAW tWR OE tCW CE tAS tWP WE tDW Data In Data valid tWHZ Data Out Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. tDH tWLZ High impedance 7/11 © 1999, Giga Semiconductor, Inc. GS78116B Write Cycle 2: CE Controlled tWC Address tAW tWR1 OE tAS tCW CE tWP WE tDW Data In Data valid Data Out Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. tDH High impedance 8/11 © 1999, Giga Semiconductor, Inc. GS78116B Package Dimensions - 119-Pin PBGA A Pin 1 Corner 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U G B P S D N R Bottom View Top View C F E K T Package Dimensions - 119 Pin PBGA Symbol Description Min. Nom. Max A Width 13.8 14.0 14.2 B Length 21.8 22.0 22.2 C Package Height (including ball) — — 2.40 D Ball Size 0.60 0.75 0.90 E Ball Height 0.50 0.60 0.70 F Package Height (excluding balls) — 1.46 1.70 G Width between Balls — 1.27 — K Package Height above board 0.80 0.90 1.00 N Cut-out Package Width — 12.00 — P Foot Length — 19.50 — R Width of package between balls — 7.62 — S Length of package between balls — 20.32 — T Variance of Ball Height — 0.15 — Unit: mm Side View BPR 1999.05.18 Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 9/11 © 1999, Giga Semiconductor, Inc. GS78116B Ordering Information Part Number* Package Access Time Temp. Range GS78116B-10 BGA 10 ns Commercial GS78116B-12 BGA 12 ns Commercial GS78116B-15 BGA 15 ns Commercial GS78116B-10I BGA 10 ns Industrial GS78116B-12I BGA 12 ns Industrial GS78116B-15I BGA 15 ns Industrial Status * Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS78116B-12T Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. 10/11 © 1999, Giga Semiconductor, Inc. GS78116B Asynchronous SRAM Datasheet Revision History Rev. Code: Old; New Types of Changes Format or Content GS78116Rev0.01a 5/1999; 1.00 X/1999 Format/Typos Content • p.2/Changed E to CE/consistency. • p.2/Changed Pin T1 from BA to BD/Correction • Added GSI Logo GS78116Rev 1.0010/1999A;Rev 1.01 2/2000FormatB Rev 1.01 2/2000FormatB; 78116_r1_02 Page #/Revisions/Reason Format/Content Rev: 1.02 9/2001 For latest documentation see http://www.gsitechnology.com. • Updated format to comply with Technical Publication standards • Finalized document and removed preliminary references 11/11 © 1999, Giga Semiconductor, Inc.