Revised December 2000 GTLP6C816A GTLP/LVTTL 1:6 Clock Driver General Description Features The GTLP6C816A is a clock driver that provides LVTTL to GTLP signal level translation (and vice versa). The device provides a high speed interface between cards operating at LVTTL logic levels and a backplane operating at GTL(P) logic levels. High speed backplane operation is a direct result of GTLP’s reduced output swing (<1V), reduced input threshold levels and output edge rate control. The edge rate control minimizes bus settling time. GTLP is a Fairchild Semiconductor derivative of the Gunning Transceiver logic (GTL) JEDEC standard JESD8-3. ■ Interface between LVTTL and GTLP logic levels Fairchild’s GTL(P) has internal edge-rate control and is process, voltage, and temperature (PVT) compensated. Its function is similar to BTL and GTL but with different output levels and receiver threshold. GTLP output LOW level is typically less than 0.5V, the output level HIGH is 1.5V and the receiver threshold is 1.0V. ■ Designed with edge rate control circuitry to reduce output noise on the GTLP port ■ VREF pin provides external supply reference voltage for receiver threshold adjustibility ■ Special PVT compensation circuitry to provide consistent performance over variations of process, supply voltage and temperature ■ TTL compatible driver and control inputs ■ Designed using Fairchild advanced BiCMOS technology ■ Bushold data inputs on A port to eliminate the need for external pull-up resistors for unused inputs ■ Power up/down and power off high impedance for live insertion ■ Open drain on GTLP to support wired-or connection ■ A Port source/sink −24mA/+24mA ■ B Port sink +50mA ■ 1:6 fanout clock driver for TTL port ■ 1:2 fanout clock driver for GTLP port ■ Low voltage version of GTLP6C816 Ordering Code: Order Number Package Number Package Description GTLP6C816AMTC MTC24 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Device is also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pin Descriptions Pin Names Connection Diagram Description TTLIN, GTLPIN Clock Inputs (LVTTL and GTLP respectively) OEB Output Enable (Active LOW) GTLP Port (LVTTL Levels) OEA Output Enable (Active LOW) TTL Port (LVTTL Levels) VCCT.GNDT TTL Output Supplies VCC Internal Circuitry VCC GNDG OBn GTLP Output Grounds VREF Voltage Reference Input OA0–OA5 TTL Buffered Clock Outputs OB0–OB1 GTLP Buffered Clock Outputs © 2000 Fairchild Semiconductor Corporation DS500179 www.fairchildsemi.com GTLP6C816A GTLP/LVTTL 1:6 Clock Driver August 1998 GTLP6C816A Functional Description The GTLP6C816A is a clock driver providing LVTTL-to-GTLP clock translation, and GTLP-to-LVTTL clock translation in the same package. The LVTTL-to-GTLP direction is a 1:2 clock driver path with a single Enable pin (OEB). For the GTLP-to-LVTTL direction the clock receiver path is a 1:6 buffer with a single Enable control (OEA). Data polarity is inverting for both directions. Truth Tables Inputs Outputs OBn TTLIN OEB H L L L L H X H High Z Inputs Outputs OAn GTLPIN OEA H L L L L H X H High Z Logic Diagram www.fairchildsemi.com 2 Supply Voltage (VCC) −0.5V to +4.6V DC Input Voltage (VI) −0.5V to +4.6V Recommended Operating Conditions (Note 3) 3.15V to 3.45V Supply Voltage VCC DC Output Voltage (VO) Bus Termination Voltage (VTT) Outputs 3-STATE −0.5V to +4.6V GTLP Outputs Active (Note 2) −0.5V to +4.6V GTL 1.14V to 1.26V VREF 0.98V to 1.02V DC Output Sink Current into 48 mA OA Port IOL Input Voltage (VI) on INA-Port DC Output Source Current and Control Pins from OA Port IOH 0.0V to 3.45V −48 mA HIGH Level Output Current (IOH) 100 mA LOW Level Output Current (IOL) DC Output Sink Current into −24 mA OA Port OB Port in the LOW State IOL DC Input Diode Current (IIK) +24 mA OA Port VI < 0V −50 mA +50 mA OB Port DC Output Diode Current (IOK) −40°C to +85°C Operating Temperature (TA) VO < 0V −50 mA VO > VCC +50 mA Note 1: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. > 2000V ESD Rating Storage Temperature (TSTG) 1.47V to 1.53V −65°C to +150°C Note 2: Io Absolute Maximum Rating must be observed. Note 3: Unused inputs must be held HIGH or LOW. DC Electrical Characteristics Over Recommended Operating Free-Air Temperature Range, VREF = 1.0V (unless otherwise noted). Symbol VIH VIL Test Conditions Min Typ VREF +0.05 GTLPIN Max (Note 4) Others 2.0 GTLPIN 0.0 VTT Units V V Others VREF −0.05 V 0.8 V VREF (Note 5) GTLP 1.0 V VTT (Note 5) 1.5 V GTLP VIK VOH VOL VOL II OAn Port OAn Port OBn Port TTLIN/ VCC = 3.15V II = −18 mA VCC = 3.15V IOH = −100 µA VCC−0.2 IOH = −18 mA 2.4 IOH = −24 mA 2.2 VCC = 3.15V VCC = 3.15V VCC = 3.45V Control Pins GTLPIN VCC = 3.45V −1.2 V V IOL = 100 µA 0.2 IOL = 18 mA 0.4 IOL = 24 mA 0.5 IOL = 100 µA 0.2 IOL = 40 mA 0.4 IOL = 50 mA 0.55 VI = 3.45V 5 VI = 0V −5 VI = VTT 5 VI = 0 −5 V V µA µA TTLIN VCC = 0 VI or VO = 0V to 3.45V 30 µA GTLPIN VCC = 0 VI or VO = 0V to VTT 30 µA IPU/PD OAn or OBn Ports VCC = 0 to 1.5V OE = Don’t Care 30 µA IOZH OAn-Port VCC = 3.45V VO =3.45V 5 VO = 1.5V 5 IOFF OBn-Port IOZL OAn-Port VCC = 3.45V VO = 0 ICC OAn or VCC = 3.45V Outputs HIGH VI = VCC or GND Outputs Disabled OBn Ports Outputs LOW 3 −5 5.5 µA µA 10 5 10 5.5 10 mA www.fairchildsemi.com GTLP6C816A Absolute Maximum Ratings(Note 1) GTLP6C816A DC Electrical Characteristics Symbol (Continued) Min Test Conditions VCC = 3.45V Typ Max (Note 4) ∆ICC TTLIN CI Control Pins/GTLPIN/TTLIN VI = VCC−0.6 VI = VCC or 0 4.5 CO OAn Port VI = VCC or 0 6.0 OBn Port VI = VCC or 0 8.0 2 Units mA pF Note 4: All typical values are at VCC = 3.3V and TA = 25°C. Note 5: GTLP VREF and VTT are specified to 2% tolerance since signal integrity and noise margin can be significantly degraded if these supplies are noisy. In addition, VTT and RTERM can be adjusted to accommodate backplane impedances other than 50Ω, within the boundaries of not exceeding the DC Absolute IOL ratings. Similarly VREF can be adjusted to compensate for changes in V TT. AC Electrical Characteristics Over recommended range of supply voltage and operating free air temperature. VREF = 1.0V (unless otherwise noted). CL = 30 pF for OBn-Port and CL = 50 pF for OAn-Port. From To (Input) (Output) Min Typ Max Symbol fTOGGLE tPLH Units (Note 6) TTLIN OBn 175 GTLPIN OAn 175 TTLIN OBn 1.3 2.3 4.0 0.9 2.6 4.3 1.5 2.6 4.1 1.2 2.5 4.1 ns tPHL tPLH MHz OEB OBn ns tPHL tRISE Transition Time, OB Outputs (20% to 80%) 1.3 tFALL Transition Time, OB outputs (20% to 80%) 1.3 tRISE Transition Time, OA outputs (10% to 90%) 1.2 tFALL Transition Time, OA outputs (10% to 90%) 2.0 tPZH, tPZL OEA OAn GTLPIN OAn 0.5 2.9 4.8 0.5 2.4 4.4 1.9 3.6 5.7 2.1 3.5 5.3 ns tPHL Note 6: All typical values are at VCC = 3.3 V and TA = 25°C. www.fairchildsemi.com ns ns tPLZ, tPHZ tPLH ns 4 Over recommended ranges of supply voltage and operating free-air temperature VREF = 1.0V (unless otherwise noted). CL = 30 pF for B Port and CL = 50 pF for A Port From To (Input) (Output) (Note 7) tOSLH (Note 8) A B 0.1 0.2 tOSHL (Note 8) A B 0.1 0.6 0.3 Symbol Min Typ Max Units ns tPS (Note 9) A B tPV(HL) (Note 10)(Note 11) A B 1.0 ns 1.3 ns tOSLH (Note 8) B A 0.1 0.7 tOSHL (Note 8) B A 0.1 0.4 tOST (Note 8) B A 0.2 1.1 ns tPS (Note 9) B A 0.1 1.0 ns tPV (Note 10) B A 2.4 ns ns Note 7: All typical values are at VCC = 3.3 V and TA = 25°C. Note 8: tOSHL/tOSLH and tOST – Output-to-Output skew is defined as the absolute value of the difference between the actual propagation delay for all outputs within the same packaged device. The specifications are given for specific worst case VCC and temperature and apply to any outputs switching in the same direction dither HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH) or in opposite directions both HL and LH (tOST). This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 9: tPS – Pin or Transition skew is defined as the difference between the LOW-to-HIGH transition and the HIGH-to-LOW transition on the same pin. The parameter is measured across all the outputs of the same chip is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP outputs could vary on the backplane due to the loading and impedance seen by the device. Note 10: tPV – Part-to-Part skew is defined as the absolute value of the difference between the actual propagation delay for all outputs from device-to-device. The parameter is specified for a specific worst case VCC and temperature. This parameter is guaranteed by design and statistical process distribution. Actual skew values between the GTLP output could vary on the backplane due to the loading and impedance seen by the device. Note 11: Due to the open drain structure on GTLP outputs tOST and tPV(LH) in the A-to-B direction are not specified. Skew on these paths is dependent on the VTT and RT values on the backplane. 5 www.fairchildsemi.com GTLP6C816A Extended Electrical Characteristics GTLP6C816A Test Circuit and Timing Waveforms Test Circuit for A Outputs Test Circuit for B Outputs Note A: CL includes probes and jig capacitance. Note A: C L includes probes and jig capacitance. Note B: For B Port C L = 30 pF is used for worst case. Voltage Waveform - Propagation Delay Times Voltage Waveform - Enable and Disable Times Output Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the control output Output Waveforms 2 is for an output with internal conditions such that the output is HIGH except when disabled by the control output Input and Measure Conditions A or LVTTL Pins B or GTLP Pins VinHIGH 3.0 1.5 VinLOW 0.0 0.0 VM 1.5 1.0 VX VOL + 0.3V N/A VY VOH + 0.3V N/A All input pulses have the following characteristics: Frequency = 10MHz, tRISE = tFALL = 2 ns, ZO = 50Ω. The outputs are measured one at a time with one transition per measurement. www.fairchildsemi.com 6 GTLP6C816A GTLP/LVTTL 1:6 Clock Driver Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC24 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com