e vice olet Obs MD De elow) n o i B r at tS Vers te alen able /883 Equiv tion” T ort Cen tsc h / a t p i p m m w r o u lace ing Info nical S tersil.c p e R er ech ww.in “Ord ur T w See ntact o SIL or (October 1999R o or c 8-INTE 1-88 ® HA-5221/883 Low Noise, Wideband, Precision Operational Amplifier Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HA-5221/883 is a high performance, dielectrically isolated, monolithic op amp, featuring precision DC characteristics while providing excellent AC characteristics. Designed for audio, video, and other demanding applications, noise (3.6nV/√Hz at 1kHz typ), total harmonic distortion (<0.005% typ), and DC errors are kept to a minimum. • Gain Bandwidth Product . . . . . . . . . . . . . .100MHz (Min) • Unity Gain Bandwidth . . . . . . . . . . . . . . . . .30MHz (Min) 40MHz (Typ) • High Slew Rate . . . . . . . . . . . . . . . . . . . . . . .25V/µs (Min) 37V/µs (Typ) • Low Offset Voltage . . . . . . . . . . . . . . . . . .0.75mV (Max) 0.30mV (Typ) • High Open Loop Gain . . . . . . . . . . . . . . . . . 106dB (Min) 128dB (Typ) • Low Voltage Noise (at 1kHz) . . . . . . . . .5.8nV/√Hz (Max) 3.6nV/√Hz (Typ) • Low Current Noise (at 1kHz) . . . . . . . . 2.0pA/√Hz (Max) 1.4pA/√Hz (Typ) • High Output Current . . . . . . . . . . . . . . . . . ±30mA (Min) ±56mA (Typ) • Low Supply Current. . . . . . . . . . . . . . . . . . . 10mA (Max) 8mA (Typ) Applications • Precision Test Systems • Active Filtering The precision performance is shown by low offset voltage (0.3mV typ), low bias currents (40nA typ), low offset currents (15nA typ), and high open loop gain (128dB typ). The combination of these excellent DC characteristics with fast settling time (0.4µs typ) make the HA-5221/883 ideally suited for precision signal conditioning. The unique design of the HA-5221/883 gives this device outstanding AC characteristics, including high unity gain bandwidth (40MHz typ) and high slew rate (37V/µs typ), not normally associated with precision op amps. Other key specifications include high CMRR (95dB typ) and high PSRR (100dB typ). The combination of these specifications will allow the HA-5221/883 to be used in RF signal conditioning as well as video amplifiers. Ordering Information OBSOLETE PART NUMBER SMD NO. TEMP RANGE (oC) HA4-5221/883 5962-9163401M2A -55 to 125 20 Ld CLCC HA7-5221/883 5962-9163401MPA -55 to 125 8 Ld CERDIP PACKAGE • Small Signal Video • Accurate Signal Processing • RF Signal Conditioning Pinouts +IN 3 V- 4 + 7 V+ 6 OUT 5 NC 3 2 NC 2 + BAL +BAL -IN 8 -BAL 1 NC -BAL NC HA-5221/883 (CLCC) TOP VIEW HA-5221/883 (CERDIP) TOP VIEW 1 20 19 NC 4 18 -IN 5 17 V+ 16 NC - NC NC 6 +IN 7 15 OUT NC 8 14 NC + CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 NC NC NC V- NC 9 10 11 12 13 File Number 3716.1 HA-5221/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- Terminals . . . . . . . . . . . . . . . . . . . 36V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VPeak Output Current (Pulsed at 1ms, 10% Duty Cycle). . . . . 100mA Continuous Output Current. . . . . . . . . . . . . . Short Circuit Protected Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC θJC Thermal Resistance θJA CerDIP Package . . . . . . . . . . . . . . . . . . . 110oC/W 27oC/W Ceramic LCC Package . . . . . . . . . . . . . . 64oC/W 13oC/W Metal Can Package . . . . . . . . . . . . . . . . . 148oC/W 67oC/W Package Power Dissipation Limit at +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.91W Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.56W Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.68W Package Power Dissipation Derating Factor Above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1mW/oC Ceramic LCC Package . . . . . . . . . . . . . . . . . . . . . . . . 15.6mW/oC Metal Can Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions VINCM ≤ 1/2 (V+ - V-) RL ≥ 1kΩ Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC Operating Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . ±10V to ±15V TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = ±15V, RLOAD = 1kΩ , VOUT = 0V, Unless Otherwise Specified. PARAMETERS Input Offset Voltage Input Bias Current SYMBOL VIO +IB -IB Input Offset Current Common Mode Range IIO +CMR -CMR Large Signal Voltage Gain +AVOL -AVOL Common Mode Rejection Ratio +CMRR -CMRR Output Voltage Swing +V OUT -V OUT CONDITIONS LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC -0.75 0.75 mV 2, 3 +125oC, -55oC -1.5 1.5 mV 1 +25oC -80 80 nA 2, 3 +125oC, -55oC -200 200 nA 1 +25oC -80 80 nA 2, 3 +125oC, -55oC -200 200 nA 1 +25oC -50 50 nA 2, 3 +125oC, -55oC -150 150 nA 1 +25oC 12 - V 2, 3 +125oC, -55oC 12 - V 1 +25oC - -12 V 2, 3 +125oC, -55oC - -12 V 4 +25oC 106 - dB 5, 6 +125oC, -55oC 100 - dB 4 +25oC 106 - dB 5, 6 +125oC, -55oC 100 - dB 1 +25oC 88 - dB 2, 3 +125oC, -55oC 86 - dB 1 +25oC 88 - dB 2, 3 +125oC, -55oC 86 - dB 4 +25oC 12.0 - V 5, 6 +125oC, -55oC 11.5 - V 4 +25oC - -12.0 V 5, 6 +125oC, -55oC - -11.5 V VCM = 0V VCM = 0V, +RS = 100.1kΩ, -RS = 100Ω VCM = 0V, +RS = 100Ω, -RS = 100.1kΩ VCM = 0V, +RS = 100.1kΩ, -RS = 100.1kΩ V+ = +3V, V- = -27V V+ = +27V, V- = -3V VOUT = 0V and +10V VOUT = 0V and -10V ∆VCM = +10V, V+ = +5V, V- = -25V, VOUT = -10V ∆VCM = -10V, V+ = +25V, V- = -5V, VOUT = +10V RL = 1kΩ RL = 1kΩ 2 HA-5221/883HA-5221/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = ±15V, RLOAD = 1kΩ , VOUT = 0V, Unless Otherwise Specified. PARAMETERS Output Current SYMBOL CONDITIONS +IOUT VOUT = +10V, RL = 1kΩ 4 +25oC 30 - mA 5, 6 +125oC, -55oC 30 - mA 4 +25oC - -30 mA 5, 6 +125oC, -55oC - -30 mA 1 +25oC - 10 mA 2, 3 +125oC, -55oC - 11 mA 1 +25oC -10 - mA 2, 3 +125oC, -55oC -11 - mA 1 +25oC 90 - dB 2, 3 +125oC, -55oC 86 - dB 1 +25oC 90 - dB 2, 3 +125oC, -55oC 86 - dB 1 +25oC VIO-1 - mV 2, 3 +125oC, -55oC VIO-1 - mV 1 +25oC VIO+1 - mV 2, 3 +125oC, -55oC VIO+1 - mV -IOUT Quiescent Power Supply Current VOUT = -10V, RL = 1kΩ +ICC VOUT = 0V, IOUT = 0mA -ICC Power Supply Rejection Ratio VOUT = 0V, IOUT = 0mA +PSRR -PSRR Offset Voltage Adjustment LIMITS GROUP A SUBGROUPS +VIOAdj -VIOAdj ∆VSUP = 10V, V+ = +20V, V- = -15V, V+ = +10V, V- = -15V ∆VSUP = 10V, V+ = +15V, V- = -20V, V+ = +15V, V- = -10V Note 1 Note 1 TEMPERATURE MIN MAX UNITS NOTE: 1. Offset adjustment range is [VIO (Measured ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through 0V. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. See AC specifications in Table 3. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = ±15V, RLOAD = 1kΩ, CLOAD = 50pF, Unless Otherwise Specified. LIMITS PARAMETERS Input Noise Voltage Density SYMBOL EN NOTES TEMPERATURE MIN MAX UNITS RS = 0Ω, fO = 10Hz CONDITIONS 1, 5 +25oC - 24.0 nV/√Hz RS = 0Ω, fO = 100Hz 1, 5 +25oC - 8.0 nV/√Hz RS = 0Ω, fO = 1kHz Input Noise Current Density IN 1, 5 +25 C - 5.8 nV/√Hz RS = 500kΩ, fO = 10Hz 1, 5 +25oC - 11.5 pA/√Hz RS = 500kΩ, fO = 100Hz 1, 5 +25oC - 6.0 pA/√Hz 1, 5 +25oC - 2.0 pA/√Hz 100 - MHz RS = 500kΩ, fO = 1kHz Gain Bandwidth Product Unity Gain Bandwidth GBWP UGBW o VOUT = 200mVP-P , fO = 100kHz 1 VOUT = 200mV 1 o +25 C o o -55 C to +125 C 90 - MHz +25oC 30 - MHz 25 - MHz 25 - V/µs -55oC to +125oC Slew Rate ±SR VOUT = ±2.5V CL = 50pF 1 3 o o -55 C to +125 C HA-5221/883HA-5221/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = ±15V, RLOAD = 1kΩ, CLOAD = 50pF, Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL CONDITIONS Full Power Bandwidth FPBW VPEAK = 10V Minimum Closed Loop Stable Gain CLSG RL = 1kΩ, CL = 50pF NOTES TEMPERATURE o o MIN MAX UNITS 1, 2 -55 C to +125 C 398 - kHz 1 -55oC to +125oC 1 - V/V Rise and Fall Time tR, tF VOUT = ±100mV 1, 4 +25oC - 20 ns Overshoot ±OS VOUT = ±100mV 1 +25oC - 25 % to +125oC - 30 % to +125oC - 660 mW -55 Power Consumption PC VOUT = 0V, IOUT = 0mA 1, 3 oC -55oC NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2πVPEAK). 3. Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.). 4. Measured between 10% and 90% points. 5. Input Noise Voltage Density and Input Noise Current Density limits are based on characterization data. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 1), 2, 3, 4, 5, 6 Group A Test Requirements 1, 2, 3, 4, 5, 6 Groups C and D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. 4 HA-5221/883 Die Characteristics DIE DIMENSIONS: 72 x 94 x 19 mils ± 1 mils 1840 x 2400 x 483µm ± 25.4µm METALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ ± 2kÅ GLASSIVATION: Type: Nitride (Si3N4) over Silox (SIO2, 5% Phos.) Silox Thickness: 12kÅ ± 2kÅ Nitride Thickness: 3.5kÅ ± 1.5kÅ WORST CASE CURRENT DENSITY: 4.2 x 104A/cm 2 SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 62 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-5221/883 V- +IN -IN -BAL +BAL OUT V+ 5 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. Typical Performance Curves Unless Otherwise Specified: TA = +25oC, VSUPPLY = ±15V SUPPLY CURRENT vs TEMPERATURE TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized at: Supply Voltage = ±15V, R L = 1kΩ, C L = 50pF, Unless Otherwise Specified PARAMETERS Input Offset Voltage CONDITIONS See Table 1 TEMPERATURE TYPICAL UNITS +25oC 0.3 mV Full 0.35 mV Average Offset Voltage Drift See Table 1 Full 0.5 µV/oC Input Bias Current See Table 1 +25oC 40 nA Full 70 nA o +25 C 15 nA Full 30 nA o Input Offset Current See Table 1 Differential Input Resistance See Table 1 +25 C 70 kΩ Input Noise Voltage fO = 0.1Hz to 10Hz +25oC 0.25 µVP-P Input Noise Voltage Density Input Noise Current Density o fO = 10Hz +25 C 10 nV/√Hz fO = 100Hz +25oC 5 nV/√Hz o fO = 1kHz +25 C 3.6 nV/√Hz fO = 10Hz +25oC 7 pA/√Hz o fO = 100Hz +25 C 3 pA/√Hz fO = 1kHz +25oC 1.4 pA/√Hz o THD & N See Note 1 +25 C 0.005 % Large Signal Voltage Gain VOUT = 0V to ±10V +25oC 128 dB Full 120 dB 6 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: Supply Voltage = ±15V, R L = 1kΩ, C L = 50pF, Unless Otherwise Specified PARAMETERS Common Mode Rejection Ratio Unity Gain Bandwidth Gain Bandwidth Product CONDITIONS ∆VCM = ±10V (-3dB) 1kHz to 400kHz Minimum Gain Stability Output Voltage Swing RL = 333Ω RL = 1K Output Current VOUT = ±10V Output Resistance TEMPERATURE TYPICAL UNITS Full 95 dB +25oC 40 MHz +125oC 33 MHz -55oC 45 MHz +25oC 130 MHz +125oC 110 MHz -55oC 150 MHz Full 1 V/V Full ±10 V +25oC ±12.5 V Full ±12.1 V Full ±56 mA +25oC 10 W 398 kHz oC Full Power Bandwidth FPBW = SR/2πVPEAK, VPEAK = 10V +25 Slew Rate VOUT = ±2.5V +25oC 37 V/µs +125oC 37 V/µs -55 C 34 V/µs +25oC 13 ns +125 C 13 ns -55oC 15 ns +25 C 13 % +125oC 13 % -55 C 11 % +25oC o Rise Time VOUT = ±100mV o Overshoot VOUT = ±100mV o o Settling Time 10VSTEP, AV = -1 0.1% 0.01% Power Supply Rejection Ratio ∆VS = ±10V to ±20V Supply Current Minimum Supply Voltage Functional Operation Only. Other Parameters May Vary. 0.4 µs o +25 C 1.5 µs Full 100 dB Full 8 mA +25oC ±5 V NOTE: 1. AVCL = 10, fO = 1kHz, VOUT = 5Vrms, R L = 600Ω, 10Hz to 100Hz, Minimum resolution of test equipment is 0.005%. 7 HA-5221 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Corporation and is for use as application and design information only. No guarantee is implied. PARAMETERS Input Noise Current Density THD & N Large Signal Voltage Gain Common Mode Rejection Ratio Unity Gain Bandwidth CONDITIONS TEMPERATURE TYPICAL UNITS fO = 10Hz +25oC 7 pA/qHz fO = 100Hz +25oC 3 pA/qHz fO = 1kHz +25oC 1.4 pA/qHz See Note 1 +25oC 0.005 % VOUT = 0 to 110V +25oC 128 dB Full 120 dB Full 95 dB Delta VCM = 110V (-3) 8 HA-5221 Ceramic Leadless Chip Carrier Packages (CLCC) J20.A MIL-STD-1835 CQCC1-N20 (C-2) 20 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE 0.010 S E H S D INCHES D3 SYMBOL j x 45o E3 B 0.010 S E F S 0.100 1.52 2.54 6, 7 0.088 1.27 2.23 - B - - - - - B1 0.022 0.028 0.56 0.71 2, 4 0.022 0.15 0.56 - 0.342 0.358 8.69 9.09 - D1 0.200 BSC 5.08 BSC D2 0.100 BSC 2.54 BSC D3 - 0.358 - E 0.342 0.358 8.69 j e -H- L3 - 0.006 h L 1.83 REF D e1 B1 0.072 REF B3 e 0.007 M E F S H S NOTES 0.060 E3 PLANE 1 -E- MAX 0.050 E2 PLANE 2 MIN A E1 A1 MILLIMETERS MAX A1 B2 E h x 45o A MIN 0.200 BSC 0.358 0.050 BSC 0.015 - 0.040 REF 0.020 REF - 9.09 2 9.09 - 5.08 BSC 0.100 BSC - - - 2.54 BSC - - 9.09 1.27 BSC 0.38 2 - - 2 1.02 REF 5 0.51 REF 5 L 0.045 0.055 1.14 1.40 - L1 0.045 0.055 1.14 1.40 - L2 0.075 0.095 1.91 2.41 - L3 0.003 0.015 0.08 0.38 - ND 5 5 NE 5 5 3 3 N 20 20 3 Rev. 0 5/18/94 -F- NOTES: B3 E1 E2 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. L2 B2 2. Unless otherwise specified, a minimum clearance of 0.015 inch (0.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) L1 3. Symbol “N” is the maximum number of terminals. Symbols “ND” and “NE” are the number of terminals along the sides of length “D” and “E”, respectively. D2 e1 D1 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer’s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension “A” controls the overall package thickness. The maximum “A” dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M-1982. 9. Controlling dimension: INCH. 9 HA-5221 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) F8.3A LEAD FINISH c1 MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE -D- -A- BASE METAL INCHES (c) SYMBOL E M -Bbbb S C A-B S -C- S1 - 0.200 - 5.08 - 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 α eA A A b2 b ccc M C A - B S e D S eA/2 NOTES b A L MAX A Q SEATING PLANE MIN M (b) D BASE PLANE MILLIMETERS MAX b1 SECTION A-A D S MIN c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 105o 90o 105o - 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. α 90o aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 - M - 0.0015 - 0.038 2, 3 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. N 8 8 8 Rev. 0 4/94 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 10 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029