ELPIDA HB54A5128FN-A75B

DATA SHEET
512MB Unbuffered DDR SDRAM DIMM
HB54A5128FN-A75B/B75B/10B (64M words × 64 bits, 2 Banks)
HB54A5129FN-A75B/B75B/10B (64M words × 72 bits, 2 Banks)
Features
The HB54A5128FN, HB54A5129FN are Double Data
Rate (DDR) SDRAM Module, mounted 256M bits DDR
SDRAM (HM5425801BTT) sealed in TSOP package,
and 1 piece of serial EEPROM (2k bits EEPROM) for
Presence Detect (PD).
The HB54A5128FN is
organized as 32M × 64 × 2 banks mounted 16 pieces
of 256M bits DDR SDRAM. The HB54A5129FN is
organized as 32M × 72 × 2 banks mounted 18 pieces
of 256M bits DDR SDRAM. Read and write operations
are performed at the cross points of the CK and the
/CK. This high-speed data transfer is realized by the 2
bits prefetch-pipelined architecture. Data strobe (DQS)
both for read and write are available for high speed and
reliable data bus design. By setting extended mode
register, the on-chip Delay Locked Loop (DLL) can be
set enable or disable. An outline of the products is
184-pin socket type package (dual lead out).
Therefore, it makes high density mounting possible
without surface mount technology. It provides common
data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the module board.
• 184-pin socket type package (dual lead out)
 Outline: 133.35mm (Length) × 31.75mm (Height) ×
4.00mm (Thickness)
 Lead pitch: 1.27mm
• 2.5V power supply (VCC/VCCQ)
• SSTL-2 interface for all inputs and outputs
• Clock frequency: 143MHz/133MHz/125MHz (max.)
• Data inputs, outputs and DM are synchronized with
DQS
• 4 banks can operate simultaneously and
independently (Component)
• Burst read/write operation
• Programmable burst length: 2, 4, 8
 Burst read stop capability
• Programmable burst sequence
 Sequential
 Interleave
• Start addressing capability
 Even and Odd
• Programmable /CAS latency (CL): 2, 2.5
• 8192 refresh cycles: 7.8µs (8192/64ms)
• 2 variations of refresh
 Auto refresh
 Self refresh
L
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Description
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Document No. E0087H40 (Ver. 4.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
This product became EOL in May, 2004.
Elpida Memory, Inc. 2001-2002
Hitachi, Ltd. 2000
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Ordering Information
Part number
Clock frequency
MHz (max.)
/CAS latency
Package
HB54A5128FN-A75B*1
HB54A5128FN-B75B*2
HB54A5128FN-10B*2
HB54A5129FN-A75B*1
HB54A5129FN-B75B*2
HB54A5129FN-10B*2
143 MHz
133 MHz
125 MHz
143 MHz
133 MHz
125 MHz
2.5
2.5
2.5
2.5
2.5
2.5
184-pin dual lead out socket Gold
type
Contact pad
Notes: 1. 133 MHz operation at /CAS latency = 2.
2. 100 MHz operation at /CAS latency = 2.
Pin Configurations
EO
Pin No.
1
VREF
DQ0
52 pin 53 pin
93 pin
92 pin
144 pin 145 pin 184 pin
Back side
Pin No.
47
48
Pin name
1
DQS8 (NC)*
L
2
Pin name
Front side
1 pin
A0
1
Pin No.
Pin name
Pin No.
Pin name
93
VSS
139
VSS
94
DQ4
140
DM8/DQS17
(NC)*1
3
VSS
49
CB2 (NC)*
95
DQ5
141
A10
4
DQ1
50
VSS
96
VCCQ
142
CB6 (NC)*1
5
DQS0
51
CB3
97
DM0/DQS9
143
VCCQ
98
DQ6
144
CB7 (NC)*1
6
DQ2
BA1 (NC)*
7
VCC
53
8
DQ3
54
9
NC
55
10
NC
56
11
VSS
57
12
DQ8
58
VSS
13
DQ9
59
BA0
14
DQS1
60
DQ35
15
VCCQ
61
DQ40
16
CK1
62
VCCQ
17
/CK1
63
/WE
18
VSS
64
DQ41
19
DQ10
65
20
DQ11
66
21
CKE0
67
22
VCCQ
68
DQ42
114
DQ20
23
DQ16
69
DQ43
115
A12
24
DQ17
70
VCC
116
VSS
25
DQS2
71
NC
117
DQ21
26
VSS
72
DQ48
118
A11
Pr
52
1
DQ32
99
DQ7
145
VSS
VCCQ
100
VSS
146
DQ36
DQ33
101
NC
147
DQ37
DQS4
102
NC
148
VCC
DQ34
103
NC
149
DM4/DQS13
od
104
VCCQ
150
DQ38
DQ12
151
DQ39
DQ13
152
VSS
107
DM1/DQS10
153
DQ44
108
VCC
154
/RAS
109
DQ14
155
DQ45
110
DQ15
156
VCCQ
/CAS
111
CKE1
157
/S0
VSS
112
VCCQ
158
/S1
DQS5
113
NC
159
DM5/DQS14
160
VSS
161
DQ46
162
DQ47
163
NC
164
VCCQ
Data Sheet E0087H40 (Ver. 4.0)
2
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106
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
27
A9
73
DQ49
119
DM2/DQS11
165
DQ52
28
DQ18
74
VSS
120
VCC
166
DQ53
29
A7
75
/CK2
121
DQ22
167
NC
30
VCCQ
76
CK2
122
A8
168
VCC
31
DQ19
77
VCCQ
123
DQ23
169
DM6/DQS15
32
A5
78
DQS6
124
VSS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
VSS
80
DQ51
126
DQ28
172
VCCQ
35
DQ25
81
VSS
127
DQ29
173
NC
36
DQS3
82
VCCID
128
VCCQ
174
DQ60
37
A4
83
DQ56
129
DM3/DQS12
175
DQ61
38
VCC
84
DQ57
130
A3
176
VSS
39
DQ26
85
VCC
131
DQ30
177
DM7/DQS16
40
DQ27
86
DQS7
132
VSS
178
DQ62
41
A2
87
DQ58
133
DQ31
179
DQ63
42
VSS
88
DQ59
134
CB4 (NC)*1
180
VCCQ
1
EO
34
A1
89
VSS
135
CB5 (NC)*
181
SA0
44
CB0 (NC)*1
90
NC
136
VCCQ
182
SA1
45
CB1 (NC)*1
91
SDA
137
CK0
183
SA2
46
VCC
92
SCL
138
/CK0
184
VCCSPD
L
43
Note: 1. The HB54A5128FN assign “NC”.
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Data Sheet E0087H40 (Ver. 4.0)
3
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Pin Description
Function
A0 to A12
Address input
Row address
Column address
BA0, BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
/RAS
Row address strobe command
/CAS
Column address strobe command
/WE
Write enable
/S0, /S1
Chip select
CKE0, CKE1
Clock enable
CK0 to CK2
Clock input
/CK0 to /CK2
Differential clock input
DQS0 to DQS8
Input and output data strobe
DM0 to DM8/DQS9 to DQS17
Input mask
SCL
Clock input for serial PD
SDA
Data input/output for serial PD
SA0 to SA2
VCC
VCCQ
VCCSPD
L
EO
Pin name
VREF
VCCID
NC
Serial address input
Power for internal circuit
Power for DQ circuit
Power for serial EEPROM
Input reference voltage
Pr
VSS
A0 to A12
A0 to A9
Ground
VCC identification flag
No connection
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Data Sheet E0087H40 (Ver. 4.0)
4
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
1
Serial PD Matrix*
Byte No.
0
1
Function described
Number of bytes utilized by module
manufacturer
Total number of bytes in serial PD
device
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
Hex value
Comments
1
0
0
0
0
0
0
0
80
128
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
1
1
07
SDRAM DDR
3
Number of row address
0
0
0
0
1
1
0
1
0D
13
Number of column address
0
0
0
0
1
0
1
0
0A
10
5
Number of DIMM banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
HB54A5128FN
0
1
0
0
0
0
0
0
40
64 bits
HB54A5129FN
0
1
0
0
1
0
0
0
48
72 bits
0
0
0
0
0
0
0
0
00
0 (+)
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
0
04
SSTL 2.5V
9
DDR SDRAM cycle time, CL = X
-A75B
0
1
1
1
0
0
0
0
70
CL = 2.5*5
-B75B
0
1
1
1
0
1
0
1
75
-10B
1
0
0
0
0
0
0
0
80
0
1
1
1
0
1
0
1
75
0.75ns*5
1
0
0
0
0
0
0
0
80
0.8ns*5
0
0
0
0
0
0
0
0
00
None
HB54A5129FN
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
7.8 µs
Self refresh
13
Primary SDRAM width
14
Error checking SDRAM width
HB54A5128FN
EO
4
7
10
Module data width continuation
SDRAM access from clock (tAC)
-A75B/B75B
L
-10B
11
DIMM configuration type
HB54A5128FN
15
17
18
19
0
0
1
0
0
0
08
×8
0
0
0
0
0
0
0
0
00

0
0
0
0
1
0
0
0
08
×8
0
0
0
0
0
0
0
1
01
1 CLK
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0E
2, 4, 8
0
0
0
1
0
0
04
4
0
0
1
1
0
0
0C
2, 2.5
0
0
0
0
0
1
01
0
0
0
0
0
0
21
SDRAM module attributes
0
0
1
0
0
0
22
SDRAM device attributes: General
1
1
0
0
0
0
23
Minimum clock cycle time at
CLX - 0.5
-A75B
0
1
1
1
0
1
1
0
1
0
0
0
Maximum data access time (tAC) from
clock at CLX - 0.5
0
-A75B/B75B
1
1
1
0
1
0
0
0
0
0
-B75B/10B
24
-10B
1
Data Sheet E0087H40 (Ver. 4.0)
5
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Pr
HB54A5129FN
SDRAM device attributes:
Minimum clock delay back-to-back
column access
SDRAM device attributes:
Burst length supported
SDRAM device attributes: Number of
banks on SDRAM device
SDRAM device attributes:
/CAS latency
SDRAM device attributes:
/CS latency
SDRAM device attributes:
/WE latency
0
1
0
02
1
0
0
20
Unbuffered
0
0
C0
± 0.2V
0
1
75
CL = 2*5
0
0
A0
0
1
75
0.75ns*5
0
0
80
0.8ns*5
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Byte No.
25
26
Function described
Bit7
Minimum clock cycle time at
0
CLX - 1
Maximum data access time (tAC) from
0
clock at CLX - 1
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
Hex value
0
0
0
0
0
0
0
00
0
0
0
0
0
0
0
00
Comments
27
Minimum row precharge time (tRP)
0
1
0
1
0
0
0
0
50
20ns
28
Minimum row active to row active
delay (tRRD)
0
0
1
1
1
1
0
0
3C
15ns
29
Minimum /RAS to /CAS delay (tRCD)
0
1
0
1
0
0
0
0
50
20ns
30
Minimum active to precharge time
(tRAS)
-A75B/B75B
0
0
1
0
1
1
0
1
2D
45ns
0
0
1
1
0
0
1
0
32
50ns
-10B
Module bank density
0
1
0
0
0
0
0
0
40
2 banks
256MB
32
Address and command setup time
before clock (tIS)
-A75B/B75B
1
0
0
1
0
0
0
0
90
0.9ns*5
1
0
1
1
0
0
0
0
B0
1.1ns*5
Address and command hold time after
clock (tIH)
1
-A75B/B75B
0
0
1
0
0
0
0
90
0.9ns*5
1
0
1
1
0
0
0
0
B0
1.1ns*5
0
1
0
1
0
0
0
0
50
0.5ns*5
0
1
1
0
0
0
0
0
60
0.6ns*5
0
1
0
1
0
0
0
0
50
0.5ns*5
0
1
1
0
0
0
0
0
60
0.6ns*5
0
0
0
0
0
0
0
0
00
Future use
0
1
0
0
0
0
0
1
41
65ns*5
0
1
0
0
0
1
1
0
46
70ns*5
0
1
0
0
1
0
1
1
4B
75ns*5
0
1
EO
31
-10B
33
-10B
Data input setup time before clock
(tDS)
-A75B/B75B
L
34
-10B
35
Data input hold time after clock (tDH)
-A75B/B75B
36 to 40
Superset information
41
Active command period (tRC)
-A75B/B75B
-10B
42
Auto refresh to active/
Auto refresh command cycle (tRFC)
-A75B/B75B
-10B
SDRAM tCK cycle max. (tCK max.)
0
0
44
Dout to DQS skew
-A75B/B75B
0
0
0
0
0
1
1
0
-10B
45
Data hold skew (tQHS)
-A75B/B75B
-10B
0
1
0
0
0
0
50
80ns*5
1
1
0
0
0
0
30
12ns*5
1
1
0
0
1
0
32
500ps*5
1
1
1
1
0
0
3C
600ps*5
1
1
0
1
0
1
75
750ps*5
1
0
0
0
0
0
A0
1000ps*5
0
0
00
Future use
0
0
00
Initial
46 to 61
Superset information
0
0
0
0
0
0
62
SPD revision
0
0
0
0
0
0
Data Sheet E0087H40 (Ver. 4.0)
6
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Pr
-10B
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Byte No.
Function described
Bit7
Bit6
Bit5 Bit4
Bit3
Bit2
Bit1 Bit0
Hex value
Comments
63
Checksum for bytes 0 to 62
HB54A5128FN-A75B
1
0
1
1
0
0
1
1
B3
179
HB54A5128FN-B75B
1
1
1
0
0
0
1
1
E3
227
HB54A5128FN-10B
1
0
1
0
1
0
0
0
A8
168
HB54A5129FN-A75B
1
1
0
0
0
1
0
1
C5
197
HB54A5129FN-B75B
1
1
1
1
0
1
0
1
F5
245
HB54A5129FN-10B
1
0
1
1
1
0
1
0
BA
186
HITACHI
Manufacturer’s JEDEC ID code
0
0
0
0
0
1
1
1
07
65 to 71
Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
00
72
Manufacturing location
×
×
×
×
×
×
×
×
××
*2 (ASCII-8bit
code)
73
Module part number
0
1
0
0
1
0
0
0
48
H
74
Module part number
0
1
0
0
0
0
1
0
42
B
75
Module part number
0
0
1
1
0
1
0
1
35
5
76
Module part number
0
0
1
1
0
1
0
0
34
4
77
Module part number
0
1
0
0
0
0
0
1
41
A
78
Module part number
0
0
1
1
0
1
0
1
35
5
79
Module part number
0
0
1
1
0
0
0
1
31
1
80
Module part number
0
0
1
1
0
0
1
0
32
2
81
Module part number
HB54A5128FN
0
0
1
1
1
0
0
0
38
8
HB54A5129FN
0
0
1
1
1
0
0
1
39
9
82
Module part number
0
1
0
0
0
1
1
0
46
F
83
Module part number
0
1
0
0
1
1
1
0
4E
N
84
Module part number
0
0
1
0
1
1
0
1
2D
—
85
Module part number
-A75B
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
0
0
1
1
0
0
0
1
31
1
0
0
1
1
0
1
1
1
37
7
0
0
1
1
0
0
0
0
30
0
0
0
1
1
0
1
0
1
35
5
0
1
0
0
0
0
1
0
42
B
0
1
0
0
0
0
1
0
42
B
0
0
1
0
0
0
0
0
20
(Space)
0
0
20
(Space)
0
0
30
Initial
0
0
20
(Space)
×
×
××
×
×
××
L
EO
64
-10B
87
Module part number
-A75B/B75B
88
Module part number
-A75B/B75B
-10B
-10B
89 to 90
Module part number
0
0
1
0
0
0
91
Revision code
0
0
1
1
0
0
92
Revision code
0
0
1
0
0
0
93
Manufacturing date
×
×
×
×
×
×
94
Manufacturing date
×
×
×
×
×
×
95 to 98
Module serial number
*3
99 to 127
Manufacturer specific data
*4
Data Sheet E0087H40 (Ver. 4.0)
7
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-10B
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86
Module part number
-A75B/B75B
Pr
-B75B
Year code
(BCD)
Week code
(BCD)
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High” These
SPD are based on JEDEC Committee Ballot JC-42.5-99-129.
2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on ASCII
code.)
3. Bytes 95 through 98 are assembly serial number.
4. All bits of 99 through 127 are not defined (“1” or “0”).
5. These specifications are defined based on component specification, not module.
Block Diagram (HB54A5128FN)
/S0
RS
RS
/S1
DM0/DQS9
DQS0
8
RS
DQ0 to DQ7
EO
DQS
/CS
DQ
D0
DM
DQS
/CS
DQ
D8
DM
RS
RS
DM1/DQS10
DQS1
8
RS
DQ8 to DQ15
DQS
/CS
DQ
D1
DM
DQS
/CS
DQ
D9
DM
RS
RS
DM2/DQS11
DQS2
8
RS
DQ16 to DQ23
DQS
/CS
DQ
D2
DM
DQS
/CS
DM
DQ
D10
RS
RS
DM3/DQS12
DQS3
8
RS
L
DQ24 to DQ31
DQS
/CS
DQ
D3
DM
DQS
/CS
DQ
D11
DM
RS
RS
DM4/DQS13
DQS4
8
RS
DQ32 to DQ39
DQS
/CS
DQ
D4
DM
DQS
/CS
DQ
D12
DM
RS
RS
DM5/DQS14
DQS5
DQS
/CS
DM
DQS
/CS
Pr
8
RS
DQ40 to DQ47
D5
DQ
DM
D13
DQ
RS
RS
DM6/DQS15
DQS6
8
RS
DQ48 to DQ55
DQS
/CS
DQ
D6
DM
DQS
/CS
DM
DQ
D14
RS
RS
DM7/DQS16
DQS7
8
RS
* D0 to D15: HM5425801
U0: 2k bits EEPROM
RS: 22Ω
/CS
DQ
D7
DM
DQS
/CS
DQ
D15
A0 to A12
BA0, BA1
A0 to A12 (D0 to D15)
BA0, BA1 (D0 to D15)
/RAS
/RAS (D0 to D15)
/CAS
/CAS (D0 to D15)
/WE (D0 to D15)
VCC, VCCQ
D0 to D15
/WE
VREF
D0 to D15
CKE0
VSS
D0 to D15
CKE1
VCCID
DM
od
DQ56 to DQ63
DQS
CKE (D0 to D7)
CKE (D8 to D15)
SCL
Clock wiring
Clock input
DDR SDRAMS
CK0/ /CK0
4DRAM loads
CK1/ /CK1
6DRAM loads
CK2/ /CK2
6DRAM loads
SCL
t
uc
Serial PD
open
SDA
SDA
U0
A0
Note: Wire per Clock loading table/Wiring diagrams.
Data Sheet E0087H40 (Ver. 4.0)
8
A1
A2
SA0 SA1 SA2
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Block Diagram (HB54A5129FN)
/S0
RS
RS
/S1
DM0/DQS9
DQS0
8
RS
DQ0 to DQ7
DQS
/CS
DQ
D0
DM
DQS
/CS
DQ
D9
DM
RS
RS
DM1/DQS10
DQS1
8
RS
DQ8 to DQ15
DQS
/CS
DQ
D1
DM
DQS
/CS
DQ
D10
DM
RS
RS
DM2/DQS11
DQS2
8
RS
DQ16 to DQ23
DQS
/CS
DQ
D2
DM
DQS
/CS
DM
DQ
D11
RS
RS
DM3/DQS12
DQS3
EO
8
RS
DQ24 to DQ31
DQS
/CS
DQ
D3
DM
DQS
/CS
DM
DQ
D12
RS
RS
DM4/DQS13
DQS4
8
RS
DQ32 to DQ39
DQS
/CS
DQ
D4
DM
DQS
/CS
DQ
D13
DM
RS
RS
DM5/DQS14
DQS5
8
RS
DQ40 to DQ47
DQS
/CS
DQ
D5
DM
DQS
/CS
DM
DQ
D14
RS
RS
DM6/DQS15
DQS6
L
8
RS
DQ48 to DQ55
DQS
/CS
DQ
D6
DM
DQS
/CS
DQ
D15
DM
RS
RS
DM7/DQS16
DQS7
8
RS
DQ56 to DQ63
DQS
/CS
DQ
D7
DM
DQS
/CS
DM
DQ
D16
RS
RS
DM8/DQS17
Pr
DQS8
8
RS
CB0 to CB7
DQS
/CS
DQ
D8
DM
/CS
DQ
D17
D0 to D17
A0 to A12 (D0 to D17)
BA0, BA1 (D0 to D17)
/RAS (D0 to D17)
/CAS
/CAS (D0 to D17)
/WE
/WE (D0 to D17)
od
/RAS
VREF
D0 to D17
CKE0
VSS
D0 to D17
CKE1
VCCID
DM
A0 to A12
BA0, BA1
* D0 to D17: HM5425801
U0: 2k bits EEPROM
RS: 22Ω
VCC, VCCQ
DQS
CKE (D0 to D8)
CKE (D9 to D17)
Serial PD
open
SCL
Clock wiring
Clock input
DDR SDRAMS
CK0/ /CK0
6DRAM loads
CK1/ /CK1
6DRAM loads
CK2/ /CK2
6DRAM loads
SCL
SDA
SDA
U0
A0
Data Sheet E0087H40 (Ver. 4.0)
9
A2
SA0 SA1 SA2
Notes:
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
t
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Note: Wire per Clock loading table/Wiring diagrams.
A1
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Logical Clock Net Structure
6DRAM loads
CK
5DRAM loads
DRAM1
DRAM2
R = 120Ω
DRAM1
R = 120Ω
DRAM3
DRAM2
DRAM3
DIMM
connector
DIMM
connector
DRAM4
Capacitance
DRAM5
DRAM5
DRAM6
DRAM6
/CK
EO
4DRAM loads
3DRAM loads
DRAM1
DRAM2
R = 120Ω
R = 120Ω
Capacitance
DIMM
connector
L
Capacitance
Capacitance
DRAM5
DRAM5
DRAM6
Capacitance
1DRAM loads
DRAM1
Capacitance
Pr
R = 120Ω
Capacitance
R = 120Ω
Capacitance
DIMM
connector
Capacitance
DRAM3
DIMM
connector
2DRAM loads
DRAM1
Capacitance
DRAM3
DIMM
connector
Capacitance
Capacitance
DRAM5
od
Capacitance
Capacitance
t
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Data Sheet E0087H40 (Ver. 4.0)
10
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs
and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs
and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred
to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK
and the /CK.
/S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored.
However, internal operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the
combinations of their voltage levels. See "Command operation".
EO
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of
the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY9) is loaded via
the A0 to the A9 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle.
This column address becomes the starting address of a burst operation.
L
A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write
command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low
when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High
when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is
disabled.
BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2
and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If
BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected.
od
Pin Functions (2)
Pr
CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are
entered when the CKE is driven Low and exited when it resumes to High.
The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK
rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with
proper hold time tIH.
DQ, CB (input and output pins): Data are input to and output from these pins.
DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input).
DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of
DQS and VREF
t
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VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output
buffer.)
VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM).
VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H10).
Data Sheet E0087H40 (Ver. 4.0)
11
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Symbol
Value
Unit
Note
Voltage on any pin relative to VSS
VT
–1.0 to +4.6
V
1
Supply voltage relative to VSS
VCC, VCCQ
–1.0 to +4.6
V
1
Short circuit output current
IOUT
50
mA
Power dissipation
HB54A5128FN
PT
8
W
HB54A5129FN
PT
9
W
Operating temperature
Topr
0 to +55
°C
Storage temperature
Tstg
–50 to +100
°C
EO
Parameter
Notes: 1. Respect to VSS.
DC Operating Conditions (TA = 0 to +55°C)
Parameter
Symbol
min.
Typ
max.
Unit
Notes
Supply voltage
VCC, VCCQ
2.3
2.5
2.7
V
1, 2
VSS
0
0
0
V
VREF
1.15
1.25
1.35
V
1
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
1
VIH
VREF + 0.18
—
VCCQ + 0.3
V
1, 3
L
Input reference voltage
DC Input high voltage
DC Input low voltage
VIL
–0.3
—
VREF – 0.18
V
1, 4
DC Input signal voltage
VIN (dc)
–0.3
—
VCCQ + 0.3
V
5
DC differential input voltage
VSWING (dc) 0.36
—
VCCQ + 0.6
V
6
All parameters are referred to VSS, when measured.
VCCQ must be lower than or equal to VCC.
VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (dc) specifies the allowable dc execution of each differential input.
VSWING (dc) specifies the input differential voltage required for switching.
t
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Pr
Notes: 1.
2.
3.
4.
5.
6.
Data Sheet E0087H40 (Ver. 4.0)
12
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
DC Characteristics 1 (TA = 0 to 55°C, VCC, VCCQ = 2.5V ± 0.2V, VSS = 0V)
Parameter
Symbol
Operating current (ACTV-PRE) ICC0
ICC1
Idle power down standby
current
ICC2P
Idle standby current
ICC2N
Active power down standby
current
ICC3P
Active standby current
ICC3N
Operating current
(Burst read operation)
ICC4R
× 72
max.
max.
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
-A75B
-B75B
-10B
1200
1120
960
1640
1520
1360
288
240
192
640
560
480
400
320
240
800
720
640
2200
2080
1960
2040
1920
1800
2040
1960
1760
1350
1260
1080
1845
1710
1530
324
270
216
720
630
540
450
360
270
900
810
720
2475
2340
2205
2295
2160
2025
2295
2205
1980
48
54
L
EO
Operating current (ACTVREAD-PRE)
× 64
Grade
ICC4W
Auto refresh current
ICC5
Self refresh current
ICC6
Test condition
mA
CKE ≥ VIH, tRC = min. 1, 2, 5
mA
CKE ≥ VIH, BL = 2,
CL = 2.5, tRC = min.
1, 2, 5
mA
CKE ≤ VIL
4
mA
CKE ≥ VIH, /CS ≥ VIH 4
mA
CKE ≤ VIL
mA
CKE ≥ VIH, /CS ≥ VIH
3
tRAS = max.
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
CKE ≥ VIH, BL = 2,
CL = 2.5
1, 2, 5, 6
mA
tRFC = min.,
Input ≤ VIL or ≥ VIH
mA
Input ≥ VCC – 0.2V
Input ≤ 0.2V.
Notes
3
These ICC data are measured under condition that DQ pins are not connected.
One bank operation.
One bank active.
All banks idle.
Command/Address transition once per one cycle.
Data/Data mask transition twice per one cycle.
The ICC data on this table are measured with regard to tCK = min. in general.
od
Notes. 1.
2.
3.
4.
5.
6.
7.
Pr
Operating current
(Burst write operation)
Unit
DC Characteristics2 (TA = 0 to 55°C, VCC, VCCQ = 2.5V ± 0.2V, VSS = 0V)
Symbol
min.
Input leakage current
ILI
–10
Output leakage current
ILO
–10
max.
Unit
Test condition
10
µA
VCC ≥ VIN ≥ VSS
10
µA
VCC ≥ VOUT ≥ VSS
Output high voltage
VOH
VTT + 0.76
—
V
Output low voltage
VOL
—
VTT – 0.76
V
Data Sheet E0087H40 (Ver. 4.0)
13
Notes
t
uc
Parameter
IOH (max.) = –15.2mA
IOL (min.) = 15.2mA
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Pin Capacitance (TA = 25°C, VCC, VCCQ = 2.5V ± 0.2V)
[HB54A5128FN]
Parameter
Symbol
Pins
min.
max.
Unit
Notes
Input capacitance
CI1
Address, Cont.

110
pF
1
Input capacitance
CI2
CKE, /S

75
pF
1
Input capacitance
CI3
CK, /CK

79
Data and DQS input/output
capacitance
CO
DQ, DQS

20
pF
1, 2
Parameter
Symbol
Pins
min.
max.
Unit
Notes
Input capacitance
CI1
Address, Cont.

117
pF
1
pF
1
pF
1, 2
[HB54A5129FN]
EO
Input capacitance
CI2
CKE, /S

82
Input capacitance
CI3
CK, /CK

79
Data and DQS input/output
capacitance
CO
DQ, DQS, CB

20
Notes: 1. These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, ∆VOUT = 0.2V.
2. Dout circuits are disabled.
Timing Parameter Measured in Clock Cycle for Unbuffered DIMM
L
Parameter
Number of clock cycle
Symbol
min.
Write to pre-charge command delay (same bank)
tWPD
3 + BL/2
Read to pre-charge command delay (same bank)
tRPD
BL/2
Write to read command delay (to input all data)
tWRD
2 + BL/2
Pr
tBSTW
2
(CL = 2.5)
tBSTW
3
tBSTZ
2
tBSTZ
2.5
tRWD
2 + BL/2
tRWD
3 + BL/2
tHZP
2
tHZP
2.5
tWCD
1
tWR
2
tDMD
0
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5)
Read command to write command delay (to output all data)
(CL = 2)
(CL = 2.5)
Pre-charge command to High-Z
(CL = 2)
(CL = 2.5)
Write command to data in latency
Write recovery
t
uc
DM to data in latency
od
Burst stop command to write command delay
(CL = 2)
max.
Register set command to active or register set command
tMRD
2
Self refresh exit to non-read command
tSNR
10
Self refresh exit to read command
tSRD
200
Power down entry
tPDEN
Power down exit to command input
tPDEX
CKE minimum pulse width
tCKEPW
Data Sheet E0087H40 (Ver. 4.0)
14
1
1
1
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
Physical Outline
Unit: mm
133.35 ± 0.15
128.95
4.00 max
4.00 min
(DATUM -A-)
(64.48)
2.30
Component area
(Front)
1
92
EO
B
A
64.77
1.27 ± 0.10
49.53
R 2.00
3.00 min
Detail A
Detail B
(DATUM -A-)
1.27 typ
6.62
0.20 ± 0.15
Pr
2.50 ± 0.20
31.75 ± 0.15
Component area
(Back)
17.80
184
L
4.00 ± 0.10
93
10.00
2 – φ 2.50 ± 0.10
2.175
R 0.90
1.00 ± 0.05
3.80
6.35
1.80 ± 0.10
od
Note: Tolerance on all dimensions ± 0.13 unless otherwise specified.
ECA-TS2-0040-01
t
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Data Sheet E0087H40 (Ver. 4.0)
15
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on
these components to prevent damaging them.
In particular, do not push module cover or drop the modules in order to protect from mechanical defects,
which would be electrical defects.
When re-packing memory modules, be sure the modules are not touching each other.
Modules in contact with other modules may cause excessive mechanical stress, which may damage the
modules.
MDE0202
NOTES FOR CMOS DEVICES
EO
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
2
L
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
3
od
Pr
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
STATUS BEFORE INITIALIZATION OF MOS DEVICES
t
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Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0087H40 (Ver. 4.0)
16
HB54A5128FN, HB54A5129FN-A75B/B75B/10B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
EO
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
L
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
Pr
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
t
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od
Data Sheet E0087H40 (Ver. 4.0)
17