Military & Space Products 32K x 8 STATIC RAM HC6856 FEATURES RADIATION OTHER • Fabricated with RICMOS™ IV Bulk 0.8 µm Process (Leff = 0.65 µm) • Listed on SMD #5962-92153. Available as MIL-PRF-38535 QML Class Q and Class V • Total Dose Hardness through 1x106 rad(SiO2) • Read/Write Cycle Times ≤ 30 ns (Typical) ≤ 40 ns (-55 to 125°C) • Neutron Hardness through 1x1014 cm-2 • Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s • Standby Current of 20 µA (typical) • Asynchronous Operation • Soft Error Rate of <1x10-10 upsets/bit-day • CMOS or TTL Compatible I/O • Dose Rate Survivability through 1x1012 rad(Si)/s • Single 5 V ± 10% Power Supply • Latchup Free • Packaging Options - 36-Lead Flat Pack (0.630 in. x 0.650 in.) - 28-Lead Flat Pack (0.530 in. x 0.720 in.) - 28-Lead DIP, MIL-STD-1835, CDIP2-T28 GENERAL DESCRIPTION The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environments. The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply. The RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 50 mW/MHz in operation, and less than 5 mW/MHz in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 20 ns. Honeywell’s enhanced RICMOS™ IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOS™ IV process is a 5-volt, twin-well CMOS technology with a 170 Å gate oxide and a minimum drawn feature size of 0.8 µm (0.65 µm effective gate length—Leff). Additional features include a three layer interconnect metalization and a lightly doped drain (LDD) structure for improved short channel reliability. High resistivity cross-coupled polysilicon resistors have been incorporated for single event upset hardening. HC6856 FUNCTIONAL DIAGRAM A:0-8,12-13 • • • Row Decoder 11 32,768 x 8 Memory Array CE • • • Column Decoder Data Input/Output NCS NWE 8 DQ:0-7 8 WE • CS • CE NWE • CS • CE • OE NOE (0 = high Z) CS • CE A:9-11,14 Signal 1 = enabled # Signal All controls must be enabled for a signal to pass. (#: number of buffers, default = 1) 4 SIGNAL DEFINITIONS A: 0-14 Address input pins (A) which select a particular eight-bit word within the memory array. DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level it forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers. If this signal is not used it must be connected to VSS. NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level it allows normal read operation. NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be connected to VSS. CE Chip enable, when at a high level allows normal operation. When at a low level it forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers. If this signal is not used it must be connected to VDD. TRUTH TABLE NCS CE NWE NOE MODE DQ L H H L Read Data Out L H L X Write Data In H X XX XX Deselected High Z X L XX XX Disabled High Z 2 Notes: X: VI=VIH or VIL XX: VSS≤VI≤VDD NOE=H: High Z output state maintained for NCS=X, CE=X, NWE=X HC6856 RADIATION CHARACTERISTICS Total Ionizing Radiation Dose The RAM will meet any functional or electrical specification after exposure to a radiation pulse of ≤ 50 ns duration up to 1x1012 rad(Si)/s, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. The RAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125°C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 keV X-ray radiation. Transistor gate threshold shift correlations have been made between 10 keV X-rays applied at a dose rate of 1x105 rad(SiO2)/min at T = 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. The RAM will meet any functional or timing specification after a total neutron fluence of up to 1x1014 cm-2 applied under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Transient Pulse Ionizing Radiation Soft Error Rate The RAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse of ≤1 µs duration up to 1x109 rad(Si)/s, when applied under recommended operating conditions. To ensure validity of all specified performance parameters before, during, and after radiation (timing degradation during transient pulse radiation is ≤10%), it is suggested that a minimum of 0.8 µF per part of stiffening capacitance be placed between the package (chip) VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through or valid stored data requirements, the capacitance specification can be reduced to a minimum of 0.1 µF per part. The RAM is capable of soft error rate (SER) performance of <1x10-10 upsets/bit-day, under recommended operating conditions. This hardness level is defined by the Adams 10% worst case cosmic ray environment. Neutron Radiation Latchup The RAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the RICMOS™ p-epi on p+ substrate process and use of proven design techniques, such as double guardbanding, ensure latchup immunity. RADIATION HARDNESS RATINGS (1) Test Conditions Total Dose ≥1x106 rad(SiO2) TA=25°C Transient Dose Rate Upset (3) ≥1x109 rad(Si)/s Pulse width≤1 µs Transient Dose Rate Survivability ≥1x1012 rad(Si)/s Pulse width≤50 ns, X-ray, VDD=6.6 V, TA=25°C Soft Error Rate: Level A <1x10-9 (4) Level Z <1x10-10 Neutron Fluence (1) (2) (3) (4) Units Limits (2) Parameter ≥1x1014 upsets/bit-day Adams 10% worst case environment N/cm2 1 MeV equivalent energy, Unbiased, TA=25°C Device will not latch up due to any of the specified radiation exposure conditions. Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55°C to 125°C. Suggested stiffening capacitance specifications for optimum expected dose rate upset performance is stated above in the text. SER <1x10-10 u/b-d from -55 to 80°C. 3 HC6856 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter Min Max Units VDD Positive Supply Voltage (2) -0.5 7.0 V VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V TSTORE Storage Temperature (Zero Bias) -65 150 °C TSOLDER Soldering Temperature • Time 270•5 °C•s PD Total Package Power Dissipation (3) 2.5 W IOUT DC or Average Output Current 25 mA VPROT ESD Input Protection Voltage (4) ΘJC Thermal Resistance (Jct-to-Case) TJ 2000 V 28 FP/36 FP 2 °C/W 28 DIP 10 °C/W 175 °C Junction Temperature (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab. RECOMMENDED OPERATING CONDITIONS Description Parameter Symbol Min Typ Max Units VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 V TA Ambient Temperature -55 25 125 °C VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 V CAPACITANCE (1) Worst Case Symbol Parameter CI Input Capacitance CO Output Capacitance Typical Max Units Test Conditions 4 6 pF VI=VDD or VSS, f=1 MHz 6.5 8 pF VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only. DATA RETENTION CHARACTERISTICS Symbol Parameter (2) Typical (1) VDR Data Retention Voltage (3) 2.0 IDR Data Retention Current 150 Worst Case Min Units Test Conditions Max 2.5 V 400 µA NCS=VDR VI=VDR or VSS NCS=VDD=VDR VI=VDR or VSS (1) Typical operating conditions: TA= 25°C, pre-radiation. (2) Worst case operating conditions: TA= -55°C to +125°C, post total dose at 25°C. (3) To maintain valid data storage during transient radiation, VDD must be held within the recommended operating range. 4 HC6856 DC ELECTRICAL CHARACTERISTICS Symbol Typical Worst Case (2) Units (1) Min Max Parameter Test Conditions (3) IDDSB1 Static Supply Current 0.02 1.2 mA IDDSB2 Static Supply Current with Chip Disabled 0.02 1.2 mA IDDOPW Dynamic Supply Current, Selected (Write) 5.5 7.5 mA IDDOPR Dynamic Supply Current, Selected (Read) 4.5 6.5 mA VIH=VDD IO=0 VIL=VSS Inputs Stable CE=VSS or NCS=VDD IO=0, VSS≤ VI≤VDD (4) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (5) f=1 MHz, IO=0, CE=VIH=VDD NCS=VIL=VSS (5) II Input Leakage Current ±0.05 -5 +5 µA VSS≤VI≤VDD IOZ Output Leakage Current ±0.1 -10 10 µA VSS≤VIO≤VDD Output=high Z VIL Low-Level InputVoltage VIH High-Level Input Voltage VOL Low-Level Output Voltage VOH High-Level Output Voltage CMOS TTL 1.9 1.3 CMOS TTL 3.0 1.7 0.8 0.7xVDD 2.2 0.2 4.8 (1) (2) (3) (4) (5) 0.3xVDD 0.4 0.05 4.2 VDD-0.05 V V VDD=4.5V VDD=4.5V V V VDD=5.5V VDD=5.5V V V VDD=4.5V, IOL=10 mA VDD=4.5V, IOL=200 µA V V VDD=4.5V, IOH=-5 mA VDD=4.5V, IOH=-200 µA Typical operating conditions: VDD= 5.0 V,TA=25°C, pre-radiation. Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55°C to +125°C, post total dose at 25°C. Input high = VIH ≥ VDD-0.3V, input low =VIL ≤ 0.3V Guaranteed but not tested. All inputs switching. DC average current. 2.9 V Vref1 + - Valid high output 249Ω DUT output Vref2 + - Valid low output CL >50 pF* *CL = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ Tester Equivalent Load Circuit 5 HC6856 READ CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical -55 to 125°C (2) Min 40 Units Max TAVAVR Address Read Cycle Time 18 ns TAVQV Address Access Time 18 TAXQX Address Change to Output Invalid Time 15 TSLQV Chip Select Access Time 20 TSLQX Chip Select Output Enable Time 20 TSHQZ Chip Select Output Disable Time 6 10 ns TEHQV Chip Enable Access Time 20 40 ns TEHQX Chip Enable Output Enable Time 20 TELQZ Chip Enable Output Disable Time 6 10 ns TGLQV Output Enable Access Time 4 10 ns TGLQX Output Enable Output Enable Time 3 TGHQZ Output Enable Output Disable Time 4 40 5 ns ns 40 16 ns ns 16 ns 0 ns 10 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF, or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF (typical). (2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, post total dose at 25°C. TAVAVR ADDRESS TAVQV TAXQX TSLQV NCS TSLQX DATA OUT TSHQZ HIGH IMPEDANCE DATA VALID TEHQX TEHQV CE TELQZ TGLQX TGLQV TGHQZ NOE (NWE = high) 6 HC6856 WRITE CYCLE AC TIMING CHARACTERISTICS (1) Symbol Parameter Typical (2) Worst Case (3) SER <1E-9 (4) SER <1E-10 Min Max Min Max Units TAVAVW Write Cycle Time (5) 30 40 60 ns TWLWH Write Enable Write Pulse Width 25 35 55 ns TSLWH Chip Select to End of Write Time 25 35 55 ns TDVWH Data Valid to End of Write Time 20 30 50 ns TAVWH Address Valid to End of Write Time 25 35 55 ns TWHDX Data Hold Time after End of Write Time 0 0 0 ns TAVWL Address Valid Setup to Start of Write Time 0 0 0 ns TWHAX Address Valid Hold after End of Write Time 0 0 0 ns TWLQZ Write Enable to Output Disable Time 5 0 TWHQX Write Disable to Output Enable Time 15 5 5 ns TWHWL Write Disable to Write Enable Pulse Width 4 5 5 ns TEHWH Chip Enable to End of Write Time 25 35 55 ns 10 0 10 (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading0 pF, or equivalent capacitive load of 5 pF for TWLQZ. (2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation. (3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C. (4) SER ≤1E-10 u/b-d from -55 to 80°. (5) TAVAVW= TWLWH + TWHWL TAVAVW ADDRESS TAVWH TWHAX TAVWL TWHWL TWLWH NWE TWLQZ DATA OUT TWHQX HIGH IMPEDANCE TDVWH DATA IN DATA VALID TSLWH NCS TEHWH CE 7 TWHDX ns HC6856 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle Write Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high. The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. Consecutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. For an address activated read cycle, NCS and CE must be valid prior to or coincident with the activating address edge transition(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum address activated read cycle time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data outputs will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. The write mode can be controlled via three different control signals: NWE, NCS, and CE. All three modes of control are similar except the NCS and CE controlled modes actually disable the RAM during the write recovery pulse. Only the NWE controlled mode is shown in the table and diagram on the previous page for simplicity; however, each mode of control provides the same write cycle timing characteristics. Thus, some of the parameter names referenced below are not shown in the write cycle table or diagram, but indicate which control pin is in control as it switches high or low. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS; however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TSHQZ time following a disabling NCS edge transition. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecutive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/ TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data outputs will not become valid until TAVQV time following the address edge transition. Data outputs will enter a high impedance state TELQZ time following a disabling CE edge transition. 8 HC6856 TESTER AC TIMING CHARACTERISTICS TTL I/O Configuration CMOS I/O Configuration 3V Input Levels* 0V VDD-0.4V 0.4 V High Z 3.4 V High Z 2.4 V High Z = 2.9V VDD/2 0.5 V 1.5 V Output Sense Levels VDD-0.5 V 1.5 V VDD/2 VDD-0.4V 0.4 V High Z 3.4 V High Z 2.4 V High Z = 2.9V * Input rise and fall times <1 ns/V QUALITY AND RADIATION HARDNESS ASSURANCE QML devices offer ease of procurement by eliminating the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. Honeywell maintains a high level of product integrity through process control, utilizing statistical process control, a complete “Total Quality Assurance System,” a computer data base process performance tracking system, and a radiation hardness assurance strategy. RELIABILITY Honeywell understands the stringent reliability requirements that space and defense systems require and has extensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOS™ process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitoring key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and continuing through product qualification and screening. SCREENING LEVELS In addition, the reliability of the RICMOS™ process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dynamic life test conditions. Packages are qualified for product use after undergoing Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The product is qualified by following a screening and testing flow to meet the customer’s requirements. Quality conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product. Honeywell offers several levels of device screening to meet your system needs. “Engineering Devices” are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MILSTD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are available per the applicable Standard Military Drawing (SMD). 9 HC6856 PACKAGING The 32K x 8 SRAM is offered in a custom 36-lead flat pack (FP), 28-Lead FP, or standard 28-lead DIP. Each package is constructed of multilayer ceramic (Al2O3) and features internal power and ground planes. The 36-lead FP also features a non-conductive ceramic tie bar on the lead frame. The purpose of the tie bar is to allow electrical testing of the device, while preserving the lead integrity during shipping and handling, up to the point of lead forming and insertion. Ceramic chip capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. These capacitors attach directly to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. All NC (no connect) pins must be connected to either VDD, VSS or an active driver to prevent charge build up in the radiation environment. 28-LEAD DIP & FP PINOUT 36-LEAD FLAT PACK PINOUT A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 VDD NWE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Top View VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 NC VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 Top View 36-LEAD FLAT PACK (22017194-001) E 1 b (width) D G Top Side e (pitch) H L L Optional Standoff Ceramic Body A J I 0.004 C X Optional Capacitors N VDD VSS VDD Y 1 O V W T P R M All dimensions are in inches [1] VSS 1 F NonConductive Tie-Bar Kovar Lid [3] U 10 S A b C D E e F G H I J L 0.095 ± 0.010 0.008 ± 0.002 0.005 to 0.0075 0.650 ± 0.010 0.630 ± 0.007 0.025 ± 0.002 [2] 0.425 ± 0.005 [2] 0.525 ± 0.005 0.135 ± 0.005 0.030 ± 0.005 0.080 typ. 0.285 ± 0.015 M N O P R S T U V W X Y 0.008 ± 0.003 0.050 ± 0.010 0.090 ref 0.015 ref 0.075 ref 0.113 ± 0.010 0.050 ref 0.030 ref 0.080 ref 0.005 ref 0.450 ref 0.400 ref [1] Parts delivered with leads unformed [2] At tie bar [3] Lid tied to VSS VSS VDD NWE CE A13 A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS HC6856 28-LEAD FLAT PACK (22017362-001) 1 b (width) e S (pitch) Z L VSS All dimensions in inches VDD 1 BOTTOM VIEW D TOP VIEW F Optional capacitors in cutout VDD E X U Y W Q A G Kovar Lid [4] Cutout Area Ceramic Body E2 V C Lead Alloy 42 [1] [2] [3] [4] E3 A b C D e E E2 E3 F G L Q S U V W X Y Z 0.135 ± 0.015 0.015 ± 0.002 0.004 to 0.009 0.720 ± 0.008 0.050 ± 0.005 [1] 0.530 ± 0.008 0.420 ± 0.008 0.055 ref 0.650 ± 0.005 [2] 0.050 ± 0.005 0.295 min [3] 0.026 to 0.045 0.035 ± 0.010 0.065 ref 0.300 ref 0.050 ref 0.030 ref 0.100 ref 0.080 ref BSC - Basic lead spacing between centers Where lead is brazed to package Parts delivered with leads unformed Lid connected to VSS 28-LEAD DIP (22017502-001) For 28-Lead DIP description, see MIL-STD-1835, Type CDIP2-T28, Config. C, Dimensions D-10 F16 F7 F6 F5 F4 F3 F2 F8 F13 F14 F1 F1 F1 R R R R R R R R R R R R R NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQO DQ1 DQ2 VDD VSS VSS VDD NWE* CE* A13* A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 STATIC BURN-IN DIAGRAM VDD VDD R R R R R R R R R R R R R R VSS R F0 F17 F15 F12 F11 F10 F17 F9 F17 F1 F1 F1 F1 F1 R R R R R R R R R R R R NC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 VSS VDD A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQO DQ1 DQ2 VDD VSS 32K x 8 SRAM VSS 32K x 8 SRAM DYNAMIC BURN-IN DIAGRAM VSS VDD NWE* CE* A13* A8 A9 A11 NOE A10 NCS DQ7 DQ6 DQ5 DQ4 DQ3 VDD VSS 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 R R R R R R R R R R R R R R VSS VDD = 6.5V, R ≤ 10 KΩ, VIH = VDD, VIL = VSS Ambient Temperature ≥ 125 °C, F0 ≥ 100 KHz Sq Wave Frequency of F1 = F0/2, F2 = F0/4, F3 = F0/8, etc. VDD = 5.5V, R ≤ 10 KΩ Ambient Temperature ≥ 125 °C NOTE — *Denotes package pinout option dependent (28-Lead DIP/FP diagrams not shown but have similar connections) 11 HC6856 ORDERING INFORMATION (1) H 6856/1 C PART NUMBER Pinout options (2) PROCESS C=CMOS SOURCE H=HONEYWELL X H Q SCREEN LEVEL (1) V=QML Class V Q=QML Class Q S=Level S B=Level B E=Engr Device (4) PACKAGE DESIGNATION W=36-Lead FP X=36-Lead FP, with standoff Y=36-Lead FP, with standoff & caps N=28-Lead FP R=28-Lead DIP - = Bare Die (No Package) Z SOFT ERROR RATE Z=<1x10-10 upsets/bit-day A=<1x10-9 upsets/bit-day (3) C=<1x10-7 upsets/bit-day - =No SER Guaranteed TOTAL DOSE HARDNESS R=1x105rad(SiO2) F=3x105 rad(SiO2) H=1x106 rad(SiO2) N=No Level Guaranteed 40 C SPEED (5) 60 ns 40 ns 35 ns INPUT BUFFER TYPE C=CMOS Level T=TTL Level (1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information. (2) Pinout options: 36-Lead FP 28-Lead FP & DIP pin 32 pin 33 pin 34 HC6856/1 A13 CE NWE JEDEC Pinout HC6856/2 CE NWE A13 N/A (3) SER <1E-10 u/b-d from -55 to 80°C. (4) Engineering Device description: Parameters are tested from -55 to 125°C, 24 hr burn-in, no radiation guaranteed. (5) Only specified for Engineering Devices. Number defines worst case maximum Write Cycle time in nano-seconds (ns). Contact Factory with other needs. To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Helping You Control Your World 900049 2/96 12