MA9264 MA9264 Radiation Hard 8192x8 Bit Static RAM Replaces June 1999 version, DS3692-6.0 DS3692-7.0 January 2000 The MA9264 64k Static RAM is configured as 8192x8 bits and manufactured using CMOS-SOS high performance, radiation hard, 1.5µm technology. The design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. Address input buffers are deselected when chip select is in the HIGH state. FEATURES See Application Note “Overview of the Dynex Semiconductor Radiation Hard 1.5µm CMOS/SOS SRAM Range”. ■ Transient Upset >1011 Rad(Si)/sec Operation Mode CS CE OE WE I/O Read L H L H D OUT Write L H X L D IN Output Disable L H H H High Z Standby H X X X High Z X L X X X ■ 1.5µm CMOS-SOS Technology ■ Latch-up Free ■ Fast Access Time 70ns Typical ■ Total Dose 106 Rad(Si) ■ SEU 4.3 x 10-11 Errors/bitday ■ Single 5V Supply Power ■ Three State Output ■ Low Standby Current 100µA Typical ■ -55°C to +125°C Operation ISB1 ■ All Inputs and Outputs Fully TTL or CMOS Compatible ISB2 ■ Fully Static Operation Figure 1: Truth Table A12 A9 A8 A4 A3 A6 A5 A7 A D D R E S S B U F F E R R O W D E C O D E R CS CE WE OE A10 A0 A1 A2 A11 Figure 2: Block Diagram 1/15 MA9264 SIGNAL DEFINITIONS A0-12 Address input pins which select a particular eight bit word within the memory array. D0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write operation. CS Chip Select, which, at low level, activates a read or write operation. When at a high level it defaults the SRAM to a prechargencondition and holds the data output drivers in a high impedance state. WE Write Enable which when at a low level enables a write and holds data output drivers in a high impedance state. When at a high level, it enables a read. 2/15 OE Output Enable which when at a high level holds the data output drivers in a high impedance state. When at a low level, data output driver state is defined by CS, WE and CE. If this signal is not used it must be connected to VSS. CE Chip Enable which when at a high level allows normal operation. When at a low level it defaults the SRAM to a precharge condition, disables the input circuits on all input pins and holds the data output drivers in a high impedance state. If this signal is not used it must be connected to VDD. MA9264 CHARACTERISTICS AND RATINGS Symbol Parameter Min. Max. Units Supply Voltage -0.5 7.0 V VI Input Voltage -0.3 VDD+0.3 V TA Operating Temperature -55 125 °C TS Storage Temperature -65 150 °C VCC Stresses above those listed may cause permanent damage to the device. This is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not Implied Exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability. Figure 3: Absolute Maximum Ratings Notes for Tables 4 and 5: Characteristics apply to pre radiation at TA = -55°C to +125°C with VDD = 5V ±10% and to post 100k Rad(Si) total dose radiation at TA = 25°C with VDD = 5V ±10% (characteristics at higher radiation levels available on request). GROUP A SUBGROUPS 1, 2, 3. Symbol Parameter Conditions VDD Supply voltage - VlH Logical ‘1’ Input Voltage - VlL Logical ‘0’ Input Voltage - VOH1 Logical ‘1’ Output Voltage VOH2 VOL (Option) Min. Typ. Max. Units 4.5 5.0 5.5 V (TTL) (CMOS) VDD/2 0.8 VDD - VDD VDD V V (TTL) (CMOS) VSS VSS - 0.8 0.2 VDD V V IOH1 = -2mA 2.4 - - V Logical ‘1’ Output Voltage IOH2 = -1mA VDD -0.5 - - V Logical ‘0’ Output Voltage IOL = 4mA - - 0.4 V ILI Input Leakage Current VIN = VDD or VSS All inputs - - ±10 µA ILO Output Leakage Current Chip disabled, VOUT = VDD or VSS - - ±10 µA ISB1 Selected Static Current (CMOS) All inputs = VDD -0.2V except CS = VSS +0.2V - 0.1 10 mA IDD Dynamic Operating Current (CMOS) fRC = 1MHz, all inputs switching, VIH = VDD -0.2V - 6 18 mA ISB2 Standby Supply Current CS = VDD -0.2V CE = VSS +0.2V - 0.1 10 mA Figure 4: Electrical Characteristics Symbol Parameter Conditions VDR VCC for Data Retention CS = VDR, CE = VSS IDDR Data Retention Current CS = VDR, VDR = 2.0V CE = VSS (Option) Min. Typ. Max. Units 2.0 - - V - 0.05 4 mA Figure 5: Data Retention Characteristics 3/15 MA9264 AC CHARACTERISTICS Conditions of Test for Tables 5 and 6: 1. Input pulse = VSS to 3.0V (TTL) and VSS to 4.0V (CMOS). 2. Times measurement reference level = 1.5V. 3. Input Rise and Fall times ≤5ns. 4. Output load 1TTL gate and CL = 60pF. 5. Transition is measured at ±500mV from steady state. 6. This parameter is sampled and not 100% tested. Notes for Tables 6 and 7: Characteristics apply to pre-radiation at TA = -55°C to +125°C with VDD = 5V±10% and to post 100k Rad(Si) total dose radiation at TA = 25°C with VDD = 5V ±10%. GROUP A SUBGROUPS 9, 10, 11. Symbol Parameter TAVAVR Read Cycle Time TAVQV MAX9264X70 Min Max MAX9264X95 Min Max Units 70 - 95 - ns Address Access Time - 65 - 90 ns TEHQV Chip Select Access Time - 70 - 95 ns TSLQV Chip Enable Access Time - 70 - 95 ns TEHQX (5,6) Chip Selection to Output in Low Z 15 - 15 - ns TSLQX (5,6) Chip Enable to Output in Low Z 15 - 15 - ns TELQZ (5,6) Chip Deselection to Output in High Z 0 20 0 20 ns TSHQZ (5,6) Chip Disable to Output in High Z 0 20 0 20 ns TAXQX Output Hold from Address Change 30 - 40 - ns TGLQV Output Enable Access Time - 25 - 30 ns TGLQX (5,6) Output Enable to Output in Low Z 15 - 15 - ns TGHQZ (5,6) Output Enable to Output in High Z 0 20 0 20 ns Figure 6: Read Cycle AC Electrical Characteristics Symbol Parameter MAX9264X70 Min Max Units TAVAVW Write Cycle Tlme 55 - 60 - ns TEHWH Chip Selection to End of Write 50 - 60 - ns TSLWH Chip Enable to End of Write 50 - 60 - ns TAVWH Address Valid to End of Write 50 - 55 - ns TAVWL Address Set Up Time 0 - 0 - ns TWLWH Write Pulse Width 40 - 45 - ns TWHAV Write Recovery Time 0 - 0 - ns Wnte to Output in High Z 0 20 0 20 ns TDVWH Data to Write Time Overlap 25 - 30 - ns TWHDX Data Hold from Write 0 - 0 - ns Output Active from End to Write 0 20 0 20 ns TWLQZ (5,6) TWHQX (5,6) Figure 7: Write Cycle AC Electrical Characteristics 4/15 MAX9264X95 Min Max MA9264 Symbol CIN COUT Parameter Conditions Min. Typ. Max. Units Input Capacitance Vl = 0V - 3 5 pF Output Capacitance VI/O = 0V - 5 7 pF Note: TA = 25°C and f = 1MHz. Data obtained by characterisation or analysis; not routinely measured. Figure 8: Capacitance Symbol FT Parameter Conditions Basic Functionality VDD = 4.5V - 5.5V, FREQ = 1MHz VIL = VSS, VIH = VDD, VOL ≤ 1.5V, VOH ≥ 1.5V TEMP = -55°C to +125°C, GPS PATTERN SET GROUP A SUBGROUPS 7, 8A, 8B Figure 9: Functionality Subgroup Definition 1 Static characteristics specified in Tables 4 and 5 at +25°C 2 Static characteristics specified in Tables 4 and 5 at +125°C 3 Static characteristics specified in Tables 4 and 5 at -55°C 7 Functional characteristics specified in Table 9 at +25°C 8A Functional characteristics specified in Table 9 at +125°C 8B Functional characteristics specified in Table 9 at -55°C 9 Switching characteristics specified in Tables 6 and 7 at +25°C 10 Switching characteristics specified in Tables 6 and 7 at +125°C 11 Switching characteristics specified in Tables 6 and 7 at -55°C Figure 10: Definition of Subgroups 5/15 MA9264 TIMING DIAGRAMS TAVAVR ADDRESS TAVQV TAXQX TSLQV CS TSLQX DATA OUT HIGH IMPEDANCE TSHQZ DATA VALID TEHQX TEHQV TELQZ CE TGLQX TGHQZ TGLQV OE 1. WE is high for Read Cycle. 2. Address Vaild prior to or coincident with CS transition low or CE transition high. Figure 11a: Read Cycle 1 TAVAVR ADDRESS TAVQV DATA OUT DATA VALID 1. WE is high for Read Cycle. 2. Device is continually selected. CS, OE low, CE high. Figure 11b: Read Cycle 2 6/15 TAXQX MA9264 TAVAVW ADDRESS TAVWH TWHAV (3) TWLWH (2) TAVWL (4) WE TAXQX TWLQZ TWLQX (5) DATA OUT (8) (6) (7) HIGH IMPEDANCE TDVWH DATA IN TWHDX DATA VALID TSLWH CS TEHWH CE 1. WE must be high during all address transitions. 2. A write occurs during the overlap (TWLWH) of a low CS, a high CE and a low WE. 3. TWHAV is measured from either CS or WE going high or CE going low, whichever is the earlier, to the end of the write cycle. 4. If the CS low or CE high transition occurs simultaneously with, or after, the WE low transition, the output remains in the high impedance state. 5. DATA OUT is in the active state, so DATA IN must not be in the opposing state. 6. DATA OUT is the write data of the current cycle, if selected. 7. DATA OUT is the read data of the next address,if selected. 8. OE is low. (If OE is high then DATA OUT remains in the high impedance state throughout the cycle). Figure 12: Write Cycle 7/15 MA9264 TYPICAL PERFORMANCE CHARACTERISTICS MAx9264x70 55 53 51 49 47 45 8/15 MA9264 72 68 64 60 56 52 48 44 40 64 62 60 58 56 54 52 50 9/15 MA9264 25 16 14 20 12 10 15 8 6 10 4 2 5 58 57 56 55 54 53 52 51 50 49 48 10/15 MA9264 OUTLINES AND PIN ASSIGNMENTS D 14 1 15 28 W ME Seating Plane A1 A C H e1 e Ref b Z Millimetres 15° Inches Min. Nom. Max. Min. Nom. Max. A - - 5.715 - - 0.225 A1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 D - - 36.02 - - 1.418 e - 2.54 Typ. - - 0.100 Typ. - e1 H Me Z W XG404 4.71 - 15.24 Typ. - 5.38 15.90 1.27 1.53 0.185 - 0.600 Typ. - - NC 1 28 VCC A12 2 27 W A7 3 26 CE A6 4 25 A8 A5 5 24 A9 A4 6 A3 7 A2 8 A1 9 23 A11 Top View 22 OE 21 A10 20 CS A0 10 19 D/Q7 0.626 D/Q0 11 18 D/Q6 0.050 D/Q1 12 17 D/Q5 0.060 D/Q2 13 16 D/Q4 GND 14 15 D/Q3 0.212 Figure 13: 28-Lead Ceramic DIL (Solder Seal) - Package Style C 11/15 MA9264 M b D Z e L A c ME Q VCC 28 Pin 1 1 NC W 27 2 A12 CE 26 3 A7 A8 25 4 A6 A9 24 5 A5 A11 23 OE 22 A10 21 Ref Millimetres 6 A4 Bottom View 8 A2 CS 20 9 A1 D/Q7 19 10 A0 D/Q6 18 11 D/Q0 D/Q5 17 12 D/Q1 D/Q4 16 13 D/Q2 D/Q3 15 14 GND Inches Min. Nom. Max. Min. Nom. Max. A - - 3.18 - - 0.125 Q 0.66 - - 0.026 - - b 0.38 - 0.48 0.015 - 0.019 c 0.10 - 0.18 0.004 - 0.007 D 18.08 - 18.49 0.712 - 0.728 e - 1.27 - - 0.050 - L 7.62 - 9.91 0.300 - 0.390 M 12.50 - 12.09 0.492 - 0.508 XG530 Figure 14: 28-Lead Ceramic Flatpack (Solder Seal) - Package Style F 12/15 7 A3 MA9264 Function Pin N umbe r Option D a nd F A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 D/Q0 11 D/Q1 12 D/Q2 13 GND(VSS) 14 D/Q3 15 D/Q4 16 D/Q5 17 D/Q6 18 D/Q7 19 CSB 20 A10 21 OEB 22 A11 23 A9 24 A8 25 CE 26 WB 27 VDD 28 Via R R R R R R R R R R R R Direct R R R R R R R R R R R R R Direct S ta tic 1 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V S ta tic 2 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 0V 5V D yna mic Ra dia tion F14 F7 F9 F8 F11 F10 F5 F4 F3 F1 F1 F1 0V F1 F1 F1 F1 F1 F15 F2 F15 F6 F13 F12 F15B F0 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 0V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 5V 1. F0=150KHz, F1=F0/2, F2=F0/4, F3=F0/8 etc. 2. Static 1, Static 2 and Dynamic: R=4k7. 3. Radiation: R=10k. Figure 15: Burnin and Radiation Configuration 13/15 MA9264 RADIATION TOLERANCE Total Dose Radiation Testing For product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. The sample devices will be subjected to the total dose radiation level (Cobalt-60 Source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. Electrical tests, pre and post irradiation, will be read and recorded. Dynex Semiconductor can provide radiation testing compliant with MIL-STD-883 test method 1019, Ionizing Radiation (Total Dose). Total Dose (Function to specification)* 1x105 Rad(Si) Transient Upset (Stored data loss) 5x1010 Rad(Si)/sec Transient Upset (Survivability) >1x1012 Rad(Si)/sec Neutron Hardness (Function to specification) >1x1015 n/cm2 Single Event Upset** 4.3x10-11 Errors/bit day Latch Up Not possible * Other total dose radiation levels available on request ** Worst case galactic cosmic ray upset - interplanetary/high altitude orbit Figure 16: Radiation Hardness Parameters SINGLE EVENT UPSET CHARACTERISTICS UPSET BIT CROSS-SECTION (cm2/bit) Ion LET (MeV.cm2/mg) Figure 17: Typical Per-Bit Upset Cross-Section vs Ion LET 14/15 MA9264 ORDERING INFORMATION 70 95 Unique Circuit Designator MAx9264xxxxxxxx Radiation Tolerance S R Q QA/QCI Process (See Section 9 Part 4) Radiation Hard Processing 100 kRads (Si) Guaranteed 300 kRads (Si) Guaranteed For radiation levels above those stated please contact Marketing T C Test Process (See Section 9 Part 3) TTL CMOS Assembly Process (See Section 9 Part 2) Package Type C F L N 70ns Speed 95ns Speed Reliability Level Ceramic DIL (Solder Seal) Flatpack (Solder Seal) Leadless Chip Carrier Naked Die L C D E B S For details of reliability, QA/QC, test and assembly options, see ‘Manufacturing Capability and Quality Assurance Standards’ Section 9. Rel 0 Rel 1 Rel 2 Rel 3/4/5/STACK Class B Class S http://www.dynexsemi.com e-mail: [email protected] HEADQUARTERS OPERATIONS DYNEX SEMICONDUCTOR LTD Doddington Road, Lincoln. Lincolnshire. LN6 3LF. United Kingdom. Tel: 00-44-(0)1522-500500 Fax: 00-44-(0)1522-500550 DYNEX POWER INC. Unit 7 - 58 Antares Drive, Nepean, Ontario, Canada K2E 7W6. Tel: 613.723.7035 Fax: 613.723.1518 Toll Free: 1.888.33.DYNEX (39639) CUSTOMER SERVICE CENTRES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 North America Tel: 011-800-5554-5554. Fax: 011-800-5444-5444 UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 SALES OFFICES France, Benelux, Italy and Spain Tel: +33 (0)1 69 18 90 00. Fax: +33 (0)1 64 46 54 50 Germany Tel: 07351 827723 North America Tel: (613) 723-7035. Fax: (613) 723-1518. Toll Free: 1.888.33.DYNEX (39639) / Tel: (831) 440-1988. Fax: (831) 440-1989 / Tel: (949) 733-3005. Fax: (949) 733-2986. UK, Germany, Scandinavia & Rest Of World Tel: +44 (0)1522 500500. Fax: +44 (0)1522 500020 These offices are supported by Representatives and Distributors in many countries world-wide. © Dynex Semiconductor 2000 Publication No. DS3692-7 Issue No. 7.0 January 2000 TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM Datasheet Annotations: Dynex Semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. The annotations are as follows:Target Information: This is the most tentative form of information and represents a very preliminary specification. No actual design work on the product has been started. Preliminary Information: The product is in design and development. The datasheet represents the product as it is understood but details may change. Advance Information: The product design is complete and final characterisation for volume production is well in hand. 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