Hermetically Sealed, High Speed, High CMR, Logic Gate Optocouplers Technical Data 6N134* 81028 HCPL-563X HCPL-663X HCPL-565X 5962-98001 HCPL-268K HCPL-665X 5962-90855 HCPL-560X *See matrix for available extensions. Features • Dual Marked with Device Part Number and DSCC Drawing Number • Manufactured and Tested on a MIL-PRF-38534 Certified Line • QML-38534, Class H and K • Five Hermetically Sealed Package Configurations • Performance Guaranteed over -55°C to +125°C • High Speed: 10 M Bit/s • CMR: > 10,000 V/µs Typical • 1500 Vdc Withstand Test Voltage • 2500 Vdc Withstand Test Voltage for HCPL-565X • High Radiation Immunity • 6N137, HCPL-2601, HCPL2630/-31 Function Compatibility • Reliability Data • TTL Circuit Compatibility Applications • Military and Space • High Reliability Systems • Transportation, Medical, and Life Critical Systems • • • • • • Line Receiver Voltage Level Shifting Isolated Input Line Receiver Isolated Output Line Driver Logic Ground Isolation Harsh Industrial Environments • Isolation for Computer, Communication, and Test Equipment Systems Description These units are single, dual and quad channel, hermetically sealed optocouplers. The products are capable of operation and storage over the full military temperature range and can be purchased as either standard product or with full MIL-PRF-38534 Class Level H or K testing or from the appropriate DSCC Drawing. All devices are manufactured and tested on a MIL-PRF-38534 certified line and are included in the DSCC Qualified Manufacturers List QML38534 for Hybrid Microcircuits. Quad channel devices are available by special order in the 16 pin DIP through hole packages. Truth Table (Positive Logic) Multichannel Devices Input On (H) Off (L) Output L H Single Channel DIP Input On (H) Off (L) On (H) Off (L) Enable H H L L Output L H H H Functional Diagram Multiple Channel Devices Available VCC VE VOUT GND The connection of a 0.1 µF bypass capacitor between VCC and GND is recommended. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. 2 Each channel contains a GaAsP light emitting diode which is optically coupled to an integrated high speed photon detector. The output of the detector is an open collector Schottky clamped transistor. Internal shields provide a guaranteed common mode transient immunity specification of 1000 V/µs. For Isolation Voltage applications requiring up to 2500 Vdc, the HCPL-5650 family is also available. Package styles for these parts are 8 and 16 pin DIP through hole (case outlines P and E respectively), and 16 pin surface mount DIP flat pack (case outline F), leadless ceramic chip carrier (case outline 2). Devices may be purchased with a variety of lead bend and plating options. See Selection Guide Table for details. Standard Microcircuit Drawing (SMD) parts are available for each package and lead style. Because the same electrical die (emitters and detectors) are used for each channel of each device listed in this data sheet, absolute maximum ratings, recommended operating conditions, electrical specifications, and performance characteristics shown in the figures are identical for all parts. Occasional exceptions exist due to package variations and limitations, and are as noted. Additionally, the same package assembly processes and materials are used in all devices. These similarities give justification for the use of data obtained from one part to represent other parts’ performance for reliability and certain limited radiation test results. Selection Guide–Package Styles and Lead Configuration Options Package Lead Style Channels 16 Pin DIP 8 Pin DIP 8 Pin DIP 8 Pin DIP 16 Pin Flat Pack 20 Pad LCCC Through Hole Through Hole Through Hole Through Hole Unformed Leads Surface Mount 2 1 2 2 4 2 Common Channel Wiring VCC, GND None VCC, GND VCC, GND VCC, GND None Withstand Test Voltage 1500 Vdc 1500 Vdc 1500 Vdc 2500 Vdc 1500 Vdc 1500 Vdc 6N134* Agilent Part # & Options Commercial HCPL-5600 HCPL-5630 HCPL-5650 HCPL-6650 HCPL-6630 MIL-PRF-38534, Class H 6N134/883B HCPL-5601 HCPL-5631 HCPL-5651 HCPL-6651 HCPL-6631 MIL-PRF-38534, Class K HCPL-560K HCPL-563K HCPL-665K HCPL-663K Gold Plate Solder Pads Standard Lead Finish Solder Dipped HCPL-268K Gold Plate Gold Plate Gold Plate Gold Plate Option #200 Option #200 Option #200 Option #200 Butt Cut/Gold Plate Option #100 Option #100 Option #100 Gull Wing/Soldered Option #300 Option #300 Option #300 Prescript for all below None 5962- None None None None Either Gold or Solder 8102801EX 9085501HPX 8102802PX 8102805PX 8102804FX 81028032X Gold Plate 8102801EC 9085501HPC 8102802PC 8102805PC 8102804FC Solder Dipped 8102801EA 9085501HPA 8102802PA 8102805PA Butt Cut/Gold Plate 8102801UC 9085501HYC 8102802YC Butt Cut/Soldered 8102801UA 9085501HYA 8102802YA Gull Wing/Soldered 8102801TA 9085501HXA 8102802ZA 5962- 5962- 5962- Class H SMD Part # 81028032A Class K SMD Part # Prescript for all below 5962- 5962- Either Gold or Solder 9800101KEX 9085501KPX 9800102KPX 9800104KFX 9800103K2X Gold Plate 9800101KEC 9085501KPC 9800102KPC 9800104KFC Solder Dipped 9800101KEA 9085501KPA 9800102KPA Butt Cut/Gold Plate 9800101KUC 9085501KYC 9800102KYC Butt Cut/Soldered 9800101KUA 9085501KYA 9800102KYA Gull Wing/Soldered 9800101KTA 9085501KXA 9800102KZA *JEDEC registered part. 9800103K2A 3 Functional Diagrams 16 Pin DIP Through Hole 2 Channels 2 VCC 15 3 VO1 14 VO2 1 VE 2 GND 8 7 VOUT 3 12 6 1 VCC VO1 2 VO2 3 4 11 6 8 16 Pin Flat Pack Unformed Leads 4 Channels 4 GND 10 GND 5 8 7 2 VCC 15 3 VO1 14 4 VO2 13 5 VO3 12 6 5 6 VO4 11 7 GND 10 15 VCC2 19 VO2 20 2 GND2 VO1 VCC1 13 12 10 3 GND1 7 8 9 8 9 20 Pad LCCC Surface Mount 2 Channels 16 1 VCC 13 4 7 8 Pin DIP Through Hole 2 Channels 16 1 5 8 Pin DIP Through Hole 1 Channel Note: All DIP and flat pack devices have common VCC and ground. Single channel DIP has an enable pin 7. LCCC (leadless ceramic chip carrier) package has isolated channels with separate VCC and ground connections. All diagrams are “top view.” Outline Drawings 16 Pin DIP Through Hole, 2 Channels 20.06 (0.790) 20.83 (0.820) 8.13 (0.320) MAX. 0.89 (0.035) 1.65 (0.065) 4.45 (0.175) MAX. 0.51 (0.020) MIN. 3.81 (0.150) MIN. 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). Leaded Device Marking Agilent DESIGNATOR Agilent P/N DSCC SMD* DSCC SMD* PIN ONE/ ESD IDENT A QYYWWZ XXXXXX XXXXXXX XXX XXX • 50434 * QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) COUNTRY OF MFR. Agilent CAGE CODE* Leadless Device Marking Agilent DESIGNATOR Agilent P/N PIN ONE/ ESD IDENT COUNTRY OF MFR. A QYYWWZ XXXXXX • XXXX XXXXXX XXX 50434 * QUALIFIED PARTS ONLY COMPLIANCE INDICATOR,* DATE CODE, SUFFIX (IF NEEDED) DSCC SMD* DSCC SMD* Agilent CAGE CODE* 4 Outline Drawings (continued) 8 Pin DIP Through Hole, 1 and 2 Channels 8 Pin DIP Through Hole, 2 Channels 2500 Vdc Withstand Test Voltage 9.40 (0.370) 9.91 (0.390) 8.13 (0.320) MAX. 9.40 (0.370) 9.91 (0.390) 8.13 (0.320) MAX. 0.76 (0.030) 1.27 (0.050) 7.16 (0.282) 7.57 (0.298) 0.76 (0.030) 1.27 (0.050) 7.16 (0.282) 7.57 (0.298) 4.32 (0.170) MAX. 3.81 (0.150) MIN. 0.51 (0.020) MIN. 0.51 (0.020) MAX. 5.08 (0.200) MAX. 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MIN. 3.81 (0.150) MIN. 7.36 (0.290) 7.87 (0.310) 2.29 (0.090) 2.79 (0.110) 2.29 (0.090) 2.79 (0.110) 0.51 (0.020) MAX. 0.20 (0.008) 0.33 (0.013) 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 16 Pin Flat Pack, 4 Channels 20 Terminal LCCC Surface Mount, 2 Channels 7.24 (0.285) 6.99 (0.275) 8.70 (0.342) 9.10 (0.358) 2.29 (0.090) MAX. 4.95 (0.195) 5.21 (0.205) 1.78 (0.070) 2.03 (0.080) 1.02 (0.040) (3 PLCS) 1.14 (0.045) 1.40 (0.055) 8.70 (0.342) 9.10 (0.358) 4.95 (0.195) 5.21 (0.205) 11.13 (0.438) 10.72 (0.422) 1.27 (0.050) REF. 0.46 (0.018) 0.36 (0.014) 8.13 (0.320) MAX. 2.85 (0.112) MAX. 0.31 (0.012) 0.23 (0.009) 0.89 (0.035) 0.69 (0.027) 5.23 (0.206) MAX. 0.88 (0.0345) MIN. 9.02 (0.355) 8.76 (0.345) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). TERMINAL 1 IDENTIFIER 2.16 (0.085) METALLIZED CASTILLATIONS (20 PLCS) 1.78 (0.070) 2.03 (0.080) 0.64 (0.025) (20 PLCS) 0.51 (0.020) 1.52 (0.060) 2.03 (0.080) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). SOLDER THICKNESS 0.127 (0.005) MAX. 5 Hermetic Optocoupler Options Option 100 Description Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). 4.32 (0.170) MAX. 0.51 (0.020) MIN. 1.14 (0.045) 1.40 (0.055) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.32 (0.170) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.14 (0.045) 1.40 (0.055) 0.20 (0.008) 0.33 (0.013) 0.51 (0.020) MAX. 7.36 (0.290) 7.87 (0.310) NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 200 300 Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 and 16 pin DIP. DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder dipped terminals as a standard feature. Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial and hi-rel product in 8 and 16 pin DIP (see drawings below for details). This option has solder dipped leads. 4.57 (0.180) MAX. 0.51 (0.020) MIN. 1.40 (0.055) 1.65 (0.065) 0.51 (0.020) MAX. 2.29 (0.090) 2.79 (0.110) 4.57 (0.180) MAX. 0.51 (0.020) MIN. 2.29 (0.090) 2.79 (0.110) 1.40 (0.055) 1.65 (0.065) 5° MAX. 0.51 (0.020) MAX. NOTE: DIMENSIONS IN MILLIMETERS (INCHES). 4.57 (0.180) MAX. 0.20 (0.008) 0.33 (0.013) 9.65 (0.380) 9.91 (0.390) 6 Absolute Maximum Ratings (No derating required up to +125°C) Storage Temperature Range, TS ................................... -65°C to +150°C Operating Temperature, TA .......................................... -55°C to +125°C Case Temperature, TC ................................................................ +170°C Junction Temperature, TJ ........................................................... +175°C Lead Solder Temperature ............................................... 260°C for 10 s Peak Forward Input Current, IF PK, (each channel, ≤ 1 ms duration) ...................................................................... 40 mA Average Input Forward Current, IF AVG (each channel) ................ 20 mA Input Power Dissipation (each channel) ..................................... 35 mW Reverse Input Voltage, VR (each channel) ......................................... 5 V Supply Voltage, VCC (1 minute maximum) ........................................ 7 V Output Current, IO (each channel) ............................................... 25 mA Output Power Dissipation (each channel) .................................. 40 mW Output Voltage, VO (each channel) .................................................. 7 V* Package Power Dissipation, PD (each channel) ........................ 200 mW *Selection for higher output voltages up to 20 V is available. Single Channel Product Only Emitter Input Voltage, VE ............................................................... 5.5 V 8 Pin Ceramic DIP Single Channel Schematic Note enable pin 7. An external 0.01 µF to 0.1 µF bypass capacitor must be connected between VCC and ground for each package type. ESD Classification (MIL-STD-883, Method 3015) HCPL-5600/01/0K ............................................................... (∆), Class 1 6N134, 6N134/883B, HCPL-5630/31/3K, HCPL-5650/51, HCPL-6630/31/3K and HCPL-6650/51/5K ....................... (Dot), Class 3 Recommended Operating Conditions Parameter Input Current, Low Level, Each Channel Input Current, High Level, Each Channel* Supply Voltage, Output Fan Out (TTL Load) Each Channel *Meets or exceeds DSCC SMD and JEDEC requirements. Symbol IFL IFH VCC N Min. 0 10 4.5 Max. 250 20 5.5 6 Units µA mA V 7 Recommended Operating Conditions (cont’d.) Single Channel Product Only[10] Parameter High Level Enable Voltage Low Level Enable Voltage Symbol VEH VEL Min. 2.0 0 Max. VCC 0.8 Units V V Electrical Characteristics (TA = -55°C to +125°C, unless otherwise specified) Parameter High Level Output Current Low Level Output Voltage Current Transfer Ratio Logic Single High Channel Supply Dual Current Channel Quad Channel Logic Single Low Channel Supply Dual Current Channel Quad Channel Input Forward Voltage Input Reverse Breakdown Voltage Input-Output Leakage Current Capacitance Between Input/ Output Limits Group A[13] Symbol Test Conditions Subgroups Min. Typ.** Max. Units Fig. Note IOH* VCC = 5.5 V, VO = 5.5 V, 1, 2, 3 20 250 µA 1 1 IF = 250 µA VOL* VCC = 5.5 V, IF = 10 mA, 1, 2, 3 0.3 0.6 V 2 1, 9 IOL (Sinking) = 10 mA hF CTR VO = 0.6 V, IF = 10 mA, 1, 2, 3 100 % 1 VCC = 5.5 V ICCH* VCC = 5.5 V, IF = 0 mA 1, 2, 3 9 14 mA 1 ICCL* VF* VCC = 5.5 V, IF1 = IF2 = 0 mA VCC = 5.5 V, IF1 = IF2 = IF3 = IF4 = 0 mA VCC = 5.5 V, IF = 20 mA VCC = 5.5 V, IF1 = IF2 = 20 mA VCC = 5.5 V, IF1 = IF2 = IF3 = IF4 = 20 mA IF = 20 mA BVR* IR = 10 µA II-O* RH = 45% VI-O = 1500 Vdc TA = 25°C VI-O = 2500 t=5s Vdc f = 1 MHz, TC = 25°C CI-O *Identified test parameters for JEDEC registered parts. **All typical values are at VCC = 5 V, TA = 25°C. 1, 2, 3 1, 2, 3 1, 2 3 1, 2, 3 18 28 mA 25 42 mA 13 18 mA 1 26 36 mA 6 33 50 mA 1.5 1.55 1.9 1.75 1.85 V V 5 6 3 3 1, 15 1, 16 V 1 1 1.0 µA 2, 8, 17 1 4 1.0 4.0 µA pF 18 1, 3, 14 1.0 8 Electrical Characteristics, (Contd.) TA = -55°C to +125°C unless otherwise specified Test Parameter Symbol Conditions Propagation Delay t * VCC = 5 V, PLH Time to High RL = 510 Ω, Output Level C L = 50 pF, IF = 13 mA Propagation Delay tPHL* Time to Low Output Level Output Rise Time Output Fall Time Common Mode Transient Immunity at High Output Level Common Mode Transient Immunity at Low Output Level tLH tHL RL = 510 Ω, CL = 50 pF, IF = 13 mA Limits Group A[13] Subgroups Min. Typ.** Max. Units Fig. Note 9 60 10, 11 Single Channel Product Only Low Level IEL VCC = 5.5 V, Enable Current VE = 0.5 V High Level VEH Enable Voltage Low Level VEL Enable Voltage ns 4, 5, 6 140 9 55 10, 11 100 1, 5 ns 120 9, 10, 11 |CMH| VCM = 50 V (PEAK), VCC = 5 V, VO (min.) = 2 V, RL = 510 Ω, IF = 0 mA |CML| VCM = 50 V (PEAK), VCC = 5 V, VO (max.) = 0.8 V, RL = 510 kΩ, IF = 10 mA 100 35 35 90 40 ns 1 9, 10, 11 1000 >10000 V/µs 7 1, 7, 14 9, 10, 11 1000 >10000 V/µs 7 1, 7, 14 1, 2, 3 1, 2, 3 -1.45 -2.0 2.0 1, 2, 3 mA V 0.8 10 V *Identified test parameters for JEDEC registered part. **All typical values are at VCC = 5 V, TA = 25°C. Typical Characteristics, TA = 25°C, VCC = 5 V Parameter Input Capacitance Input Diode Temperature Coefficient Resistance (Input-Output) Single Channel Product Only Propagation Delay Time of Enable from VEH to VEL Propagation Delay Time of Enable from VEL to VEH Sym. CIN ∆VF ∆TA RI-O Typ. 60 -1.5 Units pF mV/°C 1012 Ω VI-O = 500 V tELH 35 ns tEHL 35 ns RL = 510 Ω, CL = 50 pF IF = 13 mA, VEH = 3 V, VEL = 0 V 0.5 nA 1012 0.55 Ω pF Dual and Quad Channel Product Only Input-Input II-I Leakage Current Resistance (Input-Input) RI-I Capacitance (Input-Input) C I-I Test Conditions VF = 0 V, f = 1 MHz IF = 20 mA Relative Humidity = 45% VI-I = 500 V, t = 5 s VI-I = 500 V f = 1 MHz Fig. Note 1 1 2 8, 9 1, 11 1, 12 4 4 4 9 Notes: 1. Each channel. 2. All devices are considered two-terminal devices; I I-O is measured between all input leads or terminals shorted together and all output leads or terminals shorted together. 3. Measured between each input pair shorted together and all output connections for that channel shorted together. 4. Measured between adjacent input pairs shorted together for each multichannel device. 5. tPHL propagation delay is measured from the 50% point on the leading edge of the input pulse to the 1.5 V point on the leading edge of the output pulse. The tPLH propagation delay is measured from the 50% point on the trailing edge of the input pulse to the 1.5 V point on the trailing edge of the output pulse. 6. The HCPL-6630, HCPL-6631, and HCPL-663K dual channel parts function as two independent single channel units. Use the single channel parameter limits for each channel. 7. CM L is the maximum rate of rise of the common mode voltage that can be sustained with the output voltage in the logic low state (VO < 0.8 V). CMH is the maximum rate of fall of the common mode voltage that can be sustained with the output voltage in the logic high state (VO > 2.0 V). 8. This is a momentary withstand test, not an operating condition. 9. It is essential that a bypass capacitor (0.01 to 0.1 µF, ceramic) be connected from VCC to ground. Total lead length between both ends of this external capacitor and the isolator connections should not exceed 20 mm. 10. No external pull up is required for a high logic state on the enable input. 11. The tELH enable propagation delay is measured from the 1.5 V point on the trailing edge of the enable input pulse to the 1.5 V point on the trailing edge of the output pulse. 12. The tEHL enable propagation delay is measured from the 1.5 V point on the leading edge of the enable input pulse to the 1.5 V point on the leading edge of the output pulse. 13. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and 883B parts receive 100% testing at 25, 125, and -55°C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively). 14. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to limits specified for all lots not specifically tested. 15. Not required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types. 16. Required for 6N134, 6N134/883B, 8102801, HCPL-268K and 5962-9800101 types. 17. Not required for HCPL-5650, HCPL-5651 and 8102805 types. 18. Required for HCPL-5650, HCPL-5651 and 8102805 types only. Figure 1. High Level Output Current vs. Temperature. Figure 2. Input-Output Characteristics. Figure 3. Input Diode Forward Characteristic. 10 D.U.T. PULSE GENERATOR ZO = 50 Ω tH = 5 ns INPUT MONITORING NODE 5V VCC RL IF VO 0.01 µF BYPASS VO CL* GND Rm * CLINCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 5. Propagation Delay, tPHL and tPLH vs. Pulse Input Current, IFH. Figure 4. Test Circuit for tPHL and t PLH.* D.U.T. B II VCC +5 V 510 Ω A OUTPUT VO MONITORING 0.01 µF NODE BYPASS GND VFF VCM + – PULSE GEN. Figure 6. Propagation Delay vs. Temperature. Figure 7. Test Circuit for Common Mode Transient Immunity and Typical Waveforms. 11 PULSE GENERATOR ZO = 50 Ω tr = 5 ns OUTPUT VE MONITORING NODE +5 V D.U.T. VCC VE IF = 13 mA RL VOUT 0.01 µF BYPASS OUTPUT VO MONITORING CL* NODE GND * CL INCLUDES PROBE AND STRAY WIRING CAPACITANCE. Figure 9. Enable Propagation Delay vs. Temperature. Figure 8. Test Circuit for t EHL and tELH. VCC +5.5 V VOC +5.5 V D.U.T.* VCC (EACH INPUT) + VIN 0.01 µF – 200 Ω 5.3 V (EACH OUTPUT) GND 200 Ω (EACH OUTPUT) CONDITIONS: IF = 20 mA IO = 25 mA TA = +125 °C * ALL CHANNELS TESTED SIMULTANEOUSLY. Figure 10. Operating Circuit for Burn-In and Steady State Life Tests. MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program Agilent’s Hi-Rel Optocouplers are in compliance with MIL-PRF38534 Classes H and K. Class H and Class K devices are also in compliance with DSCC drawings 81028, 5962-90855 and 596298001. Testing consists of 100% screening and quality conformance inspection to MIL-PRF-38534. www.semiconductor.agilent.com Data subject to change. Copyright © 1999 Agilent Technologies Obsoletes 5968-4743E 5968-9407E (10/00)