HD74HC164 8-bit Parallel-out Shift Register REJ03D0580-0300 Rev.3.00 Jan 31, 2006 Description This 8-bit shift register has gated serial inputs and clear. Each register bit is a D-type master/slave flip-flop. Inputs A & B permit complete control over the incoming data. A low at either or both inputs inhibits entry of new data and resets the first flip-flop to the low level at the next clock pulse. A high level on the input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup and hold time requirements will be entered. Data is serially shifted in and out of the 8-bit register during the positive going transition of the clock pulse. Clear is independent of the clock and accomplished by a low level at the clear input. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 14.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC164P DILP-14 pin PRDP0014AB-B (DP-14AV) P — HD74HC164FPEL SOP-14 pin (JEITA) PRSP0014DF-B (FP-14DAV) FP EL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Clear L H H H H Clock X Outputs A X X L X H B X X X L H QA L QAo L L H QB L QBo QAn QAn QAn QAo to QHo = Outputs remain unchanged. QAn to QGn = Data shifted from the previous stage on a positive edge at the clock input. H: High level L: Low level X: Irrelevant Rev.3.00, Jan 31, 2006 page 1 of 6 ········· ········· ········· ········· ········· QH L QHo QGn QGn ········· QGn HD74HC164 Pin Arrangement A 1 B 2 B QH 13 QH QA 3 QA QG 12 QG QB 4 QB QF 11 QF QC 5 QC QE 10 QE QD 6 QD GND 7 Serial Inputs 14 VCC A Outputs Outputs CK CLR 9 Clear 8 Clock (Top view) Logic Diagram Clock A B D Q D Q D Q D Q D Q D Q D Q D Q CLR CLR CLR CLR CLR CLR CLR CLR Clear QA Timing Diagram Clock A B Clear QA QB QC QD QE QF QG QH Rev.3.00, Jan 31, 2006 page 2 of 6 QB QC QD QE QF QG QH HD74HC164 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC Vin, Vout IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Symbol VCC VIN, VOUT Ta Input rise / fall time*1 Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 tr, tf Unit V V °C ns 0 to 400 Note: Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Iin Quiescent supply current ICC Min 2.0 1.5 4.5 6.0 Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max — — 1.5 — 3.15 — — 3.15 — 4.2 — — 4.2 — 2.0 — — 0.5 — 0.5 4.5 — — 1.35 — 1.35 6.0 2.0 — 1.9 — 2.0 1.8 — — 1.9 1.8 — 4.5 4.4 4.5 — 4.4 — 6.0 5.9 6.0 — 5.9 — 4.5 4.18 — — 4.13 — 6.0 5.68 — — 5.63 — 2.0 — 0.0 0.1 — 0.1 4.5 — 0.0 0.1 — 0.1 6.0 — 0.0 0.1 — 0.1 4.5 — — 0.26 — 0.33 6.0 6.0 6.0 — — — — — — 0.26 ±0.1 4.0 — — — 0.33 ±1.0 40 Rev.3.00, Jan 31, 2006 page 3 of 6 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC164 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPHL tPLH tPHL Setup time tsu Hold time th Removal time Pulse width Output rise/fall time Input capacitance trem tw tTLH, tTHL Cin Ta = 25°C Ta = –40 to +85°C Unit Min Typ Max Min Max 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 — — — — — — — — — — — — 100 20 17 5 — — — — 14 — — 15 — — 17 — — 1 — — 5 25 29 160 32 27 160 32 27 175 35 30 — — — — — — — — — — — — — — — — 125 25 21 5 4 20 24 200 40 34 200 40 34 220 44 37 — — — — 4.5 6.0 5 5 0 — — — 5 5 — — 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — 5 5 5 80 16 14 80 16 14 — — — — — 0 — — 8 — — 5 — — 5 — 5 — — — — — — — — — 75 15 13 10 5 5 5 100 20 17 100 20 17 — — — — — — — — — — — — — 95 19 16 10 Rev.3.00, Jan 31, 2006 page 4 of 6 Test Conditions MHz ns Clock to Q ns ns Clear to Q ns A, B to Clock ns Clock to A, B ns Clear to Clock ns Clock ns Clear ns pF HD74HC164 Test Circuit Measurement point CL* Note: CL includes the probe and fig capacitance. Waveforms tf tr 90% Clear VCC 90% 50% 50% 10% 10% tW (Clear) trem tr tf 90% Clock 50% 10% tW (Clock) tr 90% 50% 10% VCC 50% 50% 0V th tsu 50% 50% 10% 10% tPHL tsu th VCC 90% 90% 50% Serial A, B 0V tW (Clock) tPLH 50% 0V tf tPHL VOH Output QA 50% 50% (Note 3) 50% VOL tTHL tTLH Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. The output are measured one at a time with one transition per measurement. 3. See function table for QB to QH outputs. Rev.3.00, Jan 31, 2006 page 5 of 6 HD74HC164 Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B MASS[Typ.] 0.97g Previous Code DP-14AV D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 L A θ bp e Dimension in Millimeters Min e1 A1 0.51 bp 0.40 JEITA Package Code P-SOP14-5.5x10.06-1.27 RENESAS Code PRSP0014DF-B *1 Previous Code FP-14DAV D 0.48 0.56 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.23g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 14 7.4 1.30 Z ( Ni/Pd/Au plating ) 20.32 5.06 b3 c Max 8 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 Nom Max D 10.06 10.5 E 5.50 A2 7 e A1 bp Dimension in Millimeters Min x M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 1.42 Z L L Rev.3.00, Jan 31, 2006 page 6 of 6 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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