HANBit HDD16M64D8W DDR SDRAM Module 128Mbyte (16Mx64bit), based on16Mx8,4Banks, 4K Ref., DIMM, Part No. HDD16M64D8W GENERAL DESCRIPTION The HANBiT HDD16M64D8W is 16M bit x 64 Double Data Rate SDRAM high density memory modules. The HANBiT HDD16M64D8W consists of eight CMOS 16M x 8 bit with 4banks Double Data Rate SDRAMs in 66pin TSOP-II(400mil) packages mounted on a 184pin glass-epoxy substrate. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD16M64D8W is Dual In-line Memory Modules and intended for mounting into 184pin edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. FEATURES • Part Identification HDD16M64D8W – 10A : 100MHz (CL=2) HDD16M64D8W – 13A : 133MHz (CL=2) HDD16M64D8W – 13B : 133MHz (CL=2.5) • Power supply : VDD: 2.5V ± 0.2V, VDDQ: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1250 mil, double sided component URL : www.hbe.co.kr REV 2.0 (November.2002) 1 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W PIN ASSIGNMENT P1 P2 PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol PIN Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 VREF DQ1 VSS DQ1 DQS0 DQ2 VDD DQ3 NC NC VSS DQ8 DQ9 DQS1 VDDQ CK1 /CK1 VSS DQ10 DQ11 CKE0 VDDQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 *CB0 *CB1 VDD *DQS8 A0 *CB2 VSS *CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ /WE DQ41 /CAS VSS DQS5 DQ42 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 DQ43 VDD */CS2 DQ48 DQ49 VSS /CK2 CK2 VDDQ DQS6 DQ50 DQ51 VSS VDDID DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL VSS DQ4 DQ5 VDDQ DM0 DQ6 DQ7 VSS NC NC 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 131 132 133 134 135 136 137 NC VDDQ DQ12 DQ13 DM1 VDD DQ14 DQ15 DM1 VDDQ *BA2 DQ20 *A12 VSS DQ21 A11 DM2 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DM3 A3 VSS DQ31 *CB4 *CB5 VDDQ CK0 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 /CK0 VSS *DM8 A10 *CB6 VDDQ *CB7 VSS DQ36 DQ37 VDD DM4 DQ38 DQ39 VSS DQ44 /RAS DQ45 VDDQ /CS0 */CS1 DM5 VSS DQ46 DQ47 */CS3 VDDQ DQ52 DQ53 *A13 VDD DM6 DQ54 DQ55 172 173 174 175 176 177 178 179 180 181 182 183 184 VDDQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD * These pins should be NC in the system which does not support SPD PIN PIN DESCRIPTION PIN PIN DESCRIPTION A0~A12 Address input VDD Power supply(2.5V) BA0~BA1 Bank Select Address VDDQ Power supply for DQs(2.5V) DQ0~DQ63 Data input/output VREF Power supply for reference CB0~CB7 Check bit(Data input/output) VDDSPD Serial EEPROM Power supply(3.3) DQS0~DQS7 Data Strobe input/output VSS Ground DM0~DM7 Data-in Mask SA0~SA2 Address in EEPROM CK0~CK2,/CK0~/CK2 Clock input SDA Serial data I/O CKE0 Clock enable input SCL Serial clock /CS0 Chip Select input /WE Write enable /RAS Row Address strobe VDDID VDD indentification flag URL : www.hbe.co.kr REV 2.0 (November.2002) 2 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W /CAS Column Address strobe NC No connection FUNCTIONAL BLOCK DIAGRAM URL : www.hbe.co.kr REV 2.0 (November.2002) 3 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNTE VIN, VOUT -0.5 ~ 3.6 V Voltage on VDD supply relative to Vss VDD -1.0 ~ 3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5 ~ 3.6 V Storage temperature TSTG -55 ~ +150 °C PD 8.0 W Short circuit current IOS 50 Notes: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. mA Voltage on any pin relative to Vss Power dissipation Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. POWER & DC OPERATING CONDITIONS (Recommended operating conditions (Voltage referenced to Vss = 0V, TA = 0 to 70°C) ) PARAMETER Supply Voltage I/O Supply Voltage SYMBOL MIN MAX UNIT VDD 2.3 2.7 V VDDQ 2.3 2.7 V NOTE I/O Reference Voltage VREF VDDQ/2-50mV VDDQ/2+50mV V 1 I/O Termination Voltage(system) VTT VREF – 0.04 VREF + 0.04 V 2 Input High Voltage VIH (DC) VREF + 0.15 VREF + 0.3 V 4 Input Low Voltage VIL (DC) -0.3 VREF - 0.15 V 4 Input Voltage Level, CK and /CK inputs VIN (DC) -0.3 VDDQ + 0.3 V Input Differential Voltage, CK and /CK inputs VID (DC) 0.3 VDDQ + 0.6 V 3 Input crossing point voltage, CK and CK inputs VIx (DC) 1.15 1.35 V 5 Input leakage current I LI -2 2 uA Output leakage current I OZ -5 5 uA Output High current (VOUT = 1.95V) I OH -16.8 mA Output Low current (VOUT = 0.35V) I OL 16.8 mA Output High Current(Half strengh driver) IOH -9 mA Output High Current(Half strengh driver) IOL 9 mA Notes 1. Includes ± 25mV margin for DC offset on VREF, and a combined total of ± 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of £ 3nH. 2. VTT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHZ. 5. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same. 6. These charactericteristics obey the SSTL-2 class II standards. URL : www.hbe.co.kr REV 2.0 (November.2002) 4 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W DDR SDRAM IDD SPEC TABLE SYMBOL B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) UNIT IDD0 840 760 760 mA IDD1 1040 960 960 mA IDD2P 28 24 24 mA IDD2F 200 176 176 mA IDD2Q 144 120 120 mA IDD3P 280 280 280 mA IDD3N 440 440 440 mA IDD4R 1280 1136 1136 mA IDD4W 1216 1040 1040 mA IDD5 1480 1480 1480 mA Normal 16 16 16 mA Low power 8 8 8 mA 2640 2400 2400 mA NOTE IDD6 IDD7A Optional * Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap. AC OPERATING CONDITIONS PARAMETER/ CONDITION STMBOL MIN Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.31 Input Low (Logic 0) Voltage, DQ, DQS and DM signals. VIL (AC) Input Differential Voltage, CK and CK inputs VID (AC) Input Crossing Point Voltage, CK and CK inputs VIX (AC) MAX UNIT NOTE 3 VREF - 0.31 V 3 0.7 VDDQ+0.6 V 1 0.5*VDDQ-0.2 0.5*VDDQ+0.2 V 2 Note 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of V IX is expected to equal 0.5* VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a VREF envelope that has been bandwidth limited 20MHz. AC OPERATING TEST CONDITIONS PARAMETER VALUE UNIT Input reference voltage for Clock 0.5 * VDDQ V Input signal maximum peak swing 1.5 V Input signal minimum slew rate 0.5 V/ns VREF+0.31/VREF-0.31 V Input timing measurement reference level VREF V Output timing measurement reference level VTT V See Load Circuit V Input Levels(VIH/VIL) Output load condition URL : www.hbe.co.kr REV 2.0 (November.2002) 5 NOTE HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W INPUT/OUTPUT CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V, TA = 25°C, f = 1MHz) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS, WE ) CIN1 49 57 pF Input Capacitance(CKE0) CIN2 42 50 pF Input Capacitance( CS0) CIN3 42 50 pF Input Capacitance( CLK0, CLK1,CLK2 ) CIN4 22 25 pF COUT1 6 8 pF CIN5 6 8 pF Data & DQS input/output Capacitance(DQ0~DQ63) Input Capacitance(DM0~DM8) AC TIMMING PARAMETERS & SPECIFICATIONS (THESEACCHARICTERISTICSWERETESTEDON THECOMPONENT) PARAMETER DDR200 DDR266A DDR266B -10A -13A -13B SYMBOL MIN MAX MIN MAX MIN UNIT NOTE MAX Row cycle time tRC 70 65 65 ns 1 Refresh row cycle time tRFC 80 75 75 ns 1,2 Row active time tRAS 48 ns 1,2 /RAS to /CAS delay tRCD 20 20 20 ns 3 Row precharge time tRP 20 20 20 ns 3 Row active to Row active delay tRRD 15 15 15 ns 3 Write recovery time tWR 2 2 2 tCK 3 Last data in to Read command tCDLR 1 1 1 tCK 2 Col. address to Col. address delay tCCD 1 1 1 tCK CL=2.0 Clock cycle time 10 120K 45 120K 45 120K 12 7.5 12 10 12 ns 12 7.5 12 7.5 12 ns tCK CL=2.5 URL : www.hbe.co.kr REV 2.0 (November.2002) 6 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W Clock high level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK Clock low level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tDQSCK -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Output data access time from CK/CK tAC -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns Data strobe edge to ouput data edge tDQSQ - +0.6 - +0.5 - +0.5 ns Read Preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK Read Postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK Data out high impedence time from CK-/CK tHZQ -0.8 +0.8 -0.75 +0.75 -0.75 +0.75 ns CK to valid DQS-in tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS-in setup time tWPRES 0 0 0 ns DQS-in hold time tWPREH 0.25 0.25 0.25 tCK DQS-in falling edge to CK rising-setup time tDSS 0.2 0.2 0.2 tCK DQS-in falling edge to CK rising hold time tDSH 0.2 0.2 0.2 tCK DQS-in high level width tDQSH 0.35 0.35 0.35 tCK DQS-in low level width tDQSL 0.35 0.35 0.35 tCK DQS-in cycle time tDSC 0.9 Address and Control Input setup time tIS 1.1 0.9 0.9 ns Address and Control Input hold time tIH 1.1 0.9 0.9 ns Mode register set cycle time tMRD 16 15 15 ns DQ & DM setup time to DQS tDS 0.6 0.5 0.5 ns DQ & DM hold time to DQS tDH 0.6 0.5 0.5 ns DQ & DM input pulse width tDIPW 2 1.75 1.75 ns Power down exit time tPDEX 10 10 10 ns Exit self refresh to write command tXSW 116 95 Exit self refresh to bank active command tXSA 80 75 75 ns Exit self refresh to read command tXSR 200 200 200 Cycle Refresh interval time tREF 15.6 15.6 15.6 us Output DQS valid window tQH 0.35 0.35 0.35 tCK DQS write postamble time tWPST 0.25 0.25 0.25 tCK DQS-out access time from CK/CK 1.1 0.9 1.1 0.9 1.1 ns Notes : URL : www.hbe.co.kr REV 2.0 (November.2002) Δ tIH (ps) 0 +50 +100 7 3 tCK 1. Maximum burst refresh cycle : 8 2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a previous write was in progress, DQS could be High at this time, depending on tDQSS. 3. The maximum limit for this parameter is not a device limit. The device will operate with a great value for this parameter, but system performance (bus turnaround) will degrade accordingly. 4. A write command can be applied with tRCD satisfied after this command. 5. For registered DIMMs, tCL and tCH are ≥ 45% of the period including both the half period jitter (tJIT(HP) ) of the PLL and the half jitter due to crosstalk (tJIT(crosstalk) ) on the DIMM. 6. Input Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate Δ tIS (V/ns) (ps) 0.5 0 0.4 +50 0.3 +100 2 HANBit Electronics Co.,Ltd. 1 4 HANBit HDD16M64D8W This derating table is used to increase tDS/tDH in the case where the input slew rate is below 0.5V/ns. Input setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 7. I/O Setup/Hold Slew Rate Derating Input Setup/Hold Slew Rate Δ tIS (V/ns) (ps) 0.5 0 0.4 +75 0.3 +150 Δ tIH (ps) 0 +75 +150 This derating table is used to increase tDS/tDH in the case where the I/O slew rate is below 0.5V/ns. I/O setup/hold slew rate based on the lesser of AC-AC slew rate and DC-DC slew rate. 8. I/O Setup/Hold Plateau Derating I/O Input Level Δ tDS (mV) (ps) +50 ± 280 Δ tDH (ps) +50 This derating table is used to increase tDS/tDH in the case where the input level is flat below VREF ± 310mV for a duration of up to 2ns. 9. I/O Delta Rise/Fall Rate(1/slew-rate) Derating Delta Rise/Fall Rate Δ tDS (ns/V) (ps) 0 0 ±0.25 +50 ±0.5 +100 Δ tDH (ps) 0 +50 +100 This derating table is used to increase tDS/tDH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 5V/ns and slew rate 2 =.4V/ns then the Delta Rise/Fall Rate =-0/5ns/V. Input S/H slew rate based on larger of AC-AC delta rise/fall rate and DC-DC delta rise/fall rate. 10. This parameter is fir system simulation purpose. It is guranteed by design. 11. For each of the terms, if not already an integer, round to the next highest integer. tCK is actual to the system clock cycle time. COMMAND TRUTH TABLE (V=VALID, X=DOν¢T CARE, H=LOGIC HIGH, L=LOGIC LOW) COMMAND CKE n-1 CKE n /CS /RAS /CAS /WE DM X L L L L X OP code 1,2 X L L L L X OP code 1,2 L L L H X X X X Register Extended MRS H Register Mode register set H Auto refresh Refresh Self refresh Entry Exit Bank active & Row Addr. Read & column address Write & column address Auto precharge Auto H H X L H H H H X X X L L H H H X L H L precharge disable Auto X V H X precharge X L H L H H L X H X L L H L X Entry H L H X X X active power down L V V V Exit L H X X X X Precharge power Entry H L URL : www.hbe.co.kr REV 2.0 (November.2002) H X X X L H H H 8 X 3 3 3 3 L Column H (A0 ~ A9) 4 4 Column 4 Address Address (A0 ~ A9) H L NOTE Row address V L X All banks A11 A9~A0 L X H Bank selection A10/ AP V H H enable Clock suspend or down mode L eable Burst Stop Precharge L precharge disable Auto H H BA 0,1 4,6 X V L X H 7 X X X X X HANBit Electronics Co.,Ltd. 5 HANBit HDD16M64D8W Exit DM No operation command L H H X X X L V V V H X X X L H H H H H X X X V X X X 8 9 9 Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM. PACKAGE DIMENSIONS Unit : mm 32.741 ± 0.20 Front – Side URL : www.hbe.co.kr REV 2.0 (November.2002) 9 HANBit Electronics Co.,Ltd. HANBit HDD16M64D8W 32.741 ± 0.20 Rear-Side ORDERING INFORMATION Part Number Density Org. Package Ref. Vcc MODE MAX.frq HDD16M64D8W-10A 128MByte 16M x 64 184PIN DIMM 4K 2.5V DDR 100MHz/CL2 HDD16M64D8W -13A 128MByte 16M x 64 184PIN DIMM 4K 2.5V DDR 133MHz/CL2 HDD16M64D8W -13B 128MByte 16M x 64 184PIN DIMM 4K 2.5V DDR 133MHz/CL2.5 URL : www.hbe.co.kr REV 2.0 (November.2002) 10 HANBit Electronics Co.,Ltd.