Agilent HDMP-0440 Quad Port Bypass Circuit for Fibre Channel Arbitrated Loops Data Sheet Description The HDMP-0440 is a Quad Port Bypass Circuit (PBC), which provides a low-cost, low-power physical-layer solution for Fibre Channel Arbitrated Loop (FC-AL) disk array configurations. By using a PBC such as the HDMP-0440, hard disks may be pulled out or swapped while other disks in the array are available to the system. A PBC consists of multiple 2:1 multiplexers daisy chained together. Each port has two modes of operation: “disk in loop” and “disk bypassed.” When the “disk in loop” mode is selected, the loop goes into and out of the disk drive at that port. For example, data goes from the HDMP-0440’s TO_NODE[n]± differential output pins to the Disk Drive Transceiver IC’s (e.g. an HDMP-1636A) Rx differential input pins. Data from the Disk Drive Transceiver IC’s Tx differential outputs goes to the HDMP-0440’s FM_NODE[n]± differential input pins. Figure 2 shows connection diagrams for disk drive array applications. When the “disk bypassed” mode is selected, the disk drive is either absent or non-functional and the loop bypasses the hard disk. The “disk bypassed” mode is enabled by pulling the BYPASS[n]- pin low. Leave BYPASS[n]- floating to enable the “disk in loop” mode. HDMP0440s may be cascaded with other members of the HDMP04XX/HDMP-05XX family through the appropriate FM_NODE[n]± and TO_NODE[n]± pins to accommodate any number of hard disks (see Figure 3). The unused cells in the HDMP-0440 may be bypassed by using pulldown resistors on the BYPASS[n]- pins for these cells. Features • Supports 1.0625 GBd Fibre Channel operation • Supports 1.25 GBd Gigabit Ethernet (GE) operation • Quad PBC in one package • Equalizers on all inputs • High-speed LVPECL I/O • Buffered Line Logic (BLL) outputs (no external bias resistors required) • 0.5 W typical power at VCC = 3.3 V • 44 Pin, 10 mm, low-cost plastic QFP package Applications • RAID, JBOD, BTS cabinets • Two 2:1 muxes • Two 1:2 buffers • 1 ≥ N Gigabit serial buffer • N ≥ 1 Gigabit serial mux HDMP-0440 An HDMP-0440 may also be configured as five 1:1 buffers, as two 2:1 multiplexers or as two 1:2 buffers. CAUTION: As with all semiconductor ICs, it is advised that normal static precautionsb be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (ESD). EQU TTL BLL TO_NODE[0] BYPASS[4]– TTL FM_NODE[4] EQU BLL TO_NODE[4] TTL BYPASS[3]– EQU BLL BLL 1 1 1 1 0 0 0 0 Figure 1. Block diagram of HDMP-0440. 2 BYPASS[n]- INPUT The active low BYPASS[n]- inputs control the data flow through the HDMP-0440. All BYPASS pins are LVTTL and contain internal pullup circuitry. To bypass a port, the appropriate BYPASS[n]- pin should be connected to GND through a 1 kΩ resistor. Otherwise, the BYPASS[n]- inputs should be left to float, as the internal pull-up circuitry will force them high. BYPASS[2]– TTL EQU INPUT All FM_NODE[n]± high-speed differential inputs have an Equalization (EQU) buffer to offset the effects of skin loss and dispersion on PCBs. An external termination resistor is required across all high-speed inputs. The value of the termination resistor should match the PCB trace differential impedance. Alternatively, instead of a single resistor, two resistors in series, with an AC ground between them, FM_NODE[2] EQU BLL TO_NODE[2] BYPASS[1]– EQU FM_NODE[1] TO_NODE[1] FM_NODE[0] Unused outputs should not be left unconnected. Ideally, unused outputs should have their differential pins shorted together with a short PCB trace. If longer traces or transmission lines are connected to the output pins, the lines should be differentially can be connected differentially across the FM_NODE[n]± inputs. The latter configuration attenuates high-frequency common mode noise. FM_NODE[3] BLL OUTPUT All TO_NODE[n]± high-speed differential outputs are driven by a Buffered Line Logic (BLL) circuit that has on-chip source termination, so no external bias resistors are required. The BLL Outputs on the HDMP-0440 are of equal strength and can drive lengthy FR-4 PCB trace. terminated with an appropriate resistor. The value of the termination resistor should match the PCB trace differential impedance. TO_NODE[3] HDMP-0440 Block Diagram SERDES TTL EQU TTL EQU BLL EQU BLL 1 1 TTL EQU BLL 1 2 TTL BLL 1 3 0 0 BYPASS[4]– TO_NODE[4] BYPASS[3]– BYPASS[2]– TO_NODE[2] BYPASS[1]– TO_NODE[1] EQU TO_NODE[0] = TO_LOOP SERDES FM_NODE[4] SERDES FM_NODE[3] SERDES TO_NODE[3] HARD DISK D FM_NODE[2] HARD DISK C FM_NODE[1] HARD DISK B FM_NODE[0] = FM_LOOP HARD DISK A BLL 1 4 0 0 EQU EQU EQU TTL BLL EQU EQU I/O Type Definitions I/O Type Definition I-LVTTL LVTTL Input O-LVTTL LVTTL Output HS_OUT High Speed Output, LVPECL compatible HS_IN High Speed Input C External Circuit Node S Power Supply or Ground BLL 1 1 4 0 TO_NODE[0] = TO_LOOP TTL BLL 3 0 EQU BYPASS[4] BYPASS[3]– TTL EQU 1 2 0 TO_NODE[3] TTL BLL 1 1 0 EQU BLL 1 Figure 3. Connection diagram for multiple HDMP-0440s. 3 TTL BLL 4 0 TO_NODE[2] TO_NODE[1] EQU BLL 1 3 0 TTL EQU BLL 1 2 0 BYPASS[4]– TO_NODE[4] TTL BLL 1 1 TO_NODE[3] TO_NODE[2] TTL BLL FM_NODE[4] SERDES TO_NODE[4] SERDES FM_NODE[3] SERDES BYPASS[2]– SERDES FM_NODE[2] SERDES BYPASS[1]– SERDES FM_NODE[1] SERDES FM_NODE[0] SERDES TO_NODE[0] HARD DISK G FM_NODE[4] HARD DISK F BYPASS[3]– HARD DISK E FM_NODE[3] HARD DISK H BYPASS[2]– HARD DISK D FM_NODE[2] HARD DISK C BYPASS[1]– HARD DISK B FM_NODE[1] HARD DISK A TO_NODE[1] FM_NODE[0] = FM_LOOP Figure 2. Connection diagram for disk array applications. 0 Pin Definitions Pin Name Pin Pin Type Pin Description TO_NODE[0]+ TO_NODE[0]TO_NODE[1]+ TO_NODE[1]TO_NODE[2]+ TO_NODE[2]TO_NODE[3]+ TO_NODE[3]TO_NODE[4]+ TO_NODE[4]- 24 25 07 06 44 43 38 37 31 30 HS_OUT Serial Data Outputs: High-speed outputs to a hard disk drive or to a cable. FM_NODE[0]+ FM_NODE[0]FM_NODE[1]+ FM_NODE[1]FM_NODE[2]+ FM_NODE[2]FM_NODE[3]+ FM_NODE[3]FM_NODE[4]+ FM_NODE[4]- 10 09 04 03 41 40 35 34 28 27 HS_IN Serial Data Inputs: High-speed inputs from a hard disk drive or from a cable. BYPASS[0]BYPASS[1]BYPASS[2]BYPASS[3]BYPASS[4]- 14 15 16 17 18 I-LVTTL Bypass Inputs: For “disk bypassed” mode, connect BYPASS[n]- to GND through a 1 kΩ resistor. For “disk in loop” mode, float HIGH. GND 01 08 11 12 13 19 22 23 33 39 S Ground: Normally 0 V. See Figure 9 for Recommended Power Supply Filtering. VCCHS[0] VCCHS[1] VCCHS[2] VCCHS[3] VCCHS[4] 26 05 42 36 29 S S S S S High Speed Supply: Normally 3.3 V. Used only for high-speed outputs( TO_NODE[n]). See Figure 9 for Recommended Power Supply Filtering. VCC 02 14 20 21 32 S Logic Power Supply: Normally 3.3 V. Used for internal logic. See Figure 9 for Recommended Power Supply Filtering. 4 Absolute Maximum Ratings TA = 25°C, except as specified. Operation in excess of any of these conditions may result in permanent damage to this device. Continuous operation at these minimum or maximum ratings is not recommended. Symbol Parameter Units Min. Max. VCC Supply Voltage V –0.5 4.0 VIN,LVTTL LVTTL Input Voltage V –0.5 VCC + 0.5[1] VIN,HS_IN HS_IN Input Voltage (Differential) mV 200 2000 IO,LVTTL LVTTL Output Sink/Source Current mA Tstg Storage Temperature °C –65 +150 Tj Junction Temperature °C 0 +125 ±13 Note: 1. Must remain less than or equal to absolute maximum VCC voltage of 4.0 V. DC Electrical Specifications TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V. Symbol Parameter Units Min. VIH,LVTTL LVTTL Input High Voltage Range V 2.0 VIL,LVTTL LVTTL Input Low Voltage Range V VOH,LVTTL LVTTL Output High Voltage Range, IOH = -400 µA V 2.2 VCC VOL,LVTTL LVTTL Output Low Voltage Level, IOL = 1 mA V 0 0.6 IIH,LVTTL Input High Current (Magnitude), VIN = 2.4 V, VCC = 3.45 V µA 40 IIL,LVTTL Input Low Current (Magnitude), VIN = 0.4 V, VCC = 3.45 V µA –600 ICC Total Supply Current, TA = 25°C mA 5 Typ. Max. 0.8 150 185 AC Electrical Specifications TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V. Symbol Parameter Units TLOOP_LAT Total Loop Latency from FM_NODE[0] to TO_NODE[0] ns 2.0 TCELL_LAT Per Cell Latency from FM_NODE[4] to TO_NODE[0] ns 0.8 tr,LVTTLin Input LVTTL Rise Time Requirement, 0.8 V to 2.0 V ns 2.0 tf,LVTTLin Input LVTTL Fall Time Requirement, 2.0 V to 0.8 V ns 2.0 tr,LVTTLout Output TTL Rise Time, 0.8 V to 2.0 V, 10 pF Load ns 1.7 3.3 tf,LVTTLout Output TLL Fall Time, 2.0 V to 0.8 V, 10 pF Load ns 1.7 2.4 trs,HS_OUT HS_OUT Single-Ended Rise Time, 20% to 80% ps 200 30 tfs,HS_OUT HS_OUT Single-Ended Fall Time, 20% to 80% ps 200 300 trd,HS_OUT HS_OUT Differential Rise Time, 20% to 80% ps 200 300 tfd,HS_OUT HS_OUT Differential Fall Time, 20% to 80% ps 200 30 VIP,HS_IN HS_IN Required Pk-Pk Differential Input Voltage mV 200 1200 2000 VOP,HS_OUT HS_OUT Pk-Pk Differential Output Voltage (Z0 = 75 Ω, Figure 6) mV 1100 1400 2000 Guaranteed Operating Rates TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V. FC Serial Clock Rate (MBd) Min. Max. GE Serial Clock Rate (MBd) Min. Max. 1,040 1,240 1,080 1,260 Figue 4. Eye diagram of TO_NODE[1]± high speed differential output (50 Ω termination). Note: Measurement taken with a 27-1 PRBS input to FM_NODE[1]±. 6 Min. Typ. Max. Simplified I/O Cells O_LVTTL I_LVTTL VCC VCC VCC VBB 1.4 V GND GND ESD PROTECTION ESD PROTECTION GND Figure 5. O-LVTTL and I-LVTTL simplified circuit schematic. HS_OUT HS_IN VCC VCCHS 75 Ω + – VCC TO_NODE[n]+ + – VCC Z0 = 75 Ω 0.01 µF FM_NODE[n]+ 2*Z0 = 150 Ω TO_NODE[n]– Z0 = 75 Ω GND 0.01 µF FM_NODE[n]– GND ESD ESD PROTECTION PROTECTION GND GND NOTE: 1. FM_NODE[n] INPUTS SHOULD NEVER BE CONNECTED TO GROUND AS PERMANENT DAMAGE TO THE DEVICE MAY RESULT. Figure 6. HS_OUT and HS_IN simplified circuit schematic. 7 Package Information Power Dissipation and Thermal Resistance. TA = 0°C to +70°C, VCC = 3.15 V to 3.45 V. Symbol Parameter Units Typ. Max. PD Power Dissipation mW 500 640 Θjc[1] Thermal Resistance, Junction to Case °C/W 7 Note: 1. Based on independent package testing by Agilent. Θja for this device is 57ºC/W. Θja is measured on a standard 3x3” FR4 PCB in a still air environment. To determine the actual junction temperature in a given application, use the following equation: Tj = TC + (Θja x PD), where TC is the case temperature measured on the top center of the package and PD is the power being dissipated. Item Details Package Material Plastic Lead Finish Material 85% Tin, 15% Lead Lead Finish Thickness 200-800 micro-inches Lead Skew 0.33 mm max Lead Coplanarity (Seating Plane) 0.10 mm max Mechanical Dimensions PIN #1 ID 1 2 44 43 42 41 40 39 38 37 36 35 34 33 32 3 4 5 31 30 29 TOP VIEW E E1 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 D1 D A2 c A SEATING PLANE A1 b 0.25 GUAGE PLANE L e ALL DIMENSIONS ARE IN MILLIMETERS PART NUMBER E1/D1 HDMP-0440 TOLERANCE Figure 7. HDMP-0440 package drawing. 8 10.00 E/D b e L c A2 A1 A 13.20 0.35 0.80 0.88 0.23 2.00 0.25 2.45 ± 0.10 ± 0.20 ± 0.05 BASIC + 0.15/ MAX. + 0.10/ ± 0.25 – 0.10 – 0.05 MAX. FM_NODE[3]– FM_NODE[3]+ VCCHS[3] TO_NODE[3]– GND TO_NODE[3]+ FM_NODE[2]– FM_NODE[2]+ VCCHS[2] TO_NODE[2]– TO_NODE[2]+ Pin Diagram and Recommended Supply Filtering 44 43 42 41 40 39 38 37 36 35 34 GND 1 33 VCC 2 32 VCC FM_NODE [1]– 3 31 TO_NODE[4]+ FM_NODE [1]+ 4 30 TO_NODE[4]– VCCHS[1] 5 29 VCCHS[4] TO_NODE [1]– 6 28 FM_NODE[4]+ TO_NODE [1]+ 7 27 FM_NODE[4]– GND 8 26 VCCHS[0] FM_NODE [0]– 9 25 TO_NODE[0]– FM_NODE [0]+ 10 24 TO_NODE[0]+ GND 11 23 GND Agilent HDMP-0440 nnnn-nnn Rz.zz S YYWW GND GND VCC SD GND BYPASS[4]– BYPASS[3]– BYPASS[2]– BYPASS[1]– BYPASS[0]– GND GND 12 13 14 15 16 17 18 19 20 21 22 nnnn-nnn = WAFER LOT – BUILD NUMBER; Rz.zz = DIE REVISION; S = SUPPLIER CODE YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK); COUNTRY = COUNTRY OF MANUFACTURE (ON BACK SIDE) VCC GND VCC Figure 8. HDMP-0440 package layout and marking, top view. 44 43 42 41 40 39 38 37 36 35 34 GND VCC VCC 1 33 2 32 3 31 4 30 5 GND VCC 28 7 27 8 26 9 25 10 24 11 23 GND VCC GND GND GND 12 13 14 15 16 17 18 19 20 21 22 CAPACITORS = 0.1 µF (EXCEPT WHERE NOTED). Figure 9. Recommended power supply filtering. 9 VCC 10 µF 29 HDMP-0440 6 GND GND VCC GND www.agilent.com/semiconductors For product information and a complete list of distributors, please go to our web site. For technical assistance call: Americas/Canada: +1 (800) 235-0312 or (408) 654-8675 Europe: +49 (0) 6441 92460 China: 10800 650 0017 Hong Kong: (+65) 6756 2394 India, Australia, New Zealand: (+65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (+65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (+65) 6755 2044 Taiwan: (+65) 6755 1843 Data subject to change. Copyright © 2003 Agilent Technologies, Inc. April 3, 2003 5988-8563EN