KB HE85750

King Billion Electronics Co., Ltd
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有
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公
司
HE85750
HE80000 SERIES
1. General Description
HE85750 is a member of 8-bit Micro-controller series developed by King Billion Electronics Ltd. Users
can chose 32 COM for any one of combination among 【2048 dots LCD Driver + 12 Bit I/O Port】…
【1280 dots LCD Driver + 36 Bit I/O Port】etc.. or 48COM for any one of combination among 【2304
dots LCD Driver + 12 Bit I/O Port】…【1152 dots LCD Driver + 36 Bit I/O Port】etc.. The built-in OP
comparator can be used with (light、voice、temperature、humility) sensor and used as battery low detection.
And the 7-bit current-type D/A converter and PWM device provide the complete speech output
mechanism. The 256KB ROM and 2KB RAM Size can be used in the storage of large speech data,
graphic, text etc. It can be applicable to the medium systems such as Small-Scale Dictionary, Data Bank,
Medium Level Educational Toy, Lower Second Voice Recording System etc..
The instruction set of HE85750 is easy to learn and simple to use. Only 32 instructions with four
addressing modes are provided. Most instructions take only 3 oscillator clocks. The processing power is
adequate for most battery operation systems.
2. Features
z Operation Voltage:
z System Clock:
z
z
z
z
z
z
z
z
z
z
z
z
z
z
2.4V ~ 3.6V
DC ~ 8MHz @ 3.6V
DC ~ 4MHz @ 2.4V
Internal ROM:
256K Bytes(64K Program ROM, 192K Data ROM)
Internal RAM:
2K Bytes.
Dual Clock System: Fast clock:
32768 ~ 8MHz (No Internal Clock)
Slow clock: 32.768 Hz
4 Operation Mode:
Fast, Slow, Idle, Sleep modes.
Watch Dog Timer to prevent deadlock condition.
12~36 bit Bi-directional I/O port. Mask Option can select PUSH-PULL or OPEN DRAIN output
mode for each I/O pin.
2048~1280 dots LCD driver for 32 COM or 2304~1152 dots LCD driver for 48 COM (B TYPE
selectable). LV3 must less than 8.5V.
LCD refresh cycle of 85750 is different from other’s 64 Hz. For this IC:
32 COM: Refresh Cycle=~170Hz，48 COM: Refresh Cycle=~110Hz.
7-bit current-type DAC output.
built-in OP comparator.
PWM device.
Two external interrupts and three internal timer interrupts.
Two 16-bit timer and one Time Base.
Instruction set: 32 instructions with 4 addressing modes. 11-bit DATA POINTER for RAM and
18-bit TABLE POINTER for ROM.
2003/7/30
1
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
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股
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有
限
公
司
HE85750
HE80000 SERIES
3. Internal Block
Please always keep in mind that ICE is different from IC. ICE is the whole set of HE80000 series IC, but
each IC is a subset of ICE. Never use any hardware resource that real IC didn't have, especially RAM and
register. KBIDS and compiler cannot prevent user to use some hardware resource that didn't exist. Please
check the following table and refer the abbreviation in HE80000 user's manual.
I.F.C. E.S.C. I.P.R PROM
DROM
TP
TP+1 RAM PP DP I/O DTMF WDT Timer
◎
◎
◎ 64KB
◎
◎ T1,T2,TB
192KB
18-bit
2KB 3-bit 8-bit 12~36 —
VO DAO OP PWM
LCD
COM*SEG
Bias Rgr ChrgPmp LV2 LR LVG REC S.R.
◎
◎ 4:0 ◎
— ◎ ◎ 2304~1152 32*64,48*48 1/7, 1/8 — 1,3/2,2,3
—
—
Pin No
19,
18
Pin Name
FXI,
FXO
22,
21
SXI,
SXO
17
RSTP_N
20
TSTP_P
2003/7/30
PRTC7
PRTC6
PRTC5
PRTC4
C0M16
C0M17
C0M18
C0M19
C0M20
C0M21
C0M22
C0M23
C0M24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
PWM
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
66
65
64
63
62
61
60
59
58
57
56
55
54
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
33
VDD
PRTD7
PRTD6
PRTD5
PRTD4
PRTD3
PRTD2
PRTD1
PRTD0
GND_PWM
23
24
25
26
27
28
29
30
31
32
22
SXI
HE85750
LC1
LC2
LV1
LV2
LV3
LR4
LR3
LR2
LR1
LR0
LVG
GND
VO
OPIN
OPIP
OPO
RSTP_N
FXO
FXI
TSTP_P
SXO
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
121
122
123
124
125
126
127
128
129
130
131
132
133
COM13
COM14
COM15
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
CMSG47
CMSG46
CMSG45
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
4. Pin Description
I/O
Function
Description
External
fast
clock
pin. Mask option setting：
B, Connecting to crystal or RC to MO_FCK/SCKN= 00：Slow Clock only
O generate 32.768 kHz ~ 8MHz
01：Illegal
frequency.
10：Dual Clock
11：Fast Clock only
MO_FOSCE = 0：Internal fast osc.
External
slow
clock
pin.
= 1：External fast osc.
Connecting with 32768 Hz MO_FXTAL = 0：RC osc. for fast clock
crystal or resistor as slow clock
= 1：X’tal osc. for fast clock
I,
and providing clock source for
MO_SXTAL
=
0：RC for 32768 Hz clock
O
LCD
display,
TIMER1,
= 1：X’tal for 32768 Hz clock
Time-Base and other internal
Use
OP1
and
OP2 to switch among different operation mode
blocks.
(NORMAL, SLOW, IDEL and SLEEP). In Dual Clock
mode, the main system clock is still the Fast Clock. The
32768 Hz clock is for LCD and Timer 1 only.
Level trigger, active low. Except for using this pin, using
mask option (MO_PORE=1) could enable IC build-in
Power-on reset circuit.
I System Reset.
Besides, MO_WDTE can set Watch Dog Timer：
MO_WDTE=0：Disable Watch Dog Timer
=1：Enable Watch Dog Timer
Please bond this pin and add a test point on PCB for
I Test Pin
debugging. Please connect this pin with zero ohm resistor
to GND.
2
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
Pin No
Pin Name
34..
37
PRTC[7:4]
24..
31
PRTD[7:0]
94..
101
PRT14[7:0]/
SEG[23:16]
102..
109
110..
117
PRT15[7:0]/
SEG[15:8]
PRT17[7:0]/
SEG[7:0]
53..38
118..
COM[31:0]
133
69..54 CMSG[47:32]
70..93 SEG[47:24]
2
LC2
1
LC1
5
L V3
4
L V2
3
L V1
6..10
LR[4..0]
11
L VG
33
PWM
13
14
15
16
23
12
32
VO
OPIN
OPIP
OPO
VDD
GND
GND_PWM
2003/7/30
I/O
B
B
B/
O
B/
O
B/
O
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Function
有
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公
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HE85750
HE80000 SERIES
Description
Mask options：
MO_CPP[7..5]=1 ~ Push-pull.
4-pin bi-directional I/O port.
=0 ~ Open-drain.
Output must be “1” before reading whenever
input (No tri-state structure).
Mask options：
8-pin bi-directional I/O port.
MO_DPP[7..0]=1 ~ Push-pull.
PRTD[7..2] as wake-up pin.
=0 ~ Open-drain.
PRTD[7..6] as external interrupt
Output
must
be
“1”
before reading whenever
pin.
input (No tri-state structure).
Mask options：
MO_LIO14[7..0]=1 ~ LCD Pin.
=0 ~ I/O Pin.
8-pin bi-directional I/O port that
MO_14PP[7..0]=1
~ Push-pull.
is shared with LCD segment pin.
=0 ~ Open-drain.
Output must be “1” before reading whenever
input (No tri-state structure).
Mask options：
MO_LIO15[7..0]=1 ~ LCD Pin.
=0 ~ I/O Pin.
8-pin bi-directional I/O port that
MO_15PP[7..0]=1
~ Push-pull.
is shared with LCD segment pin.
=0 ~ Open-drain.
Output must be “1” before reading whenever
input (No tri-state structure).
Mask options：
MO_LIO17[7..0]=1 ~ LCD Pin.
=0 ~ I/O Pin.
8-pin bi-directional I/O port that
MO_17PP[7..0]=1
~ Push-pull.
is shared with LCD segment pin.
=0 ~ Open-drain.
Output must be “1” before reading whenever
input (No tri-state structure).
O LCD COMMON Output
uses them as
uses them as
uses them as
uses them as
uses them as
LCD Data filled from PAGE 6 and 7, please refer the LCD
RAM map.
O
O
B
B
B
B
B
B
I
COM[47:32] / SEG[48:63]
LCD SEGMENT Output
Charge Pump Switch 1
Add one 0.1 µF capacitor between LC1 and LC2. Please
refer the application circuit.
Charge Pump Switch 2
Charge Pump V3
LV3< 8.5 Volts.
Charge Pump V2
Please refer the application circuit.
Charge Pump V1
LCD Resister level 4 ~ 1
Please refer the application circuit.
LCD Virtual Ground
Please refer the application circuit.
The PWM positive output can
Set the bit2 of VOC register as one to turn on PWM.
O
drive speaker or buzzer directly.
O D/A output.
Bit 1 of VOC = ‘1’ , Turn on DA
I DAC Voice Output
Set the VOC[1] (DA=1) to turn on DAC with VO output.
I OPAMP negative input pin.
Built-in OP comparator. Set the VOC[0] = ‘1’ , Turn on OP
O OPAMP positive input pin.
P OPAMP output pin.
All of power must connect to power source, can not be
P Power Ground Input
floating.
P Dedicated PWM Ground
3
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
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股
份
有
限
公
司
HE85750
HE80000 SERIES
5. Pad Location
C
M
S
G
[4
4]
C
M
S
G
[4
1]
C
M
S
G
[4
0]
C
M
S
G
[3
9]
C
M
S
G
[3
8]
C
M
S
G
[3
7]
C
M
S
G
[3
6]
C
M
S
G
[3
5]
C
M
S
G
[3
4]
C
M
S
G
[3
3]
C
M
S
G
[3
2]
COM[31]
COM[30]
COM[29]
COM[28]
COM[27]
COM[26]
COM[25]
COM[24]
COM[23]
COM[22]
COM[21]
COM[20]
COM[19]
COM[18]
COM[17]
COM[16]
PRTC[4]
PRTC[5]
PRTC[6]
PRTC[7]
PWM
Die Size: 7290 µm * 1760 µm。
Substrate connect with GND。
GND_PWM
PRTD[0]
PRTD[1]
PRTD[2]
PRTD[3]
PRTD[4]
PRTD[5]
PRTD[6]
PRTD[7]
VDD
SXI
C
O
M
[1
2]
2003/7/30
C
M
S
G
[4
2]
Product Name
CMSG[45]
CMSG[46]
CMSG[47]
SEG[47]
SEG[46]
SEG[45]
SEG[44]
SGKY[43]
SGKY[42]
SGKY[41]
SGKY[40]
SGKY[39]
SGKY[38]
SGKY[37]
SGKY[36]
SGKY[35]
SGKY[34]
SGKY[33]
SGKY[32]
SGKY[31]
SGKY[30]
SGKY[29]
SGKY[28]
SGKY[27]
SGKY[26]
SGKY[25]
SGKY[24]
PRT14[7]
PRT14[6]
PRT14[5]
PRT14[4]
PRT14[3]
PRT14[2]
PRT14[1]
PRT14[0]
PRT15[7]
PRT15[6]
PRT15[5]
PRT15[4]
PRT15[3]
PRT15[2]
PRT15[1]
PRT15[0]
PRT17[7]
PRT17[6]
PRT17[5]
PRT17[4]
PRT17[3]
PRT17[2]
PRT17[1]
PRT17[0]
COM[15]
COM[14]
COM[13]
C
M
S
G
[4
3]
C
O
M
[1
1]
C
O
M
[1
0]
SXO
TSTP_P
FXI
FXO
RSTP_N
OPO
OPIP
OPIN
VO
GND
LVG
LR0
LR1
LR2
LR3
LR4
LV3
LV2
LV1
LC2
LC1
C C C C C C C C C C
O O O O O O O O O O
M M M M M M M M M M
[9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
4
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
PIN
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
2003/7/30
億
電
子
股
份
PIN
X
Y
Name
Coordinate Coordinate
LC1
3149.55
815.00
LC2
3033.65
815.00
LV1
2917.75
815.00
LV2
2801.85
815.00
LV3
2685.95
815.00
LR4
2570.05
815.00
LR3
2454.15
815.00
LR2
2338.25
815.00
LR1
2222.35
815.00
LR0
2106.45
815.00
LVG
1990.55
815.00
GND
1874.65
815.00
VO
1758.75
815.00
OPIN
1642.85
815.00
OPIP
1526.95
815.00
OPO
1411.05
815.00
RSTP_N
1295.15
815.00
FXO
1179.25
815.00
FXI
1063.35
815.00
TSTP_P
947.45
815.00
SXO
831.55
815.00
SXI
675.55
815.00
VDD
424.55
815.00
PRTD[7]
308.65
815.00
PRTD[6]
192.75
815.00
PRTD[5]
76.85
815.00
PRTD[4]
-39.05
815.00
PRTD[3]
-154.95
815.00
PRTD[2]
-270.85
815.00
PRTD[1]
-386.75
815.00
PRTD[0]
-502.65
815.00
GND_PWM -618.15
815.00
PWM
-778.90
815.00
PRTC[7]
-943.55
815.00
PRTC[6]
-1059.45
815.00
PRTC[5]
-1175.35
815.00
PRTC[4]
-1291.25
815.00
COM[16] -1409.15
815.00
COM[17] -1525.05
815.00
COM[18] -1640.95
815.00
COM[19] -1756.85
815.00
COM[20] -1872.75
815.00
COM[21] -1988.65
815.00
COM[22] -2104.55
815.00
有
PIN
Number
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
5
限
公
司
HE85750
HE80000 SERIES
PIN
X
Y
Name
Coordinate Coordinate
CMSG[46] -2975.90
-815.00
CMSG[47] -2860.00
-815.00
SEG[47]
-2744.10
-815.00
SEG[46]
-2628.20
-815.00
SEG[45]
-2512.30
-815.00
SEG[44]
-2396.40
-815.00
SGKY[43] -2280.50
-815.00
SGKY[42] -2164.60
-815.00
SGKY[41] -2048.70
-815.00
SGKY[40] -1932.80
-815.00
SGKY[39] -1816.90
-815.00
SGKY[38] -1659.60
-815.00
SGKY[37] -1543.70
-815.00
SGKY[36] -1427.80
-815.00
SGKY[35] -1311.90
-815.00
SGKY[34] -1196.00
-815.00
SGKY[33] -1080.10
-815.00
SGKY[32] -964.20
-815.00
SGKY[31] -848.30
-815.00
SGKY[30] -732.40
-815.00
SGKY[29] -616.50
-815.00
SGKY[28] -500.60
-815.00
SGKY[27] -384.70
-815.00
SGKY[26] -268.80
-815.00
SGKY[25] -152.90
-815.00
SGKY[24]
-37.00
-815.00
PRT14[7]
94.20
-815.00
PRT14[6]
210.10
-815.00
PRT14[5]
326.00
-815.00
PRT14[4]
441.90
-815.00
PRT14[3]
557.80
-815.00
PRT14[2]
673.70
-815.00
PRT14[1]
789.60
-815.00
PRT14[0]
905.50
-815.00
PRT15[7]
1021.40
-815.00
PRT15[6]
1137.30
-815.00
PRT15[5]
1253.20
-815.00
PRT15[4]
1369.10
-815.00
PRT15[3]
1485.00
-815.00
PRT15[2]
1600.90
-815.00
PRT15[1]
1716.80
-815.00
PRT15[0]
1832.70
-815.00
PRT17[7]
1948.60
-815.00
PRT17[6]
2064.50
-815.00
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
PIN
Number
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
億
電
子
股
份
PIN
X
Y
Name
Coordinate Coordinate
COM[23] -2220.45
815.00
COM[24] -2336.35
815.00
COM[25] -2452.25
815.00
COM[26] -2568.15
815.00
COM[27] -2684.05
815.00
COM[28] -2799.95
815.00
COM[29] -2915.85
815.00
COM[30] -3031.75
815.00
COM[31] -3147.65
815.00
CMSG[32] -3580.00
701.00
CMSG[33] -3580.00
585.10
CMSG[34] -3580.00
469.20
CMSG[35] -3580.00
353.30
CMSG[36] -3580.00
237.40
CMSG[37] -3580.00
121.50
CMSG[38] -3580.00
5.60
CMSG[39] -3580.00
-110.30
CMSG[40] -3580.00
-226.20
CMSG[41] -3580.00
-342.10
CMSG[42] -3580.00
-458.00
CMSG[43] -3580.00
-573.90
CMSG[44] -3580.00
-689.80
CMSG[45] -3091.80
-815.00
有
限
PIN
Number
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
公
HE85750
司
HE80000 SERIES
PIN
X
Y
Name
Coordinate Coordinate
PRT17[5]
2180.40
-815.00
PRT17[4]
2296.30
-815.00
PRT17[3]
2412.20
-815.00
PRT17[2]
2528.10
-815.00
PRT17[1]
2644.00
-815.00
PRT17[0]
2759.90
-815.00
COM[15]
2894.85
-815.00
COM[14]
3010.75
-815.00
COM[13]
3126.65
-815.00
COM[12]
3580.00
-708.95
COM[11]
3580.00
-593.05
COM[10]
3580.00
-477.15
COM[9]
3580.00
-361.25
COM[8]
3580.00
-245.35
COM[7]
3580.00
-129.45
COM[6]
3580.00
-13.55
COM[5]
3580.00
102.35
COM[4]
3580.00
218.25
COM[3]
3580.00
334.15
COM[2]
3580.00
450.05
COM[1]
3580.00
597.05
COM[0]
3580.00
712.95
6. LCD Power Supply
The LCD power supply is equipped with voltage charge-pump, and bias voltage generating resistor
network. The input power VDD of MCU is charge-pumped to generate LV3. The voltage of LV3 may be
up to 1, 2 or 3 times of VDD depending on the external capacitor configurations and VDD connection.
LV3=VDD
VDD
VOLTAGE DOUBLER
LV3=2XVDD
LV3
LV2
LV1
LV2
LV1
LV3
LC2
LC2
LC1
LC1
VDD
VOLTAGE TRIPLER
LV3=3XVDD
VDD
LV1
LV2
LV3
1uF
104
1uF
LC2
1uF
104
1uF
LC1
The bias voltages for LCD driver are then generated from LV3 using the internally resistor voltage
dividing network if the mask option MO_LCDBE is set to ‘1’ and the resistance of bias voltage
generating network can be adjusted by mask option MO_LCDBS[2..0]. Users may select options with
smaller resistance to get stronger bias voltages as needed when driving larger LCD panel. However the
bias network will consume more power as consequence. Therefore uses must trade off between bias
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strength and power consumption. Users also can disable the internal bias circuit and use the external
resistor bias circuit by setting the mask option MO_LCDBE to ‘0’. The LVG pin can be connected to
ground directly or connecting to a variable resistor to fine-tune the LCD contrast as below diagram
shown.
Mask Option MO_LCDBE='1', the
internal bias circuit is
enabled; otherwise user shall
use external resistors bias
circuit which is like resistor
Rx between LR0~4
External Bias Circuit
Internal Bias Circuit
LV3
R
Cx
Rx
R
LR4
Cx
Rx
LR3
Cx
3/4Rx
3R/4R
LR2
1/7 Bias Resistance=3R
1/8 Bias Resistance=4R
R
Cx
Rx
LR1
R
Cx
Rx
3
LR0
2
R= GRAY x1.2K
1
GRAY=LCDC[7..2]
LCDE
LVG
VR
LVG can be connected to
GND directly or through
a resistor VR to GND
VSS
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MO_LCDBS LCD Bias R ≈
000
30K ohm
001
60K ohm
010
90K ohm
011
120K ohm
100
210K ohm
101
240K ohm
110
270K ohm
111
300K ohm
6.1. LCDC Control register
The contrast of LCD panel can be adjusted by GRAY bits of LCDC register.
LCDC
Field
Reset
bit 7
-
Field
Value
000000
GRAY
111111
0
BLANK
1
LCDE
0
1
bit 6
bit 5
bit 4
bit 3
GRAY (Contrast adjustment)
-
bit 2
-
bit 1
bit 0
BLANK LCDE
0
0
Function
LCD is darkest
LCD is lightest
Normal display
LCD display blanked. LCD driver changes only COM output signal, SEG
signal remains unchanged.
LCD driver disabled, LCD driver has no output signal.
LCD driver Enabled
Please note that LCD driver must be turned off before the entering sleep mode. That means user must
clear the bit 0 of LCDC to turn off LCD driving circuit before setting bit6 of OP1 to enter sleep mode.
Large current might happen if the procedure is not followed.
Please also note that LCD driver uses slow clock as clock source. The LCD display will not display
normally if it works in Fast clock only mode because the LCD refresh action is too fast.
There are two LCD driver configurations.
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7. LCD RAM Map
There are two LCD configurations 32/48 COM, user shall write the display data into the related LCD
RAM map location to obtain the correct the display image.
32 COM:
Page
7
COM0
COM1
COM2
:
:
COM29
COM30
COM31
48 COM:
Page
6, 7
COM0
COM1
:
COM15
COM16
:
COM31
COM32
:
COM46
COM47
SEG
[7:0]
7E0H
7E1H
7E2H
:
:
7FDH
7FEH
7FFH
SEG
[15:8]
7C0H
7C1H
7C2H
:
:
7DDH
7DEH
7DFH
SEG
[7:0]
7C0H
7C1H
:
7CFH
7D0H
:
7DFH
7E0H
:
7EEH
7EFH
SEG
[23:16]
7A0H
7A1H
7A2H
:
:
7BDH
7BEH
7BFH
SEG
[15:8]
780H
781H
:
78FH
790H
:
79FH
7A0H
:
7AEH
7AFH
SEG
[31:24]
780H
781H
782H
:
:
79DH
79EH
79FH
SEG
[23:16]
740H
741H
:
74FH
750H
:
75FH
760H
:
76EH
76FH
SEG
[39:32]
760H
761H
762H
:
:
77DH
77EH
77FH
SEG
[47:40]
740H
741H
742H
:
:
75DH
75EH
75FH
SEG
[31:24]
700H
701H
:
70FH
710H
:
71FH
720H
:
72EH
72FH
SEG
[55:48]
720H
721H
722H
:
:
73DH
73EH
73FH
SEG
[39:32]
6C0H
6C1H
:
6CFH
6D0H
:
6DFH
6E0H
:
6EEH
6EFH
SEG
[63:56]
700H
701H
702H
:
:
71DH
71EH
71FH
SEG
[47:40]
680H
681H
:
68FH
690H
:
69FH
6A0H
:
6AEH
6AFH
8. Oscillators
The MCU is equipped with two clock sources with a variety of selections on the types of oscillators to
choose from. So that system designer can select oscillator types based on the cost target, timing accuracy
requirements etc.
2003/7/30
OP1
Field
BIT7
DRDY
BIT6
STOP
BIT5
SLOW
BIT4
INTE
BIT3
T2E
BIT2
T1E
BIT1
Z
BIT0
C
OP2
Field
BIT7
IDLE
BIT6
PNWK
BIT5
TCWK
BIT4
TBE
BIT3
BIT2
BIT1
TBS[3..0]
BIT0
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Crystal, Resonator or the RC oscillator can be used as fast clock source, components should be placed as
close to the pins as possible. The type of oscillator used is selected by mask option MO_FXTAL.
VDD
FXI
FXI
FXO
Crystal Osc.
RC Osc.
MO_FXTAL Fast clock type
0
RC Oscillator.
1
Crystal Oscillator.
Slow clock is the clock source for LCD display, Timer1, and Timer Base, etc. Two types of oscillator,
crystal and RC, can be used as slow clock by mask option MO_SXTAL. If used for time keeping function
or other applications that required the accurate timing, crystal oscillator is recommended. If the timing
accuracy is not important, then RC type oscillator can be used to reduce cost.
MO_SXTAL Slow clock type
0
R/C oscillator
1
Crystal oscillator
SXI
SXI
SXO
SXO
Crystal Osc.
RC Osc.
With two clock sources available, the system operation modes can be switched among normal, slow, idle,
and sleep modes by the setting of OP1 and OP2 registers as shown in tables below to suit the needs of
application such as power saving, etc. If the dual clock mode is used, the LCD display, Timer1 and Timer
Base will derive its clock source from slow clock while the other blocks will operate with the fast clock.
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9. General Purpose I/O
There are two dedicated general purpose I/O port, PRTC[7..4] and PRTD, while PRT14, PRT15 and
PRT17 are multiplexed with LCD segment driver pins. All the I/O ports are bi-directional and of nontri-state output structure. The output has weak sourcing (50 µA) and stronger sinking (1 mA) capability
and each can be configured as push-pull or open-drain output structure individually by mask option.
When the I/O port is used as input, the weakly high sourcing can be used as weakly pull-up. Open drain
can be used if the pull-up is not required and let the external driver to drive the pin. Please note that a
floating pad could cause more power consumption since the noise could interfere with the circuit and
cause the input to toggle. A ‘1’ needs to be written to port first before reading the input data from the I/O
pin. If the PMOS is used as pull-up, care should be taken to avoid the constant power drain by DC path
between pull-up and external circuit.
The input port has built-in Schmidt trigger to prevent it from chattering. Hysteresis level of Schmidt
trigger is 1/3*VDD.
VDD
DOUT
VDD
Q
LATCH
Q'
MO_?PP
PAD
DIN
SCHMIDT Trigger input
As pads of PRT14, PRT15 and PRT17 are shared with LCD segment driver, the function of the pads is
determined by mask options.
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LIO17=0
LIO17=1
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
LIO15=0
LIO15=1
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
LIO14=0
LIO14=1
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
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Following table is the setting for MO_LIO?[...] and MO_?PP[...] and others related to LCD display
setting and pin assignment features.
MO_LIO?[…] MO_?PP[...]
I/O Port
LCD Pin
0
0
Open-drain output
-0
1
Push-pull output
-1
0
-xx
1
1
-LCD Display
--: Function not available.
xx: Displayable, but may have abnormal leakage current, do not use.
10. Timer1
The Timer1 consists of two 8-bit write-only preload registers T1H and T1L and 16-bit down counter. If
Timer1 is enabled, the counter will decrement by one with each incoming clock pulse. Timer1 interrupt
will be generated when the counter underflows - counts down to FFFFH. And the counter will be
automatically reloaded with the value of T1H and T1L.
The clock source of Timer1 is derived from slow clock “SCK” at dual clock or slow clock only mode.
And it comes from the fast clock “FCK” at fast clock only mode.
Please note that the interrupt is generated when counter counts from 0000H to FFFFH. If the value of
T1H and T1L is N, and count down to FFFFH, the total count is N+1. The content of counter is zero
when system resets. Once it is enabled to count at this moment, interrupt will be generated immediately
and value of T1H and T1L will be loaded since it counts to FFFFH. So the T1H and T1L value should be
set before enabling Timer1.
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T1H
The contents of
T1H and T1L are
almost loaded into
Timer1 immediately
when Timer1 is
enabled after reset.
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Auto reload
when Timer1
is underflow
< Timer1 Counter >
Decreases 1
No
Count To
0xFFFFh
Yes
Timer1
Interrupt
Request
T1_INT
The Timer1 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC1_IER
2
T1L
T1H
0x03
0x04
T1L[7:0]
T1H[7:0]
7~0
7~0
OP1
0x09
TC1E
2
Description
0: TC1 interrupt is disabled. (default)
R/W
1: TC1 interrupt is enabled.
W Low byte of TC1 pre-load value
W High byte of TC1 pre-load value
0: TC1 is disabled. (default)
R/W
1: TC1 is enabled.
11. Timer2
Timer2 is similar in structure to Timer1 except that clock source of Timer2 comes from the system clock
“Fsys”/1.5. The system clock “Fsys” varies depending on the operation modes of the MCU.
The Timer2 consists of two 8-bit write-only preload registers T2H and T2L and 16-bit down counter. If
Timer2 is enabled, counter will decrement by one with each incoming clock pulse. Timer2 interrupt will
be generated when the counter underflows - counts down to FFFFH. And it will be automatically reloaded
with the value of T2H and T2L.
Please note that the interrupt signal is generated when counter counts from 0000H to FFFFH. If the value
of counter is N, and count down to FFFFH, the total count is N+1. The content of counter is zero when
system resets. Once it is enabled to count at this time, the interrupt will be generated immediately and
value of T2H and T2L will be loaded since the counter counts to FFFFH. So the T2H and T2L value
should be set before enabling Timer2.
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T2H
The contents of
T2H and T2L are
almost loaded into
Timer2 immediately
when Timer2 is
enabled after reset.
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Auto reload
when Timer2
is underflow
T2L
< Timer2 Counter >
Decreases 1
No
Count To
0xFFFFh
Timer2
Interrupt
Request
Yes
T2_INT
The Timer2 related control registers are list as below:
Register Address
Field
Bit position Mode
IER
0x02
TC2_IER
1
T2L
T2H
0x05
0x06
T2L[7:0]
T2H[7:0]
7~0
7~0
OP1
0x09
TC2E
3
Description
0: TC2 interrupt is disabled. (default)
R/W
1: TC2 interrupt is enabled.
W Low byte of TC2 pre-load value
W High byte of TC2 pre-load value
0: TC2 is disabled. (default)
R/W
1: TC2 is enabled.
12. Time Base Interrupt
The TB timer is used to generate time-out interrupt at fixed period. The time-out frequency of TB is
determined by dividing slow clock with a factor selected in OP2[3:0]. TBE (Time Base Enable) bit
controls enable or disable of the circuit.
OP2
BIT7
IDLE
BIT6
PNWK
BIT5
TCWK
BIT4
TBE
BIT3
BIT2
BIT1
TBS[3..0]
BIT0
TBE Function
0
Disable Time Base
1
Enable Time Base
For example, if the slow clock is 32768 Hz, then the interrupt frequency is as shown in following table.
TBS[3..0] Interrupt Frequency
0000
16.384 KHz
0001
8.192 KHz
0010
4.096 KHz
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TBS[3..0] Interrupt Frequency
0011
2.048 KHz
0100
1.024 KHz
0101
512 Hz
0110
256 Hz
0111
128 Hz
1000
64 Hz
1001
32 Hz
1010
16 Hz
1011
8 Hz
1100
4 Hz
1101
2 Hz
1110
1 Hz
1111
0.5 Hz
13. Watch Dog Timer
Watch Dog Timer (WDT) is designed to reset system automatically prevent system dead lock caused by
abnormal hardware activities or program execution. WDT needs to be enabled in Mask Option.
MO_WDTE Function
0
WDT disable
1
WDT enable
To use WDT function, “CLRWDT” instruction needs to be executed in every possible program path
when the program runs normally in order to clears the WDT counter before it overflows, so that the
program can operate normally. When abnormal conditions happen to cause the MCU to divert from
normal path, the WDT counter will not be cleared and reset signal will be generated.
WDT is the enabling signal generated by calculating 32768-clock overflow. Reset Register content is
same as TC1 (Timer1 clock), which uses the same clock count source. WDT function can be generated in
Normal, Slow and Idle Mode. However, WDT will not function during Sleep Mode (as the TC1 clock has
stopped.)
14. Digital-to-Analog Converter
The Digital-to-Analog converter (DAC) converts 7-bit unsigned speech data written to PWMC data
register to proportional current.
PWMC register
DA & PWM Data
Control
2003/7/30
Bit 7
0
1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
DA and PWM output value
PWM O/P driver
15
Bit 1
Bit 0
-
PWME
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There are two output paths for the DAC. Either VO or DAO can be selected as output port of DAC by
VOC register when it is enabled. The VO output is primarily intended for speech generation, although it
is not necessary so, while the DAO output path can be used in conjunction with built-in OP comparator to
function as an Analog-to-Digital Converter as required in applications such as speech recording, speech
recognition or sensor interfaces.
OPO
OP
+
-
PWMC[DATA]
DAC
OPIP
OPIN
1
DAO
0
VO
R
VOC[DAC]
VOC[OP]
The DAC is enabled by DAC bit of VOC register. Please note that the DAC bit of VOC register will be
automatically cleared when the system enter Idle or Sleep mode. So it needs to be set again when
returning to Normal mode.
VOC Register
VOC register
Field
Reset
Bit 7
-
Bit 6
-
Bit 5
-
Bit Name Value
1
1
DAC
0
Bit 4
-
Bit 3
-
Bit 2
PWM
0
Bit 1
DAC
0
Bit 0
OP
0
Function description
DA Enable
DA Disable
15. Pulse-Width Modulation
The pulse-width modulator (PWM) converts 7-bit unsigned speech data written to PWMC data register to
proportional duty cycle of PWM output. PWM module shares the PWMC data register with
Digit-to-Analog Converter. So PWM and DA output can exist at the same time. When PWM circuit is
enabled, it generates signal with duty ratio in proportion to the DA value.
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DA = 0x20
DA = 0x80
DA = 0xE0
1 subframe
The PWM bit of VOC register controls register to enable the circuit and output driver. When PWM bit of
VOC is ‘0’, PWME bit and output drivers settings are both cleared. To use PWM for voice output, PWM
bit has to be set to ‘1’ first, then set PWME bit and enable output driver by setting the driver number. If
PWM bit is disabled and enabled again, the setting for driver and PWME bit will be clear.
The Fast Clock is gated through PWME bit of PWMC command register to provide the clock source of
PWM circuit when it is enabled. As PWM needs higher frequency to operate, it cannot generate correct
PWM signal in Slow clock only mode.
When the program enters into Sleep mode or Idle mode, it will automatically turn off all voice outputs by
clearing VOC[2:1] to ”00”. To activate voice output again when returning to Normal Mode, the VOC
register needs to be set again.
The PWM output volume can be adjusted by command register PWMC[6:4]. The bit 6 and 5 control 2
time driver, while bit 4 controls 1 time driver, thus it has 5 levels of driver output. By turning on/off the
internal drivers, the sound level of PWM output can be turned up and down. Please note that this
adjustment apply only to PWM, but not DA output.
PWM output driver selection
PWMC[6..4] Number of Driver
000
off
001
1
010
2
011
3
100
2
101
3
110
4
111
5
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16. Absolute Maximum Rating
Item
Supply Voltage
Input Voltage
Output Voltage
Operating Temperature
Storage Temperature
Sym.
Rating
Vdd
-0.5V ~ 5V
Vin -0.5V ~ Vdd+0.5V
Vo
-0.5V ~ Vdd+0.5V
Top
00C ~ 700C
Tst
-500C ~ 1000C
Condition
17. Recommended Operating Conditions
Item
Supply Voltage
Input Voltage
Operating Frequency
Operating Temperature
Storage Temperature
2003/7/30
Sym.
Rating
Vdd
2.4V ~ 3.6V
Vih
0.9 Vdd ~ Vdd
Vil
0.0V ~ 0.1Vdd
Fmax
8MHz
4MHz
0
Top
0 C ~ 700C
Tst -500C ~ 1000C
18
Condition
Vdd =5.0V
Vdd =2.4V
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18. DC/AC Characteristics
Testing Condition : TEMP=25℃, VDD=3V+/-10%, GND=0V
PARAMETER
CONDITION
IFast NORMAL Mode Current System
ISlow SLOW Mode Current
IIdle
IDLE Mode Current
System
System
ILCD Extra Current if LCD ON System
ISleep Sleep Mode Current
PWM
IoVO DAC Output Current
VO
ViH
Input High Voltage
I/O pins
ViL
Input Low Voltage
I/O pins
IoH Output Drive Current
IoL_1 Output Sink Current
IiL_1 Input Low Current
IiL_2 Input Low Current
2M ext. R/C
32.768K X’tal
LCD Disable
32.769K X’tal
LCD Disable
LCD Enable,
LCD option=128Kohm
LV3=6 Volt
LCD Enable,
LCD option=16Kohm,
LV3=6 Volt
1
1.5
mA
15
30
μA
10
25
μA
65
72
μA
300
System
IPWM PWM Output Current
Vhys Input Hysteresis Width
MIN TYP MAX UNIT
330
1
With 32Ω Loading
With 64Ω Loading
With 100Ω Loading
VDD=3V;VO=0~2V,
Data=7F
10
6
4
14
8
5
μA
mA
mA
mA
2.5
3
mA
0.8
VDD
V
0.2
VDD
Threshold=2/3VDD(input
from low to high)
I/O, RSTP_N
Threshold=1/3VDD(input
from high to low)
*1
I/O pull-high VoL=2.0V
I/O pull-low*1 VoL=0.4V
ViL=GND,
RSTP_N
pull high Internally
ViL=GND,
I/O
if pull high Internally by user
1/3
VDD
50
1.0
V
V
μA
mA
20
μA
100
μA
Note:*1: Drive Current Spec. for Push-Pull I/O port only
Sink Current Spec. for both Push-Pull and Open-Drain I/O port.
*2: This Spec. base on one driver only. There are five build-in driver, so user just multiply the
number of driver he used to one driver current to get the total amount of current.
( IPWM * N; N=0,1,2,3,4,5)
2003/7/30
19
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
HE85750
司
HE80000 SERIES
19. Application Circuit
PRTC7
PRTC6
PRTC5
PRTC4
C0M16
C0M17
C0M18
C0M19
C0M20
C0M21
C0M22
C0M23
C0M24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
PWM
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
+
33p
R
LR4
R
LR3
3R/4R
33p
Rx
Cx
3/4Rx
Cx
Rx
Cx
Rx
Cx
R
BUZZER
47uF
Cx
LR2
1/7 Bias Resistance=3R
1/8 Bias Resistance=4R
PWM
3.0V
Rx
2
22p
LV3
VDD
1uF
22p
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
VDD
0.1uF
32768Hz
1
1uF
33
VDD
PRTD7
PRTD6
PRTD5
PRTD4
PRTD3
PRTD2
PRTD1
PRTD0
GND_PWM
23
24
25
26
27
28
29
30
31
32
22
VDD
0
4 MHz
66
65
64
63
62
61
60
59
58
57
56
55
54
COM31
COM30
COM29
COM28
COM27
COM26
COM25
COM24
COM23
COM22
COM21
COM20
COM19
COM18
COM17
COM16
PRTC4
PRTC5
PRTC6
PRTC7
VDD
0.1uF
PWM
0.1uF
RSTP
PRTD0
PRTD1
PRTD2
PRTD3
PRTD4
PRTD5
PRTD6
PRTD7
SXI
SXO
TSTP
FXI
FXO
RSTP
OPO
OPIP
OPIN
VO
LVG
LR0
LR1
LR2
LR3
LR4
LV3
LV2
LV1
LC2
47K
SXI
LC1
LC2
LV1
LV2
LV3
LR4
LR3
LR2
LR1
LR0
LVG
GND
VO
OPIN
OPIP
OPO
RSTP_N
FXO
FXI
TSTP_P
SXO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
VDD
HE85750
CMSG44
CMSG43
CMSG42
CMSG41
CMSG40
CMSG39
CMSG38
CMSG37
CMSG36
CMSG35
CMSG34
CMSG33
CMSG32
External Bias Circuit
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Internal Bias Circuit
COM13
COM14
COM15
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
SEG40
SEG41
SEG42
SEG43
SEG44
SEG45
SEG46
SEG47
CMSG47
CMSG46
CMSG45
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
CMSG45
CMSG46
CMSG47
SEG47
SEG46
SEG45
SEG44
SGKY43
SGKY42
SGKY41
SGKY40
SGKY39
SGKY38
SGKY37
SGKY36
SGKY35
SGKY34
SGKY33
SGKY32
SGKY31
SGKY30
SGKY29
SGKY28
SGKY27
SGKY26
SGKY25
SGKY24
PRT147
PRT146
PRT145
PRT144
PRT143
PRT142
PRT141
PRT140
PRT157
PRT156
PRT155
PRT154
PRT153
PRT152
PRT151
PRT150
PRT177
PRT176
PRT175
PRT174
PRT173
PRT172
PRT171
PRT170
COM15
COM14
COM13
121
122
123
124
125
126
127
128
129
130
131
132
133
COM12
COM11
COM10
COM9
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
Mask Option MO_LCDBE='1', the
internal bias circuit is
enabled; otherwise user shall
use external resistors bias
circuit which is like resistor
Rx between LR0~4
LR1
VOLTAGE DOUBLER
LV3=2XVDD
LV3
LV2
LV1
LV2
LV1
LV3
LC2
LC2
LC1
LC1
COMXSEG
CMSG32
CMSG33
CMSG34
CMSG35
CMSG36
CMSG37
CMSG38
CMSG39
CMSG40
CMSG41
CMSG42
CMSG43
CMSG44
CMSG45
CMSG46
CMSG47
VDD
1uF
104
VDD
1uF
LC2
32X64
48X48
SEG63
SEG62
SEG61
SEG60
SEG59
SEG58
SEG57
SEG56
SEG55
SEG54
SEG53
SEG52
SEG51
SEG50
SEG49
SEG48
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
PRT150
PRT151
PRT152
PRT153
PRT154
PRT155
PRT156
PRT157
R
SXO
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
R
FXI
LR0
R
1uF
104
1uF
FXI
LC1
SXI
2003/7/30
VDD
LV1
LV2
LV3
SXI
SXO
VOLTAGE TRIPLER
LV3=3XVDD
LIO17=0
LIO17=1
PRT170
PRT171
PRT172
PRT173
PRT174
PRT175
PRT176
PRT177
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
LIO15=0
LIO15=1
LIO14=1
PRT140
PRT141
PRT142
PRT143
PRT144
PRT145
PRT146
PRT147
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
GRAY=LCDC[7..2]
2
R= GRAYx1.2K
C
FXO
OPO
OP
+
-
PWMC[DATA]
PRT150
SEG8
PRT151
SEG9
PRT152
SEG10
PRT153
SEG11
PRT154
SEG12
Note:
PRT155
SEG13
PRT156 1. UseSEG14
ICE5.x
PRT157 2. Type
SEG15
1 Passive bias network
LIO14=0
3
VDD
1
LV3=VDD
DAC
LCDE
OPIP
LVG
OPIN
1
DAO
0
VO
R
VOC[DAC]
VR
LVG can be connected to
GND directly or through
a resistor VR to GND
VSS
VOC[OP]
20
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
Triple Charge Pump is selected
LCD Max. Voltage=LV3=3*VDD
VDD
億
電
股
份
Triple Charge Pump is selected
LCD Max. Voltage=LV3=3/2*VDD
VDD
LV1
C8 0.1uF LV2
C9 0.1uF LV3
LC1
C6
0.1uF
子
C1
HE80000 SERIES
Triple Charge Pump is selected
LCD Max. Voltage=LV3=VDD
LV3
Floating
LV2
C9 0.1uF LV3
Floating
LV1
LC1
LC1
No Capacitor
LC2
No External Parts is
necessary if user adopt
Internal Fast RC Clock
LC2
External Fast Clock:
Crystal osc.
FXI
R1
50K
C2
0.1uF 100uF
FXO
SXI
RSTP_N
C3
SW1
0.1uF
RESET
LC1
LC2
LV1
LV2
LV3
CONFIGURATION
32 COM:1/7 BIAS
48 COM:1/8 BIAS
SXO
LC1
PRTC[7:4]/SCNI[3:0]
LC2
SGKY[43:24]/SCNO[19:0]
COM[31:0]
CMSG[47:32]
LV1
LV2
C1
0.1uF
LV3 < 7 Volt
C2
0.1uF
LR4
C3
0.1uF
LR3
C4
0.1uF
LR2
C5
0.1uF
LR1
OPIN
OPIP
OPO
PWM
TSTP_P
GND_PWM
VO
LVG
VR1
FXI
20P
FXO
SXI
FXO
SXO
2MHZ
20P
External Fast Clock:
RC osc.
KEY SCAN
VDD
LCD PANEL
R > 8.2 KOhm
FXI
PRT14[7:0]/SEG[23:16]
PRT15[7:0]/SEG[15:8]
PRT17[7:0]/SEG[7:0]
LR0
?K Ohm
FXI
PRTD[7:0]
GND
HE85750
2003/7/30
HE85750
司
C7 0.1uF LV1
VDD
3V
公
VDD
VDD
BATTERY1
限
LV2
C6
0.1uF
LC2
有
21
C: Please Ref. AN016
External Slow Clock:
Crystal osc.
VDD
Buzzer
or
Speaker
Circuit
SXI
VDD
Passive
Bias &
Q1
NPN
Filter
Circuit
Please Refer
AN022 for Speech
Output Circuit
SP1
SXO
20P
32.768K
20P
SPEAKER
External Slow Clock:
RC osc.
SXI
R: Please ref. AN016
SXO
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
Twice Charge Pump is selected
LCD Max. Voltage=LV3=2*VDD
C6
0.1uF
VDD
電
子
股
份
VDD
LC1
LC2
LV1
LV2
Floating
LV1
LV2
LC1
C9 0.1uF LV3
No Capacitor
LC2
C1
HE85750
司
HE80000 SERIES
No External Parts is
necessary if user adopt
Internal Fast RC Clock
External Fast Clock:
Crystal osc.
FXI
R1
50K
C2
0.1uF 100uF
FXO
SXI
RSTP_N
C3
SW1
0.1uF
RESET
LC1
LC2
LV1
LV2
LV3
CONFIGURATION
32 COM:1/7 BIAS
48 COM:1/8 BIAS
SXO
LC1
PRTC[7:4]/SCNI[3:0]
LC2
SGKY[43:24]/SCNO[19:0]
COM[31:0]
LV1
CMSG[47:32]
LV2
C1
0.1uF
LV3 < 7 Volt
C2
0.1uF
LR4
C3
0.1uF
LR3
C4
0.1uF
LR2
C5
0.1uF
LR1
OPIN
OPIP
OPO
PWM
TSTP_P
GND_PWM
VO
LVG
VR1
FXI
20P
FXO
SXI
FXO
2MHZ
20P
SXO
External Fast Clock:
RC osc.
KEY SCAN
VDD
LCD PANEL
R > 8.2 KOhm
FXI
PRT14[7:0]/SEG[23:16]
PRT15[7:0]/SEG[15:8]
PRT17[7:0]/SEG[7:0]
LR0
?K Ohm
FXI
PRTD[7:0]
GND
C: Please Ref. AN016
External Slow Clock:
Crystal osc.
VDD
Buzzer
or
Speaker
Circuit
SXI
VDD
Passive
Bias &
Q1
NPN
Filter
Circuit
Please Refer
AN022 for Speech
Output Circuit
SP1
SXO
20P
32.768K
20P
SPEAKER
External Slow Clock:
RC osc.
SXI
R: Please ref. AN016
HE85750
2003/7/30
公
LV3
Floating
VDD
3V
限
Twice Charge Pump is selected
LCD Max. Voltage=LV3=VDD
VDD
BATTERY1
有
22
SXO
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
HE85750
HE80000 SERIES
20. Important Note
1. For accessing any address large than 64KB, users must update TPP first, TPH then TPL. Only by this
order, the pre-charge circuit of ROM will work correctly. 5us waiting is necessary before LDV
instruction is executed since Data ROM is a low speed ROM. Users can not emulate this accessing
process in ICE. So 5us delay should be added by firmware.
2. LCD driving circuit must be turn off before IC goes into sleep mode.
3. Please bonds the TSTP_P, RSTP_N and PRTD[7:0] with test point on PCB to do some testing when
it’s necessary and TSTP_P shall tie to low for normal operation.
Add zero Ohm resistor
to TSTP_P.
4. LV3 must small than 8.5 Volt. Otherwise IC may breakdown.
5. The LCDC of 85750 is different from other IC of HE80000 series. Please Use ICE5.0/5.1 to emulate
the LCDC configuration. The LCDC:[G5G4G3G2 G1G0BE]; G[5:0]: gray level control, 64 levels
for this body. B: blank control bit. E: LCD enable bit.
21. Updated Record
Version
V1.52
2003/7/30
Date
July 30,
2003
Section
Original Content
23
New Content
Modify the datasheet format and
review all the contents, add some
sections.
V1.52E
This specification is subject to change without notice. Please contact sales person for the latest version before use.