HEF4104B Quad low-to-high voltage translator with 3-state outputs Rev. 07 — 16 December 2009 Product data sheet 1. General description The HEF4104B is a quad low voltage-to-high voltage translator with 3-state outputs. It provides the capability of interfacing low voltage circuits to high voltage circuits. For example low voltage Local Oxidation Complementary MOS (LOCMOS) and Transistor Transistor Logic (TTL) to high voltage LOCMOS. It has four data inputs (A0 to A3), an active HIGH output enable input (OE), four data outputs (B0 to B3) and their complements (B0 to B3). With OE = HIGH, the outputs B0 to B3 and B0 to B3 are in the low impedance ON-state, either HIGH or LOW as determined by the inputs A0 to A3. With OE = LOW, the outputs B0 to B3 and B0 to B3 are in the high-impedance OFF-state. It uses a common negative supply (VSS) and separate positive supplies for the inputs (VDD(A)) and the outputs (VDD(B)). VDD(A) must always be less than or equal to VDD(B), even during power turn-on and turn-off. For the permissible operating range of VDD(A) and VDD(B) see Figure 4. Each input protection circuit is terminated between VDD(B) and VSS. This allows the input signals to be driven from any potential between VDD(B) and VSS, without regard to current limiting. When driving from potentials greater than VDD(B) or less than VSS, the current at each input must be limited to 10 mA. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Inputs and outputs are protected against electrostatic effects Operates across the full industrial temperature range from −40 °C to +85 °C Complies with JEDEC standard JESD 13-B 3. Applications Industrial HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +85 °C. Type number Package Name Description Version HEF4104BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4104BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 5. Functional diagram VDD(A) VDD(B) 16 1 3 A0 4 2 A1 6 5 B0 B0 LEVEL CONVERTER A0 B1 B0 B0 7 B1 LEVEL CONVERTER A1 A2 11 LEVEL CONVERTER 10 9 A3 B2 B1 LEVEL CONVERTER A2 B2 B2 B3 LEVEL CONVERTER A3 14 15 B3 LEVEL CONVERTER 8 VSS Logic symbol VDD(A) 001aag262 Fig 2. VDD(B) 001aag264 Logic diagram HEF4104B_7 Product data sheet B3 B3 OE Fig 1. B2 12 13 OE B1 © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 2 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 6. Pinning information 6.1 Pinning HEF4104B VDD(B) 1 16 VDD(A) B0 2 15 OE B0 3 14 B3 A0 4 13 B3 A1 5 12 A3 B1 6 11 A2 B1 7 10 B2 VSS 8 9 B2 001aag263 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VDD(B) 1 supply voltage port B B0 to B3 2, 7, 9, 14 complementary data output B0 to B3 3, 6, 10, 13 data output A0 to A3 4, 5, 11, 12 data input VSS 8 common negative supply voltage (0 V) OE 15 output enable input VDD(A) 16 supply voltage port A 7. Functional description Table 3. Function table[1] Control Output OE Bn Bn H An An L Z Z [1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 3 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter Conditions Min VDD(A) supply voltage A port A; VDD(A) ≤ VDD(B) −0.5 +18 V VDD(B) supply voltage B port B; VDD(B) ≥ VDD(A) −0.5 +18 V IIK input clamping current VI < −0.5 V or VI > VDD(A) + 0.5 V - ±10 mA VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature Ptot total power dissipation P power dissipation Max −0.5 VO < −0.5 V or VO > VDD(B) + 0.5 V [1] Unit VDD(A) + 0.5 V - ±10 mA - ±10 mA - 50 mA −65 +150 °C −40 +85 °C Tamb = −40 °C to +85 °C DIP16 [2] - 750 mW SO16 [3] - 500 mW - 100 mW per output [1] IDD is the combined current of IDD(A) and IDD(B). [2] For DIP16 packages: above Tamb = 70 °C, Ptot derates linearly at 12 mW/K. [3] For SO16 packages: above Tamb = 70 °C, Ptot derates linearly at 8 mW/K. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VDD(A) supply voltage A Conditions 3 - ≤ VDD(B) V VDD(B) supply voltage B ≥ VDD(A) - 15 V VI input voltage 0 - VDD(A) V Tamb ambient temperature in free air −40 - +85 °C Δt/ΔV input transition rise and fall rate VDD(A) = 5 V - - 3.75 μs/V VDD(A) = 10 V - - 0.5 μs/V VDD(A) = 15 V - - 0.08 μs/V HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 4 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 10. Static characteristics Table 6. Static characteristics VDD(A) = VDD(B); VSS = 0 V; VI = VSS or VDD(A); unless otherwise specified. Symbol Parameter HIGH-level input voltage VIH LOW-level input voltage VIL VOH VOL IOH HIGH-level output voltage Min Max Min Max - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V |IO| < 1 μA 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V |IO| < 1 μA 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V V 15 V - 0.05 - 0.05 - 0.05 HIGH-level output current VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - mA VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA - ±0.3 - ±0.3 - ±1.0 μA - 20 - 20 - 150 μA 10 V - 40 - 40 - 300 μA 15 V - 80 - 80 - 600 μA HIGH level; VO = VDD(B) 15 V - 1.6 - 1.6 - 12.0 μA LOW level; VO = VSS 15 V - −1.6 - −1.6 - −12.0 μA digital inputs - - - - 7.5 - input leakage current IDD supply current OFF-state output current input capacitance CI Max 3.5 |IO| < 1 μA II IOZ Min 5V |IO| < 1 μA LOW-level output voltage LOW-level output current IOL Tamb = −40 °C Tamb = +25 °C Tamb = +85 °C Unit VDD[1] Conditions 15 V all valid input combinations; IO = 0 A [1] VDD is the same as VDD(A) and VDD(B). [2] IDD is the combined current of IDD(A) and IDD(B). 5V [2] HEF4104B_7 Product data sheet - pF © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 5 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 001aag265 15 VDD(B) (V) operating area 10 5 0 0 5 10 15 VDD(A) (V) The shaded area shows the permissible operating range. Fig 4. VDD(B) as a function of VDD(A) 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL tPLH tTHL tTLH tPHZ HIGH to LOW propagation delay LOW to HIGH propagation delay Conditions Min Typ Max Unit An to Bn, Bn; see Figure 5 VDD(A) = VDD(B) = 5 V 143 ns + (0.55 ns/pF)CL - 170 340 ns VDD(A) = VDD(B) = 10 V 69 ns + (0.23 ns/pF)CL - 80 160 ns VDD(A) = VDD(B) = 15 V 57 ns + (0.16 ns/pF)CL - 65 135 ns An to Bn, Bn; see Figure 5 VDD(A) = VDD(B) = 5 V 143 ns + (0.55 ns/pF)CL - 170 340 ns VDD(A) = VDD(B) = 10 V 69 ns + (0.23 ns/pF)CL - 80 160 ns VDD(A) = VDD(B) = 15 V 62 ns + (0.16 ns/pF)CL - 70 140 ns HIGH to LOW output Bn or Bn; see Figure 6 transition time VDD(A) = VDD(B) = 5 V 10 ns + (1.00 ns/pF)CL - 60 120 ns VDD(A) = VDD(B) = 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns VDD(A) = VDD(B) = 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns LOW to HIGH output Bn or Bn; see Figure 6 transition time VDD(A) = VDD(B) = 5 V HIGH to OFF-state propagation delay Extrapolation formula[1] 10 ns + (1.00 ns/pF)CL - 60 120 ns VDD(A) = VDD(B) = 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns VDD(A) = VDD(B) = 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns OE to Bn, Bn; see Figure 6 VDD(A) = VDD(B) = 5 V - 70 135 ns VDD(A) = VDD(B) = 10 V - 55 110 ns VDD(A) = VDD(B) = 15 V - 60 120 ns HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 6 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs Table 7. Dynamic characteristics …continued Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Extrapolation formula[1] Symbol Parameter Conditions tPLZ OE to Bn, Bn; see Figure 6 LOW to OFF-state propagation delay OFF-state to HIGH propagation delay tPZH OFF-state to LOW propagation delay tPZL [1] Min Typ Max Unit VDD(A) = VDD(B) = 5 V - 70 135 ns VDD(A) = VDD(B) = 10 V - 55 105 ns VDD(A) = VDD(B) = 15 V - 55 110 ns VDD(A) = VDD(B) = 5 V - 195 395 ns VDD(A) = VDD(B) = 10 V - 95 195 ns VDD(A) = VDD(B) = 15 V - 80 165 ns VDD(A) = VDD(B) = 5 V - 195 395 ns VDD(A) = VDD(B) = 10 V - 95 190 ns VDD(A) = VDD(B) = 15 V - 80 160 ns OE to Bn, Bn; see Figure 6 OE to Bn, Bn; see Figure 6 Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VDD(A) = VDD(B); VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol Parameter dynamic power dissipation PD VDD[1] Typical formula (μW) 5V PD = 3000 × fi + Σ(fo × CL) × VDD where 2 fi = input frequency in MHz; 10 V PD = 12200 × fi + Σ(fo × CL) × VDD2 fo = output frequency in MHz; 15 V PD = 31000 × fi + Σ(fo × CL) × VDD2 CL = output load capacitance in pF; Σ(fo × CL) = sum of the outputs; VDD = supply voltage in V. [1] VDD is the same as VDD(A) and VDD(B). HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 7 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 12. Waveforms VI An input VM 0V tPHL VOH tPLH VY VM Bn output VX VOL tTHL tTLH tPLH VOH tPHL VY Bn output VX VOL tTLH tTHL 001aaj783 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 5. Data input (An) to data output (Bn, Bn) propagation delays and output transition times VI OE input VM VSS tPLZ output LOW-to-OFF OFF-to-LOW tPZL VOH VY VX VOL tPHZ VOH tPZH VY output HIGH-to-OFF OFF-to-HIGH VX VOL outputs on outputs off outputs on 001aaj782 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 6. Table 9. Enable and disable times Measurement points Input Output VI VM VM VX VY VSS or VDD(A) 0.5VDD(A) 0.5VDD(B) 0.1VDD(B) 0.9VDD(B) HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 8 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VEXT VDD VI RL VO G DUT RT CL 001aaj915 b. Test circuit Test data given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RL = load resistance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit for measuring switching times Table 10. Test data Supplies Input Load VDD(A) = VDD(B) tr, tf RL CL VEXT tPHL, tPLH tPZL, tPLZ tPZH, tPHZ 5 V to 15 V ≤ 20 ns 1 kΩ 50 pF open VDD(B) VSS HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 9 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 8. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 10 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 11 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4104B_7 20091216 Product data sheet - HEF4104B_6 Modifications: • Section 12 “Waveforms” Figure 7 “Test circuit for measuring switching times” updated. HEF4104B_6 20091102 Product data sheet - HEF4104B_5 HEF4104B_5 20090728 Product data sheet - HEF4104B_4 HEF4104B_4 20090305 Product data sheet - HEF4104B_CNV_3 HEF4104B_CNV_3 19950101 Product specification - HEF4104B_CNV_2 HEF4104B_CNV_2 19950101 Product specification - - HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 12 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 15.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4104B_7 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 07 — 16 December 2009 13 of 14 HEF4104B NXP Semiconductors Quad low-to-high voltage translator with 3-state outputs 17. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 December 2009 Document identifier: HEF4104B_7