HI-8597 3.3V Single-Rail ARINC 429 Differential Line Driver with Integrated DO-160G Level 3 Lightning Protection July 2013 GENERAL DESCRIPTION FEATURES The HI-8597 is a 3.3V single supply ARINC 429 line driver with built-in lightning protection. The internal lightning protection circuitry allows compliance with RTCA/DO160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B) without the use of any external components, an industry first. Pin surge levels for Level 3 are summarized as follows: Waveform 3 Waveform 4 Waveform 5A Waveform 5B Voc/Isc Voc/Isc Voc/Isc Voc/Isc 600V/24A 300V/60A 300V/300A 300V/300A An internal 37.5 Ohm resistor on each output enables direct connection to the ARINC 429 bus. In addition, the device includes a dual polarity voltage doubler, allowing it to operate from a single +3.3V supply using only four external capacitors. • Internal lightning protection circuitry allows compliance with RTCA/DO-160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B). • Operates from a single +3.3V supply • Superb short circuit capability on ARINC 429 outputs (±50V for 1 second) • All ARINC 429 voltage levels generated on-chip • Digitally selectable rise and fall times • Tri-state Outputs • 37.5 Ohm output resistance allows direct connection to ARINC 429 bus • Industrial and Extended temperature ranges • Burn-in available PIN CONFIGURATION (TOP VIEW) Other features include high-impedance outputs (tristate) when both data inputs are taken high, allowing multiple line drivers to be connected to a common bus. NC 1 Bus pins feature built-in 8kV ESD input protection (HBM), with 6kV capability on all other pins. All logic inputs are 5V or 3.3V compatible. o DS8597 Rev. F. 15 CN+ TXAOUT 3 14 CN- HI-8597PSIF HI-8597PSTF TXBOUT 4 GNDB 5 SLP 6 The HI-8597 line driver is intended for use where logic signals must be converted to ARINC 429 levels such as when using an FPGA or the HI-3586 ARINC 429 protocol IC. The single supply operation and internal lightning protection circuitry enable huge board space saving, making HI-8597 the most compact, cost effective ARINC 429 line driver on the market today. 13 GND 12 VDD 11 CP- TX0IN 7 10 CP+ TX1IN 8 9 VDD2+ 16-Pin Plastic ESOIC package (Wide Body) Table 1. Function Table o The part is available in Industrial -40 C to +85 C, or o o Extended, -55 C to +125 C temperature ranges. Optional burn-in is available on the extended temperature range. 16 VDD2- GNDA 2 TX1IN TX0IN SLP TXAOUT TXBOUT SLOPE 0 0 X 0V 0V N/A 0 1 0 -5V 5V 10μs 0 1 1 -5V 5V 1.5μs 1 0 0 5V -5V 10μs 1 0 1 5V -5V 1.5μs 1 1 X Hi-Z Hi-Z N/A HOLT INTEGRATED CIRCUITS www.holtic.com 1 07/13 HI-8597 BLOCK DIAGRAM VDD CSUPPLY 3.3V SLP TX0IN VDD2+ 5V ONE ESD PROTECTION & VOLTAGE TRANSLATION CURRENT CONTROL NULL “A” SIDE Lightning Protection ZERO TX1IN CONTROL LOGIC VDD2+ -5V CURRENT CONTROL NULL “B” SIDE VDD TXBOUT -5V Lightning Protection CN+ CFLY GNDB VDD2+ VDD2+ CP+ CFLY CP- GNDA 37.5 OHMS ZERO CONTROL LOGIC TXAOUT 5V ONE GND 37.5 OHMS Dual Polarity Voltage Doubler COUT VDD2- VDD2- CN- COUT Figure 1. HI-8597 Block Diagram HOLT INTEGRATED CIRCUITS 2 HI-8597 PIN DESCRIPTIONS Table 2. Pin Descriptions Pin No. Pin Name Function Description 1 NC None No connect. 2 GNDA POWER Ground connection of internal lightning protection circuitry for ARINC high output. MUST be tied to chip ground pin, GND. 3 TXAOUT OUTPUT ARINC high output with 37.5 Ohms series resistance 4 TXBOUT OUTPUT ARINC low output with 37.5 Ohms series resistance 5 GNDB POWER Ground connection of internal lightning protection circuitry for ARINC low output. MUST be tied to chip ground pin, GND. 6 SLP INPUT Output slew rate control. High selects ARINC 429 high-speed. Low selects ARINC 429 low-speed. 7 TX0IN INPUT Data input zero 8 TX1IN INPUT Data input one 9 VDD2+ OUTPUT Voltage doubler positive output (~6.25V for 3.3V supply) 10 CP+ ANALOG VDD2+ flyback capacitor, CFLY; positive terminal 11 CP- ANALOG VDD2+ flyback capacitor, CFLY; negative terminal 12 VDD POWER +3.3V power supply 13 GND POWER Ground supply 14 CN- ANALOG VDD2- flyback capacitor, CFLY; negative terminal 15 CN+ ANALOG VDD2- flyback capacitor, CFLY; positive terminal 16 VDD2- OUTPUT Voltage doubler negative output (~ -6.1V for 3.3V supply) HOLT INTEGRATED CIRCUITS 3 HI-8597 FUNCTIONAL DESCRIPTION Figure 1 shows a block diagram of the line driver. The HI-8597 is internally lightning protected in compliance with RTCA/DO-160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B). The waveforms are shown in Figure 5 through Figure 7. The device requires only a single +3.3V power supply. An integrated inverting / non-inverting voltage doubler generates the rail voltages (±6.6V) which are then used to produce the ±5V ARINC-429 output levels. The internal dual polarity charge pump circuit requires four external capacitors, two for each polarity generated by the doubler. CP+ and CP- connect the external charge transfer or “fly” capacitor, CFLY, to the positive portion of the doubler, resulting in twice VDD at the VDD2+ pin. An output “hold” capacitor, COUT, is placed between VDD2+ and GND. COUT should be ten times the size of CFLY. The inverting or negative portion of the converter works in a similar fashion, with CFLY and COUT placed between CN+ / CN- and VDD2- / GND respectively. Currents for slope control are set by on-chip resistors. at Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to 5V on an “A” side internal capacitor while the “B” side is enabled to -5V. The charging current is selected by the SLP pin. If the SLP pin is high, the capacitor is nominally charged from 10% to 90% in 1.5μs. If SLP is low, the rise and fall times are 10μs. A unity gain buffer receives the internally generated slopes and differentially drives the ARINC line. Current is limited by the series output resistors at each pin. There are no fuses at the outputs of the HI-8597. The HI-8597 has 37.5 ohms in series with each TXOUT output, allowing direct connection to the ARINC 429 bus. The outputs are automatically lightning protected in compliance with RTCA/DO-160G, Section 22 Level 3 Pin Injection Test Waveform Set A (3 & 4), Set B (3 & 5A) and Set Z (3 & 5B) without any external components. Tri-stateable outputs allow multiple line drivers to be connected to the same ARINC 429 bus. Setting TX1IN and TX0IN both to a logic “1” puts the outputs in the high-impedance state. The TX0IN and TX1IN inputs receive logic signals from a control transmitter chip such as the HI-3584 or HI-3586. TXAOUT and TXBOUT hold each side of the ARINC bus ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS Supply Voltages VDD .......................................................... +5V o Power Dissipation at 25 C o plastic SOIC ........... 1.0W, derate 10mW/ C o Supply Voltages VDD ................................... +3.0V to +3.6V Temperature Range o o Solder Temperature (reflow) .............................. 260 C Industrial Screening .............. -40 C to +85 C Storage Temperature ....................... -65 C to +150 C Hi-Temp Screening .............. -55 C to +125 C o o RTCA/DO-160G, Section 22 pin injection Waveform Voc/Isc 3 800V/32A 4 375V/75A 5A 375V/375A 5B 375V/375A o o NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. HOLT INTEGRATED CIRCUITS 4 HI-8597 ELECTRICAL CHARACTERISTICS Table 3. DC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Test Conditions Min Typ Max Units Input Voltage (TX1IN, TX0IN, SLP) High VIH 0.7VDD - - V Low VIL - - 0.3VDD V 0.1 μA Input Current (TX1IN, TX0IN, SLP) Source IIH VIN = 0V - - Sink IIL VIN = 3.3V, 7.34kΩ pulldown - 45 one VDIFF1 no load; TXAOUT - TXBOUT 9 10 11 V zero VDIFF0 no load; TXAOUT - TXBOUT -11 -10 -9 V null VDIFFN no load; TXAOUT - TXBOUT -0.5 0 0.5 V one or zero VDOUT no load & magnitude at pin 4.5 5.0 5.5 V null VNOUT no load -0.25 0 0.25 V μA ARINC Output Voltage (Differential) ARINC Output Voltage (Ref. to GND) Operating Supply Current SLP = VDD No load IDDNL TX1IN & TX0IN = 0V - 65 100 mA Max. Load IDDL 100kHz, 400Ω load - 130 - mA ARINC Outputs Shorted IDDS See Note 1 - 330 - mA ARINC Output Impedance ZOUT TXOUT pins 37.5 Ohms TX0IN = TX1IN = VDD, ARINC Output Tri-State Current IOZ TA = 25oC -200 200 μA +5.5 V -5.5V < VOUT < +5.5V TX0IN = TX1IN = VDD, ARINC Output Tri-State Voltage VOZ TA = 25oC -150μA < IOUT < +150μA Note 1: TXAOUT and/or TXBOUT shorted to each other or ground. HOLT INTEGRATED CIRCUITS 5 -5.5 - HI-8597 Table 4. Converter Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Start-up transient (V+, V-) Operating Switching Frequency Worst case maximum voltage doubler output Min Typ Max Units tSTART - - 10 ms fsw - 650 - kHz 6.93 V VDD2+(max) Test Conditions VDD = 3.6V. T = -55oC. Open load. DC/DC convertor capacitor recommendations. For optimum performance use typical (not min.) values. For EMC compliance, see AN-135. CFLY and COUT caps are Ceramic or Tantalum, preferably multilayer, non polarized dielectric XR7, 10V min. CSUPPLY cap is Tantalum 10V min. Ratio of bulk storage to fly-back capacitors COUT / CFLY Fly-back capacitor (Recommend ceramic, preferably multilayer, dielectric XR7 caps, 10V min.). Bulk storage capacitor (Recommend ceramic, preferably multilayer, dielectric XR7 caps, 10V min.). By-pass capacitor (Recommend tantalum cap, 10V min.). 2.2 10 4.7 CFLY COUT / CFLY >= 10 1.0 - CFLY(ESR) [0.5, 1.0]Mhz 500 COUT COUT / CFLY >= 10 2.2 COUT(ESR) [0.5, 1.0]Mhz 300 CSUPPLY CSUPPLY >= COUT (connect from VDD to GND) μF mΩ 47 - μF mΩ Table 5. AC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Test Conditions Min Typ Max Units Output high to low tphlx defined in Figure 2, no load - 500 - ns Output low to high tplhx - 500 - ns Line Driver Propogation Delay Line Driver Transition Times High Speed SLP pin = Logic “1” Output high to low tfx 1.0 1.5 2.0 μs Output low to high trx 1.0 1.5 2.0 μs Low Speed SLP pin = Logic “0” Output high to low tfx 5.0 10.0 15.0 μs Output low to high trx 5.0 10.0 15.0 μs CIN - - 10 pF - - 10 pF Input Capacitance (Logic)1 Output Capacitance (Tri-state)1 COUT TX0IN = TX1IN = VDD Notes: 1. Guaranteed but not tested HOLT INTEGRATED CIRCUITS 6 HI-8597 5V TX1IN 0V tphlx tplhx tplhx 5V TX0IN 0V tphlx trx trx VDIFF (TXAOUT - TXBOUT) 10% 10V 90% 0V 10% 90% -10V 10% tfx tfx Figure 2. Line Driver Timing 2000 -55C 1500 -40C 25C +85C Leakage Current (uA) 1000 +125C 500 0 -500 -1000 -1500 -2000 -5.50 -4.50 -3.50 -2.50 -1.50 -0.50 0.50 1.50 2.50 3.50 4.50 5.50 Bus Voltage (V) Figure 3. Tri-State Leakage Current vs Bus Voltage at Temperature. HOLT INTEGRATED CIRCUITS 7 HI-8597 125 100 25C 75 Leakage Current (uA) 50 25 0 -25 -50 -75 -100 -125 -5.50 -4.50 -3.50 -2.50 -1.50 -0.50 0.50 1.50 2.50 3.50 4.50 5.50 Bus Voltage (V) Figure 4. Tri-State Leakage Current vs Bus Voltage at Room Temperature. HOLT INTEGRATED CIRCUITS 8 HI-8597 LIGHTNING INDUCED TRANSIENT VOLTAGE WAVEFORMS Waveform 3. V or I Largest Peak 25% to 75% of Largest Peak 50% 0 t Figure 5. DO-160G Lightning Induced Transient Voltage Waveform 3. Voc = 600V, Isc = 24A, Frequency = 1MHz ± 20%. Waveform 4. V or I Peak T1 = 6.4µs ± 20% T2 = 70µs ± 20% 50% 0 T1 T2 t Figure 6. DO-160G Lightning Induced Transient Voltage Waveform 4. Voc = 300V, Isc = 60A. HOLT INTEGRATED CIRCUITS 9 HI-8597 Waveform 5. V or I Peak 5A: T1 = 40µs ± 20% T2 = 120µs ± 20% 5B: T1 = 50µs ± 20% T2 = 500µs ± 20% 50% 0 T1 t T2 Figure 7. DO-160G Lightning Induced Transient Voltage Waveforms 5A and 5B. Voc = 300V, Isc = 300A. ORDERING INFORMATION HI - 8597Px x x (Plastic) PART NUMBER F PART NUMBER LEAD FINISH 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE o o FLOW BURN IN I -40 C to +85 C I No T -55oC to +125oC T No M Yes M PART NUMBER 8597PS o o -55 C to +125 C PACKAGE DESCRIPTION LEAD FINISH 16 PIN PLASTIC SMALL OUTLINE - WB SOIC (16HWE) Solder HOLT INTEGRATED CIRCUITS 10 HI-8597 REVISION HISTORY Revision DS8597, Date Description of Change Rev. New 11/9/12 Initial Release Rev. A 12/11/12 Clarify operating supply current for shorted ARINC outputs. Change “VSS” pin label to “GND” and “-” to “NC” for clarification. Add pin numbers to Pin Description table. Rev. B 01/21/13 Rephrase “guarantees” compliance with DO-160G Level 3 to “allows” compliance with DO-160G Level 3. Update tri-state leakage parameter to 200μA. Add Absolute Maximum Ratings for lightning waveforms. Rev. C 03/14/13 Remove erroneous references to AMPA and AMPB outputs in footnote on page 5. Rev. D 05/08/13 Corrected state of SLP pin and erroneous reference to pin 1 in Test Conditions for Line Driver Transition Times (see AC Characteristics Table). Rev. E 06/13/13 Update operating supply current. Rev. F 07/19/13 Update operating supply current from 85mA to 100mA max. HOLT INTEGRATED CIRCUITS 11 HI-8597 PACKAGE DIMENSIONS inches (millimeters) 16-PIN PLASTIC SMALL OUTLINE (SOIC) - WB (Wide Body, Thermally Enhanced) .008 ± .005 (.215 ± .115) .406 BSC (10.3) .406 BSC (10.3) .295 BSC (7.5) Top View Package Type: 16HWE .245 ± .015 (6.225 ± .385) .195 ± .015 (4.955 ± .385) Bottom View See Detail A .050 BSC (1.27) .081 min. (2.05) .0161 ± .004 (.41 ± .10) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 0° to 8° Electrically isolated heat sink pad on bottom of package. .008 ± .004 (.20 ± .10) .033 ± .017 (.835 ± .435) Detail A HOLT INTEGRATED CIRCUITS 12