HI-8596 July 2011 Single-Rail ARINC 429 Differential Line Driver GENERAL DESCRIPTION PIN CONFIGURATION (TOP VIEW) The HI-8596 bus interface product is a silicon gate CMOS device designed as a line driver in accordance with the ARINC 429 bus specifications. The part includes a dual polarity voltage doubler, allowing it to operate from a single +3.3V supply using only four external capacitors. The part also features high-impedance outputs (tri-state) when both data inputs are taken high, allowing multiple line drivers to be connected to a common bus. AMPB 1 TXBOUT 2 o o FEATURES 14 - HI-8596PSI HI-8596PST TX1IN 4 CP- 5 CP+ 6 13 SLP 12 CN+ 11 CN- VDD2P 7 10 VDD2N VDD 8 9 GND 16-Pin Plastic SOIC package (Narrow Body) 37.5 Ohm or 5 Ohm resistors in series with each ARINC output are available to allow the use of external resistors for lightning protection. The part is available in Industrial -40 C to +85 C, or o o Extended, -55 C to +125 C temperature ranges. Optional burn-in is available on the extended temperature range. 15 TXAOUT TX0IN 3 Logic inputs feature built-in 4kV ESD input protection (HBM) as well as 5V or 3.3V logic level compatibility. The HI-8596 line driver is intended for use where logic signals must be converted to ARINC 429 levels such as when using an FPGA or the HI-3586 ARINC 429 protocol IC. 16 AMPA (See page 9 for additional package pin configurations) Table 1. Function Table TX1IN TX0IN SLP TXAOUT TXBOUT SLOPE 0 0 X 0V 0V N/A 0 1 0 -5V 5V 10μs 0 1 1 -5V 5V 1.5μs 1 0 0 5V -5V 10μs 1 0 1 5V -5V 1.5μs 1 1 X Hi-Z Hi-Z N/A • Single +3.3V supply • All ARINC 429 voltage levels generated on-chip • Digitally selectable rise and fall times • Tri-state Outputs • 5 Ohm or 37.5 Ohm output resistance • Industrial and Extended temperature ranges • Burn-in available DS8596 Rev. B. HOLT INTEGRATED CIRCUITS www.holtic.com 1 07/11 HI-8596 BLOCK DIAGRAM VDD CSUPPLY 3.3V 5 OHMS SLP TX0IN VDD2+ 5V ONE ESD PROTECTION & VOLTAGE TRANSLATION CURRENT CONTROL NULL “A” SIDE CONTROL LOGIC VDD2- 37.5 OHMS -5V 5 OHMS 5V ONE CURRENT CONTROL NULL GND “B” SIDE VDD AMPB TXBOUT 37.5 OHMS ZERO CONTROL LOGIC -5V VDD2+ VDD2+ CP+ CFLY CN+ CFLY TXAOUT ZERO TX1IN CP- AMPA Dual Polarity Voltage Doubler COUT VDD2- VDD2- CN- COUT Figure 1. HI-8596 Block Diagram HOLT INTEGRATED CIRCUITS 2 HI-8596 PIN DESCRIPTIONS Table 2. Pin Descriptions Pin Function Description SLP INPUT Output slew rate control. High selects ARINC 429 high-speed. Low selects ARINC 429 low-speed. TX0IN INPUT Data input zero TX1IN INPUT Data input one VDD POWER +3.3V power supply GND POWER Ground supply VDD2+ OUTPUT Voltage doubler positive output (~6.6V for 3.3V supply) CP+ ANALOG VDD2+ flyback capacitor, CFLY; positive terminal CP- ANALOG VDD2+ flyback capacitor, CFLY; negative terminal VDD2- OUTPUT Voltage doubler negative output (~ -6.6V for 3.3V supply) CN+ ANALOG VDD2- flyback capacitor, CFLY; positive terminal CN- ANALOG VDD2- flyback capacitor, CFLY; negative terminal TXAOUT OUTPUT ARINC high output with 37.5 Ohms series resistance AMPA OUTPUT ARINC high output with 5 Ohms series resistance TXBOUT OUTPUT ARINC low output with 37.5 Ohms series resistance AMPB OUTPUT ARINC low output with 5 Ohms series resistance HOLT INTEGRATED CIRCUITS 3 HI-8596 FUNCTIONAL DESCRIPTION Figure 1 is a block diagram of the line driver. The HI-8596 requires only a single +3.3V power supply. An integrated inverting / non-inverting voltage doubler generates the rail voltages (±6.6V) which are then used to produce the ±5V ARINC-429 output levels. The internal dual polarity charge pump circuit requires four external capacitors, two for each polarity generated by the doubler. CP+ and CP- connect the external charge transfer or “fly” capacitor, CFLY, to the positive portion of the doubler, resulting in twice VDD at the VDD2+ pin. An output “hold” capacitor, COUT, is placed between VDD2+ and GND. COUT should be ten times the size of CFLY. The inverting or negative portion of the converter works in a similar fashion, with CFLY and COUT placed between CN+ / CN- and VDD2- / GND respectively. Currents for slope control are set by on-chip resistors. The TX0IN and TX1IN inputs receive logic signals from a control transmitter chip such as the HI-3584. TXAOUT and TXBOUT hold each side of the ARINC bus at Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to ABSOLUTE MAXIMUM RATINGS A unity gain buffer receives the internally generated slopes and differentially drives the ARINC line. Current is limited by the series output resistors at each pin. There are no fuses at the outputs of the HI-8596. The HI-8596 has 37.5 ohms in series with each TXOUT output and 5 ohms in series with each AMP output. The AMP outputs are for applications where external series resistance is required, typically for lightning protection devices. Holt Application Note AN-300 describes suitable lightning protection schemes. Tri-stateable outputs allow multiple line drivers to be connected to the same ARINC 429 bus. Setting TX1IN and TX0IN both to a logic “1” puts the outputs in the high-impedance state. RECOMMENDED OPERATING CONDITIONS Supply Voltages VDD .......................................................... +5V o Power Dissipation at 25 C o plastic SOIC ........... 1.0W, derate 10mW/ C o ceramic DIP ......... 0.5W, derate 7mW/ C o Solder Temperature ......................... 275 C for 10sec o 5V on an “A” side internal capacitor while the “B” side is enabled to -5V. The charging current is selected by the SLP pin. If the SLP pin is high, the capacitor is nominally charged from 10% to 90% in 1.5μs. If SLP is low, the rise and fall times are 10μs. o Storage Temperature ....................... -65 C to +150 C Note: HEAT SINK on QFN PACKAGE Supply Voltages VDD ................................... +3.0V to +3.6V Temperature Range o o Industrial Screening .............. -40 C to +85 C o o Hi-Temp Screening .............. -55 C to +125 C NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. The HI-8596 driver is available in a small-footprint, thermally enhanced QFN (chip-scale) package. This package includes an electrically isolated metal heat sink located on the bottom surface of the device. This heat sink should be soldered down to the printed circuit board for optimum thermal dissipation. HOLT INTEGRATED CIRCUITS 4 HI-8596 ELECTRICAL CHARACTERISTICS Table 3. DC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Test Conditions Min Typ Max Units Input Voltage (TX1IN, TX0IN, SLP) High VIH 0.7VDD - - V Low VIL - - 0.3VDD V 0.1 μA Input Current (TX1IN, TX0IN, SLP) Source IIH VIN = 0V - - Sink IIL VIN = 3.3V, 7.34kΩ pulldown - 45 one VDIFF1 no load; TXAOUT - TXBOUT 9 10 11 V zero VDIFF0 no load; TXAOUT - TXBOUT -11 -10 -9 V null VDIFFN no load; TXAOUT - TXBOUT -0.5 0 0.5 V one or zero VDOUT no load & magnitude at pin 4.5 5.0 5.5 V null VNOUT no load -0.25 0 0.25 V μA ARINC Output Voltage (Differential) ARINC Output Voltage (Ref. to GND) Operating Supply Current SLP = VDD No load IDDNL TX1IN & TX0IN = 0V - 28 40 mA Max. Load IDDL 100kHz, 400Ω load - 65 - mA ARINC Output Impedance ZOUT TXOUT pins 37.5 Ohms AMP pins 5 Ohms ARINC Output Tri-State Current IOZ TX0IN = TX1IN = VDD -5.75V < VOUT < +5.75V HOLT INTEGRATED CIRCUITS 5 -1.0 0 +1.0 μA HI-8596 Table 4. Converter Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Start-up transient (V+, V-) Operating Switching Frequency Symbol Test Conditions Min Typ Max Units tSTART - - 10 ms fsw - 650 - kHz 2.2 4.7 - μF 22 47 - μF 47 68 - μF Min Typ Max Units CFLY Recommended Capacitors COUT / CFLY >= 10 COUT CSUPPLY CSUPPLY >= COUT (connect from VDD to GND) Table 5. AC Electrical Characteristics VDD = +3.3V, TA = Operating Temperature Range (unless otherwise stated) Parameters Symbol Line Driver Propogation Delay Test Conditions defined in Figure 2, no load Output high to low tphlx - 500 - ns Output low to high tplhx - 500 - ns Line Driver Transition Times High Speed SLP = V+ Output high to low tfx pin 1 = logic 1 1.0 1.5 2.0 μs Output low to high trx pin 1 = logic 1 1.0 1.5 2.0 μs Low Speed SLP = V+ Output high to low tfx pin 1 = logic 0 5.0 10.0 15.0 μs Output low to high trx pin 1 = logic 0 5.0 10.0 15.0 μs - - 10 pF - - 10 pF Input Capacitance (Logic)1 Output Capacitance (Tri-state)1 CIN COUT TX0IN = TX1IN = VDD Notes: 1. Guaranteed but not tested HOLT INTEGRATED CIRCUITS 6 HI-8596 5V TX1IN 0V tphlx tplhx tplhx 5V TX0IN 0V tphlx trx trx VDIFF (TXAOUT - TXBOUT) 10% 10V 90% 0V 10% 90% -10V 10% tfx Figure 2. Line Driver Timing HOLT INTEGRATED CIRCUITS 7 tfx HI-8596 ORDERING INFORMATION HI - 8596Px x x (Plastic) PART NUMBER Blank F PART NUMBER LEAD FINISH Tin / Lead (Sn / Pb) Solder 100% Matte Tin (Pb-free, RoHS compliant) TEMPERATURE RANGE o FLOW BURN IN o I -40 C to +85 C I No T -55oC to +125oC T No M Yes M o o -55 C to +125 C PACKAGE DESCRIPTION LEAD FINISH 8596PS 16 PIN PLASTIC SMALL OUTLINE - NB SOIC (16HN) Solder 8596PC 16 PIN PLASTIC QFN (16PCS) Solder PART NUMBER HI - 8596CD x (Ceramic) PART NUMBER TEMPERATURE RANGE FLOW BURN IN LEAD FINISH I -40oC to +85oC I No Gold (Pb-free, RoHS compliant) T -55oC to +125oC T No Gold (Pb-free, RoHS compliant) M Yes Tin / Lead (Sn / Pb) Solder M PART NUMBER 8596CD o o -55 C to +125 C PACKAGE DESCRIPTION 20 PIN CERAMIC SIDE BRAISED DIP (20C) HOLT INTEGRATED CIRCUITS 8 HI-8596 ADDITIONAL PIN CONFIGURATIONS NOTE: All power and ground pins must be connected. 14 - TX1IN 4 13 SLP CP- 5 12 CN+ CP+ 6 11 CN- TX0IN 1 TX1IN 2 CP- 3 CP+ 4 12 11 10 9 SLP CN+ CN- 10 VDD2N 5 6 7 8 VDD 8 16 15 14 13 15 TXAOUT TX0IN 3 VDD2P 7 TXBOUT AMPB AMPA TXAOUT 16 AMPA 9 GND HI-8596CD 16-PIN CERAMIC SIDE-BRAZED DIP HOLT INTEGRATED CIRCUITS 9 VDD2P VDD GND VDD2N AMPB 1 TXBOUT 2 HI-8596PC 16-LEAD 4mm x 4mm QFN HI-8596 REVISION HISTORY Revision DS8596, Date Description of Change Rev. NEW 11/10/10 Initial Release Rev. A 11/11/10 Clarified connection of heat sink and updated some electrical parameters (VIH, VIL, fsw). Added operating supply current at full load (IDDL). Rev. B 7/14/11 Updated supply voltage range. Corrected dimensions on QFN heat sink. Added voltage limits for Tri-state output current. HOLT INTEGRATED CIRCUITS 10 HI-8596 PACKAGE DIMENSIONS inches (millimeters) 16-PIN PLASTIC SMALL OUTLINE (SOIC) - NB Narrow Body) .0087 ± .0015 (.220 ± .029) .390 ± .004 (9.90 ± .10) .236 .008 (5.99 .20) Package Type: 16HN .1525 ± .0025 (3.87 ± .06) Top View See Detail A .0165 ± .003 (.419 ± .089) .061 ± .007 (1.549 ± .178) .050 BSC (1.27) 0 to 8 .0025 ± .002 (.064 ± .038) .033 ± .017 (.838 ± .432) Detail A millimeters 16-PIN PLASTIC CHIP-SCALE PACKAGE (QFN) 4.00 BSC 4.00 BSC Electrically isolated heat sink pad on bottom of package. Top View Package Type: 16PCS 2.80 ± .10 Bottom View 2.80 ± .10 0.65 BSC 0.30 ± .05 0.40 ± .05 1.00 max 0.20 typ HOLT INTEGRATED CIRCUITS 11 BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8596 16-PIN CERAMIC SIDE-BRAZED DIP inches (millimeters) Package Type: 16C .810 max (20.574) .295 ± .010 (7.493 ± .254) PIN 1 .200 max (5.080) .050 ± .005 (1.270 ± .127) .035 ± .010 (.889 ± .254) BASE PLANE .125 min (3.175) .018 ± .002 (.457 ± .051) .010 ± .002 (.254 ± .051) SEATING PLANE .100 BSC (2.54) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HOLT INTEGRATED CIRCUITS 12 .300 ± .010 (7.620 ± .254)