HI2304 Semiconductor NS EW August 1997 NOT RN D FO 8 E D EN I117 OMM See H C E R IG DES Triple 8-Bit, 20 MSPS, RGB, 3-Channel D/A Converter Features Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 8-Bit The HI2304 is a triple 8-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 8-bit, pixel inputs, one each for red, green, and blue video data. A single 3.3V power supply and pixel clock input can be controlled individually, or connected together as one. The HI2304 also has BLANK video control signal. For faster speed and 5.0V operation, refer to the HI1178. • Maximum Conversion Speed . . . . . . . . . . . . . . . 20MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . . .50mW (330Ω Load for 1.2VP-P Output) • Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . +3.3V Ordering Information • Low Glitch Noise PART NUMBER • Direct Replacement for Sony CXD2304 Applications TEMP. RANGE (oC) HI2304JCQ -20 to 75 PACKAGE 48 Ld MQFP PKG. NO. Q48.7x7-S • Digital TV • Graphics Display • High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation Pinout R0 B0 G0 G0 VG B0 AVDD AVDD AVDD AVDD DVDD DVDD HI2304 (MQFP) TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 R0 R0 1 R1 2 3 35 IREF 34 VREF 4 33 5 32 6 7 31 AVSS VB DVSS 30 DVSS R7 8 29 G0 G1 9 28 BCK GCK 10 27 RCK 11 12 26 CE BLK B7 B6 B4 B5 B2 B3 G4 G3 25 13 14 15 16 17 18 19 20 21 22 23 24 B1 G2 B0 R6 G6 G7 R4 R5 G5 R2 R3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 10-1 File Number 4116.1 HI2304 Functional Block Diagram (LSB) R0 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 (LSB) G0 2 LSBs CURRENT CELLS DECODER 47 DVDD 48 DVDD 6 MSBs CURRENT CELLS LATCHES 36 RO 37 RO 27 RCK CLOCK GENERATOR DECODER 43 AVDD 44 AVDD 2 LSBs CURRENT CELLS 9 G1 10 45 AVDD 46 AVDD G2 11 G3 12 DECODER G4 13 38 GO 6 MSBs CURRENT CELLS LATCHES 39 GO 28 GCK G5 14 G6 15 CLOCK GENERATOR DECODER G7 16 33 AVSS 30 DVSS 2 LSBs CURRENT CELLS (LSB) B0 17 B1 18 31 DVSS B2 19 B3 20 DECODER B4 21 40 BO 6 MSBs CURRENT CELLS LATCHES 41 BO 29 BCK B5 22 B6 23 DECODER CLOCK GENERATOR B7 24 42 VG - + CURRENT CELLS (FOR FULL SCALE) BLK 25 BIAS VOLTAGE GENERATOR CE 26 34 VREF 35 IREF 32 VB Pin Descriptions PIN NO. SYMBOL 1 to 8 R0 to R7 9 to 16 G0 to G7 17 to 24 B0 to B7 EQUIVALENT CIRCUIT DESCRIPTION Digital Input. DVDD 1 TO 25 DVSS 10-2 HI2304 Pin Descriptions PIN NO. SYMBOL 25 BLK (Continued) EQUIVALENT CIRCUIT DESCRIPTION Blanking pin. No signal at “H” (Output 0V) Output condition at “L”. DVDD 25 DVSS 32 VB DVDD Connect a capacitor of about 0.1µF. DVDD + 32 - DVSS 27 RCK 28 GCK 29 BCK Clock Pin. DVDD 27 28 29 DVSS 30, 31 DVSS Digital GND. 33 AVSS Analog GND. 26 CE Chip Enable Pin. No signal (Output 0V) at “H” and minimizes power consumption. DVDD 26 DVSS 10-3 HI2304 Pin Descriptions PIN NO. SYMBOL 35 IREF (Continued) EQUIVALENT CIRCUIT AVDD 34 VREF 42 VG DESCRIPTION Connect a resistance 16 times “16R” that of output resistance value “R”. AVDD Set full scale output value. Connect a capacitor of about 0.1µF. 35 AVDD + - AVDD AVSS 34 42 AVSS AVSS 43 to 46 AVDD 37 RO 39 GO 41 BO 36 RO 39 38 GO 41 40 BO Analog VDD . Current output pin. Voltage output can be obtained by connecting a resistance. AVDD 37 Inverted current output pin. Normally dropped to analog GND. AVSS AVDD 36 38 40 AVSS 47, 48 DVDD Digital VDD . 10-4 HI2304 TA = 25oC Absolute Maximum Ratings Thermal Information Supply Voltage (VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT). . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA (Every Each Channel) Operating Conditions Temperature Range (TOPR) . . . . . . . . . . . . . . . . . . . . -20oC to 75oC Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0V to 3.6V DVDD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3.0V to 3.6V Reference Input Voltage (VREF). . . . . . . . . . . . . . . . . . . . . . . . 1.2V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns (Min) Thermal Resistance (Typical, Note 1) θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature (TSTG) . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fCLK = 20MHz, VDD = 3.3V, ROUT = 330Ω, VREF = 1.2V, RIRF = 5.1kΩ, TA = 25oC PARAMETER SYMBOL Resolution TEST CONDITIONS MIN TYP MAX UNITS - 8 - Bit n Maximum Conversion Speed fMAX 20 - - MHz Linearity Error INL -2.5 - 2.5 LSB Differential Linearity Error DNL -0.5 - 0.5 LSB Full Scale Output Voltage VFS 1.12 1.24 1.36 V Full Scale Output Ratio (Note 1) FSR 0 1.5 3 % Full Scale Output Current IFS - 3.8 - mA Offset Output Voltage VOS - - 1 mV Power supply Current IDD - 15 - mA 14.3MHz, at Color Bar Data input H Level IIH - - 5 µA L Level IIL -5 - - µA Set Up Time tS 7 - - ns Hold Time tH 3 - - ns Digital Input Current Propagation Delay Time tPD - 20 - ns Glitch Energy GE - 150 - pV/s Crosstalk CT - 53 - dB 1MHz Sine Wave Output NOTE: 2. Full Scale Output Ratio = I/O Chart Full scale voltage of channel ------------------------------------------------------------------------------------------------------------------------------- – 1 Average of the full-scale voltage of the channels x 100(%). (When Full Scale Output Voltage at 2.00V) INPUT CODE MSB 1 1 1 1 OUTPUT VOLTAGE 1 1 1 LSB 1 0 0 0 0 0.6V 0 0 0 0 0V 1.2V • • • 1 0 0 0 • • • 0 0 0 0 10-5 HI2304 Timing Diagram tPW1 tPW1 CLK tS tH tS tH tS tH DATA tPD 100% 50% D/A OUT tPD tPD 0% Typical Application Circuit B (BLUE) OUT 330 AVSS G (GREEN) OUT 330 DVDD AVSS AVDD R (RED) OUT 0.1µ 330 48 47 46 45 44 43 42 41 40 39 38 37 (LSB) R (RED) IN 1 36 2 35 3 34 4 33 5 32 AVSS AVDD 1.2V 1K 5.1K AVSS AVSS 0.1µ 6 31 HI2304 7 30 8 (BCK) 29 9 (GCK) 28 10 (RCK) 27 11 26 12 25 (MSB) (LSB) (MSB) (LSB) G (GREEN) IN (MSB) 13 14 15 16 17 18 19 20 21 22 23 24 B (BLUE) IN 10-6 DVSS CLOCK IN DVSS HI2304 Notes On Operation • How to Select the Output Resistance resistance value can curb power consumption. On the other hand, glitch energy and data settling time will inversely increase. Set the most suitable value according to the desired application. The HI2304 is a current output D/A converter. To obtain the output voltage, connect the resistance to IO pin (RO, GO, BO). For specifications we have: • Phase Relation Between Data and Clock To obtain the expected performance as a D/A converter, it is necessary to set properly the phase relation between data and clock, applied from the exterior. Be sure to satisfy the provisions of the set up time (tS) and hold time (tH) as stipulated in the Electrical Characteristics. Output Full Scale Voltage VFS = 1.2 [V]. Output Full Scale Current IFS = 3.8 [mA]. Calculate the output resistance value from the relation of VFS = IFS x R. Also, 16 times resistance of the output resistance is connected to reference current pin IREF . In some cases, however, this turns out to be a value that does not actually exist. In such a case a value close to it can be used as a substitute. Here, please note that VFS becomes VFS = VREF x 16R/R. R is the resistance connected to IO while R is connected to IREF . Increasing the • VDD , VSS To reduce noise effects, separate analog and digital systems in the device periphery. For VDD pins, both digital and analog, bypass respective GNDs by using a ceramic capacitor of about 0.1µF, as close as possible to the pin. Test Circuits R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 8-BIT COUNTER WITH LATCH R0 37 330 AVSS OSCILLOSCOPE G0 39 25 BLK 0.1µ 330 26 CE 32 VB HI2304 B0 41 AVSS 330 DVSS AVSS AVDD CLK 20MHz SQUARE WAVE 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K 5.1K AVSS FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 8-BIT COUNTER WITH LATCH R0 37 330 AVSS 25 BLK DELAY CONTROLLER 0.1µ 330 26 CE B0 41 32 VB HI2304 AVSS 330 DVSS CLK 1MHz SQUARE WAVE OSCILLOSCOPE G0 39 AVSS AVDD DELAY CONTROLLER 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K 5.1K AVSS FIGURE 2. SET-UP HOLD TIME GLITCH ENERGY TEST CIRCUIT 10-7 HI2304 Test Circuits (Continued) ALL “1” DIGITAL WAVEFORM GENERATOR R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 R0 37 330 AVSS 25 BLK 0.1µ SPECTRUM ANALYZER G0 39 330 26 CE B0 41 32 VB HI2304 AVSS 330 DVSS AVSS AVDD CLK 20MHz SQUARE WAVE 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K 5.1K AVSS FIGURE 3. CROSSTALK TEST CIRCUIT (See Figure 7) R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 CONTROLLER R0 37 330 AVSS 25 BLK 0.1µ DVM G0 39 330 26 CE B0 41 32 VB HI2304 AVSS 330 DVSS AVSS AVDD CLK 20MHz SQUARE WAVE 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K 5.1K AVSS FIGURE 4. DC CHARACTERISTICS TEST CIRCUIT 10-8 HI2304 Test Circuits (Continued) R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 B0 TO B7 17 TO 24 FREQUENCY DEMULTIPLIER R0 37 330 AVSS 25 BLK 0.1µ OSCILLOSCOPE G0 39 330 26 CE B0 41 32 VB HI2304 AVSS 330 DVSS AVSS AVDD CLK 1MHz SQUARE WAVE 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K 5.1K AVSS FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT ALL “1” DIGITAL WAVEFORM GENERATOR ALL “1” R0 TO R7 1 TO 8 G0 TO G7 9 TO 16 R0 37 330 B0 TO B7 17 TO 24 AVSS 25 BLK 0.1µ SPECTRUM ANALYZER G0 39 330 26 CE B0 41 32 VB HI2304 AVSS 330 DVSS AVSS AVDD CLK 20MHz SQUARE WAVE 27 RCK VG 42 28 GCK VREF 34 29 BCK IREF 35 0.1µ 1K AVSS FIGURE 6. SNR TEST CIRCUIT (See Figure 8) 10-9 SNR: Difference between primary component and secondary distortion. HI2304 80 80 60 60 SNR (dB) CROSSTALK (dB) Typical Performance Curves 40 40 20 20 0 0 0.1M 1M 0.1M 10M FIGURE 7. CROSSTALK 10M FIGURE 8. SNR (DIFFERENCE BETWEEN PRIMARY COMPONENT AND SECONDARY DISTORTION) 1.27 20 CURRENT CONSUMPTION (mA) OUTPUT FULL SCALE VOLTAGE (V) 1M OUTPUT FREQUENCY (Hz) OUTPUT FREQUENCY (Hz) 1.26 0 -25 0 25 50 10 0 75 10K AMBIENT TEMPERATURE (oC) 100K FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE 10M FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION 400 GLITCH ENERGY (pV/s) 1M OUTPUT FREQUENCY (Hz) 200 0 200 400 600 FIGURE 11. OUTPUT RESISTANCE vs GLITCH ENERGY 10-10 HI2304 Reference Measurement Condition and Description AVDD = 3.3V. DVDD = 3.3V. VREF = 1.2V. RIRF = 5.1kΩ. TA = 25oC. Figure 7 and Figure 8 refer to the measurement circuit. Figure 9 is input data = all 1. Figure 10 is input data = output of incremental counter, current consumption is total of 3ch. 10-11