HI2309 ® January 1998 Features NS ESIG D NEW r at OR F e nt e c D C E 0 t r D 5 EN HI30 p po m/ts OMM See ical Su ersil.co C E n t R h w .in Te c N OT our L or w w t c RSI onta or c 8-INTE 1-88 Triple 10-Bit, 50 MSPS, 3-Channel D/A Converter Description • Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . Triple 10-Bit • Maximum Conversion Speed . . . . . . . . . . . . . . . 50MHz • RGB 3-Channel Input/Output • Differential Linearity Error . . . . . . . . . . . . . . . ±0.5 LSB • Low Power Consumption . . . . . . . . . . . . . . . . . . 200mW (200Ω Load for 2V P-P Output) • Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . +5V Single • Low Glitch The HI2309 is a triple 10-bit, high-speed, CMOS D/A converter designed for video band use. It has three separate, 10-bit, pixel inputs, one each for red, green, and blue video data. A single 5.0V power supply and pixel clock input is all that is required to make the device operational. A bias voltage generator is internal. Each channel clock input can be controlled individually, or connected together as one. The HI2309 also has BLANK video control signal. Ordering Information • Direct Replacement for Sony CXD2309 PART NUMBER Applications TEMP. RANGE ( oC) HI2309JCQ • Digital TV -20 to 75 PACKAGE PKG. NO. 48 Ld MQFP Q48.12x12-S • Graphics Display • High Resolution Color Graphics • Video Reconstruction • Instrumentation • Image Processing • I/Q Modulation Pinout VREF AVDD VG AVDD RO AVDD AVSS AVSS GO BO DVDD AVSS HI2309 (MQFP) TOP VIEW 1 48 47 46 45 44 43 42 41 40 39 38 37 36 R1 2 35 VB R2 R3 3 34 DVSS 4 33 R4 5 32 R5 6 31 BCK GCK RCK R6 7 30 B9 R7 8 29 R8 R9 9 28 B8 B7 10 27 B6 26 B5 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 10-1 IREF B4 B3 B2 B0 (LSB) B1 G8 G9 G7 G6 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 G2 (LSB) G1 G4 G5 G0 G3 (LSB) R0 File Number 4118.2 HI2309 Functional Block Diagram (LSB) R0 1 R1 2 R2 3 R3 4 R4 5 R5 6 R6 7 R7 8 R8 9 43 AVSS 4 LSBs CURRENT CELLS 42 RO 6 LSBs CURRENT CELLS LATCHES DECODER CLOCK GENERATOR DECODER R9 10 RCK 31 (LSB) G0 11 45 AVSS 4 LSBs CURRENT CELLS G1 12 G2 13 44 GO G3 14 G4 15 G5 16 6 LSBs CURRENT CELLS LATCHES DECODER G6 17 G7 18 G8 19 DECODER CLOCK GENERATOR G9 20 GCK 32 (LSB) B0 21 47 AVSS 4 LSBs CURRENT CELLS B1 22 B2 23 46 BO B3 24 41 AVDD B4 25 B5 26 DECODER 6 LSBs CURRENT CELLS LATCHES B6 27 40 AVDD 39 AVDD B7 28 B8 29 CLOCK GENERATOR DECODER B9 30 38 VG BCK 33 DVDD 48 - BIAS VOLTAGE GENERATOR CURRENT CELLS (FOR FULL SCALE) VB 35 DVSS 34 10-2 + 37 VREF 36 IREF HI2309 Pin Descriptions PIN NO. SYMBOL 1 to 10 R0 to R9 11 to 20 G0 to G9 21 to 30 B0 to B9 EQUIVALENT CIRCUIT DESCRIPTION Digital Input. DVDD 1 TO 30 DVSS 31 RCLK 32 GCLK 33 BCLK Clock pin. DVDD 31 TO 33 DVSS 34 DVSS 35 VB Digital GND. Connect an approximately 0.1µF capacitor. DVDD DVDD + 35 - DVSS 36 IREF 37 VREF 38 VG AVDD Connect a “16R” resistor which is 16 times the output resistance “R”. AVDD Sets an output full scale value. Connect an approximately 0.1µF capacitor. + 36 - AVDD AVDD AVDD 38 37 AVSS AVSS 39 to 41 AV DD 42 RO 44 GO 46 BO Analog VDD . Current Output. Output can be obtained by connecting a resistor (200Ω typical). AVDD 42 44 46 AVSS AVSS 43, 45, 47 AV DD Analog GND. 47, 48 DVDD Digital VDD . 10-3 HI2309 Absolute Maximum Ratings TA = 25oC Thermal Information Supply Voltage (V DD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Input Voltage (V IN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD to VSS Output Current (IOUT) . . . . . . . . . . . . . . . . . . . . . . . . .0mA to 15mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC 150oC Thermal Resistance (Typical, Note 1) Operating Conditions Supply Voltage AVDD , AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V DV DD , DVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.25V Reference Input Voltage (V REF) . . . . . . . . . . . . . . . . . .0.5V to 2.0V Clock Pulse Width tPW1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) tPW0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Min) Temperature Range (TOPR). . . . . . . . . . . . . . . . . . . . -20oC to 75oC θJA (oC/W) MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications fCLK = 50MHz, VDD = 5V, R = 200Ω , VREF = 2.0V, TA = 25oC PARAMETER MIN TYP MAX UNITS n - 10 - Bit fMAX 50 - - MHz Linearity Error EL -2.0 - 2.0 LSB Differential Linearity Error ED -0.5 - 0.5 LSB Output Full Scale Voltage V FS 1.8 1.92 2.0 V Output Full Scale Current IFS 9.0 9.6 10 mA Output Offset Voltage VOS - - 1 mV Supply Current IDD - 40 50 mA High Level IIH - - 5 µA Low Level IIL -5 - - µA High Level V IH DVDD = 4.75 to 5.25V 2.15 - - V Low Level VIL DVDD - 4.75 to 5.25V - - 0.85 V VOC 1.8 1.92 2.0 V Setup Time tS 6 - - ns Hold Time tH 3 - - ns Propagation Delay Time tPD - 14 - ns Glitch Energy GE For ROUT = 100Ω, 1VP-P Output - 50 - pV/s Cross Talk CT For 10MHz Sine Wave Output 40 42 - dB SNR For 1MHz Sine Wave Output 50 55 - dB Resolution Maximum Conversion Speed Digital Input Current Digital Input Voltage Precision Guaranteed Output Voltage Range SNR SYMBOL TEST CONDITIONS NOTE: Full scale voltage for each channel 2. Output full scale ratio = ------------------------------------------------------------------------------------------------------------------------- – 1 x 100% . Average of full scale voltage for each channel 10-4 HI2309 Test Circuits 10 10-BIT COUNTER WITH LATCH 10 10 RO TO R9 1 TO 10 RO 42 200 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 AVSS 43 AVSS GO 44 OSCILLOSCOPE 200 0.1µ AVSS 45 35 VB AVSS BO 46 200 DVSS CLK 50MHz SQUARE WAVE 31 RCK AVSS 47 32 GCK VG 38 33 BCK AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3K HI2309 AVSS FIGURE 1. MAXIMUM CONVERSION RATE TEST CIRCUIT 10 10-BIT COUNTER WITH LATCH DELAY CONTROLLER 10 10 0.1µ RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 RO 42 200 AVSS 43 AVSS GO 44 OSCILLOSCOPE 200 AVSS 45 35 VB AVSS BO 46 200 DVSS CLK 50MHz SQUARE WAVE DELAY CONTROLLER 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 AVSS AVDD 2V 0.1µ IREF 36 3.3K HI2309 AVSS FIGURE 2. SETUP HOLD TIME GLITCH ENERGY TEST CIRCUIT 10-5 HI2309 Test Circuits (Continued) DVDD DIGITAL WAVEFORM GENERATOR 10 10 10 RO TO R9 1 TO 10 RO 42 200 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 AVSS 43 AVSS GO 44 200 0.1µ AVSS 45 35 VB AVSS BO 46 DVSS CLK 50MHz SQUARE WAVE SPECTRUM ANALYZER 200 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 AVSS AVDD 2V 0.1µ IREF 36 3.3K HI2309 AVSS FIGURE 3. CROSS TALK TEST CIRCUIT 10 10-BIT COUNTER WITH LATCH 10 10 0.1µ RO TO R9 1 TO 10 RO 42 200 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 AVSS 43 AVSS GO 44 OSCILLOSCOPE 200 AVSS 45 35 VB AVSS BO 46 CLK 50MHz SQUARE WAVE 200 DVSS 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 AVSS AVDD 2V 0.1µ IREF 36 3.3K HI2309 AVSS FIGURE 4. DC CHARACTERISTICS TEST CIRCUIT 10-6 HI2309 Test Circuits (Continued) 10 10-BIT COUNTER WITH LATCH RO TO R9 1 TO 10 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 10 RO 42 200 AVSS 43 AVSS GO 44 OSCILLOSCOPE 200 0.1µ AVSS BO 46 DELAY CONTROLLER CLK 50MHz SQUARE WAVE AVSS 45 35 VB 200 DVSS DELAY CONTROLLER 31 RCK AVSS 47 32 GCK VG 38 33 BCK AVSS AVDD VREF 37 2V 0.1µ IREF 36 3.3K HI2309 AVSS FIGURE 5. PROPAGATION DELAY TIME TEST CIRCUIT 10 ALL “1” DIGITAL WAVEFORM GENERATOR 10 10 ALL “1” 0.1µ RO TO R9 1 TO 10 G0 TO G9 11 TO 20 B0 TO B9 21 TO 30 RO 42 200 AVSS 43 AVSS GO 44 200 AVSS 45 35 VB AVSS BO 46 200 DVSS CLK 50MHz SQUARE WAVE 31 RCK AVSS 47 32 GCK VG 38 33 BCK VREF 37 2V AVSS AVDD 0.1µ IREF 36 3.3K HI2309 FIGURE 6. SNR TEST CIRCUIT 10-7 AVSS SPECTRUM ANALYZER HI2309 Application Circuit C C R2 CLOCK INPUT 36 R3 C C 34 33 32 31 R1 27 26 25 24 38 23 39 22 40 21 41 20 17 45 16 46 15 47 14 48 13 3 4 LSB 2 5 6 LSB 18 44 1 B CH INPUT 19 HI2309 43 R1 29 28 37 42 R1 30 7 8 9 10 11 12 G CH INPUT AVDD DVDD AVSS DVSS LSB C R4 35 R CH INPUT • When the power supply (AV DD and DV DD is 5.0. • R1 - 200Ω. • R2 = 3.3kΩ. • R3 = 3.0kΩ. • R4 = 2.0kΩ. • C = 0.1µF. Application circuits shown are typical examples illustrating the operation of the devices. Intersil cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. 2.0 GLITCH ENERGY (pV/S) OUTPUT FULL SCALE VOLTAGE (V) Typical Performance Curves 1.0 1.0 2.0 100 50 100 200 OUTPUT RESISTANCE (Ω) REFERENCE VOLTAGE (V) FIGURE 7. OUTPUT FULL SCALE VOLTAGE vs REFERENCE VOLTAGE FIGURE 8. OUTPUT RESISTANCE vs GLITCH ENERGY 10-8 (Continued) ∆V = 0.02mV/oC CURRENT CONSUMPTION (mA) OUTPUT FULL SCALE VOLTAGE (V) Typical Performance Curves 1.95 1.90 0 -25 0 25 50 50 40 10 75 AMBIENT TEMPERATURE (oC) 1 5 10 15 20 OUTPUT FREQUENCY (MHz) FIGURE 9. OUTPUT FULL SCALE VOLTAGE vs AMBIENT TEMPERATURE FIGURE 10. OUTPUT FREQUENCY vs CURRENT CONSUMPTION Standard Measurement Conditions and Description time. Set the best values according to the purpose of use. VDD = 5.0V. R = 200Ω. For HI2309 to display the desired performance as a D/A converter, the data transmitted from outside and the clock must be synchronized properly. Adjust the setup time (tS) and hold time (tH ) as specified in “Electrical Characteristics.” 16R = 3.3kΩ. VDD , VSS : TA = 25oC. Separate the analog and digital signals around the device to reduce noise effects. Bypass the VDD pin to each GND with a 0.1µF ceramic capacitor as near as possible to the pin for both digital and analog signals. Correlation Between Data and Clock: VREF = 2.0V. VREF in Figure 9 is fixed to 2VDC without resistor dividing. Input data in Figure 10 = all “0” and “1” of rectangular wave, clock frequency = 50MHz for a total value of three channels. Notes On Operation Selecting the Output Resistance: HI2309 is a current output type D/A converter. To create the output voltage, connect the resistor to the current output pin. Specifications: Latch Up: The AVDD and DV DD pins must be able to share the same power supply of the board. This is to prevent latch up caused by potential difference between the two pins when the power is turned on. IREF Pin: The IREF pin is very sensitive to improve the AC Characteristics. Pay attention for capacitance component not to attach to this pin because its output may become unstable. Output full scale voltage VFS Max = 2.0 [V]. Output full scale current IFS Max = 10 [mA]. Calculate the output resistance from VFS = IFS x R. Connect a resistance sixteen times the output resistance to the reference current pin IREF . In some cases, this value may not exist, a similar value can be used instead. Note that the VFS will be the following: VG Pin: It is recommended to use a 1µF capacitor to improve the AC Characteristics, though the typical capacitance value externally connected to the VG Pin is 0.1µF. VFS = V REF x 16 R/R’. R is the resistor to be connected to the IO and R’ is the resistor to be connected to the IREF . Power consumption can be reduced by increasing the resistance, but this will on the contrary, increase the glitch energy and data setting 10-9