HI3306 6-Bit, 15 MSPS, Flash A/D Converter December 1997 Features Description • CMOS Low Power (Typ). . . . . . . . . . . . . . . . . . . . .55mW The HI3306 family are CMOS parallel (FLASH) analog-todigital converters designed for applications demanding both low power consumption and high speed digitization. Digitizing at 15MHz, for example, requires only about 55mW. • Parallel Conversion Technique • Single Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V • Sampling Rate with Single 5V Supply . . . . . . . . 15MHz The HI3306 family operates over a wide, full scale signal input voltage range of 1V up to the supply voltage. Power consumption is as low as 15mW, depending upon the clock frequency selected. The HI3306 offers improved linearity at a lower reference voltage and high operating speed with a 5V supply. • 6-Bit Latched Three-State Output with Overflow Bit • Linearity (INL, DNL): - HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . . . . . - HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . . . . . . - HI3306JIB/15 . . . . . . . . . . . . . . . . . . . . . . . . . - HI3306JIB/10 . . . . . . . . . . . . . . . . . . . . . . . . . ±0.5 LSB ±0.5 LSB ±0.5 LSB ±0.5 LSB The overflow bit makes possible the connection of two or more HI3306s in series to increase the resolution of the conversion system. • Sampling Rate: - HI3306JIP/15 . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns) - HI3306JIP/10 . . . . . . . . . . . . . . . . . . . . 10MHz (100ns) Sixty-four paralleled auto balanced comparators measure the input voltage with respect to a known reference to produce the parallel bit outputs in the HI3306. Sixty-three comparators are required to quantize all input voltage levels in this 6-bit converter, and the additional comparator is required for the overflow bit. - HI3306JIB/15 . . . . . . . . . . . . . . . . . . . . . 15MHz (67ns) - HI3306JIB/10 . . . . . . . . . . . . . . . . . . . . 10MHz (100ns) Ordering Information Applications TEMP. RANGE (oC) • Video Digitizing PART NUMBER • Digital Communication Systems HI3306JIP/15 -40 to 85 18 Ld PDIP E18.3 • High Speed Data Acquisition HI3306JIP/10 -40 to 85 18 Ld PDIP E18.3 • Radar Signal Processing HI3306JIB/15 -40 to 85 20 Ld SOIC M20.3 HI3306JIB/10 -40 to 85 20 Ld SOIC M20.3 PACKAGE PKG. NO. Pinouts HI3306 (PDIP) TOP VIEW (MSB) B6 1 OVERFLOW 2 VSS 3 VZ 4 HI3306 (SOIC) TOP VIEW 14 B2 CE2 6 13 B1 (LSB) CLK 7 12 VDD VREF + 9 OVERFLOW 2 17 B4 REF 16 CENTER 15 B3 CE2 5 PHASE 8 (MSB) B6 1 18 B5 NC 4 19 B4 18 REF CENTER 17 B3 VZ 5 16 B2 VSS 3 11 VIN 10 VREF - CE2 6 15 B1 (LSB) CE1 7 14 VDD CLK 8 13 NC PHASE 9 12 VIN VREF + 10 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 1 20 B5 11 VREF - File Number 4136.2 HI3306 Functional Block Diagram VIN φ1 φ1 φ1 φ2 R/2 COMP 64 φ2 VREF+ THREE-STATE R COMP 63 R R ≅ 120Ω REF CENTER COMP 32 R COMPARATOR LATCHES AND ENCODER LOGIC R COMP 2 R D Q CL OVERFLOW D Q CL B6 (MSB) D Q CL B5 D Q CL B4 D Q CL B3 D Q CL B2 D Q CL B1 (LSB) VREF COMP 1 R/2 ≅ 50kΩ CLOCK CE1 φ2 (SAMPLE UNKNOWN) PHASE φ1 (AUTO BALANCE) CE2 ZENER 6.2V NOMINAL DIODE VDD VSS VSS Typical Application Circuit OF B6 1 B6 2 OF B4 17 3 VSS RC 16 B2 4 VZ B3 15 B1 (LSB) 5 CE2 B2 14 6 CE1 B1 13 7 CLK VDD 12 8 PH 9 VREF+ HI3306 B5 18 B5 0.1µF 6.2V 560Ω +12V B4 B3 DATA OUTPUT +5V +5V CLOCK +12V 0.2µF 5kΩ + CA741CE VIN 11 0.1µF 2 VREF- 10 SIGNAL INPUT 10µF HI3306 Absolute Maximum Ratings Thermal Information DC Supply Voltage Range, VDD Voltage Referenced to VSS Terminal . . . . . . . . . . . -0.5V to +8.5V Input Voltage Range All Inputs Except Zener. . . . . . . . . . . . . . . . . -0.5V to VDD + 0.5V DC Input Current CLK, PH, CE1, CE2, VIN . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Thermal Resistance (Typical, Note 1) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3V to 8V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for HI3306XXX/15, 10MHz for HI3306XXX/10 PARAMETER TEST CONDITIONS MIN TYP MAX UNITS SYSTEM PERFORMANCE Resolution 6 - - Bits Integral Linearity Error, INL - ±0.25 ±0.5 LSB - ±0.25 ±0.5 LSB Offset Error (Unadjusted) (Note 2) - ±0.5 ±1 LSB Gain Error (Unadjusted) (Note 3) Differential Linearity Error, DNL - ±0.5 ±1 LSB Gain Temperature Coefficient - +0.1 - mV/oC Offset Temperature Coefficient - -0.1 - mV/oC DYNAMIC CHARACTERISTICS Input Signal Level 0.5dB Below Full Scale Maximum Conversion Speed Maximum Conversion Speed HI3306XXX/10 10 13 - MSPS HI3306XXX/15 15 20 - MSPS 12 - - MSPS 18 - - MSPS DC - fCLOCK/2 MHz - 30 - MHz HI3306XXX/10 HI3306XXX/15 Allowable Input Bandwidth (Note 5) φ1, φ2 ≥ Minimum (Note 5) -3dB Input Bandwidth Signal to Noise Ratio, SNR fS = 15MHz, fIN = 100kHz - 34.6 - dB RMS Signal = ---------------------------------RMS Noise fS = 15MHz, fIN = 5MHz - 33.4 - dB Signal to Noise Ratio, SINAD fS = 15MHz, fIN = 100kHz - 34.2 - dB RMS Signal = -----------------------------------------------------------------RMS Noise + Distortion fS = 15MHz, fIN = 5MHz - 29.0 - dB Total Harmonic Distortion, THD fS = 15MHz, fIN = 100kHz - -46.0 - dBc fS = 15MHz, fIN = 5MHz - -30.0 - dBc fS = 15MHz, fIN = 100kHz - 5.5 - Bits fS = 15MHz, fIN = 5MHz - 4.5 - Bits Effective Number of Bits, ENOB ANALOG INPUTS Positive Full Scale Input Range (Notes 4, 5) 1 4, 8 VDD + 0.5 V Negative Full Scale Input Range (Notes 4, 5) -0.5 0 VDD - 1 V Input Capacitance Input Current VIN = 4.92V, VDD = 5V - 15 - pF - - ±500 µA 5.4 6.2 7.4 V - 12 25 Ω INTERNAL VOLTAGE REFERENCE Zener Voltage IZ = 10mA Zener Dynamic Impedance IZ = 10mA, 20mA 3 HI3306 Electrical Specifications TA = 25oC, VDD = 5V, VREF + = 4.8V, VSS = VREF - = GND, Clock = 15MHz Square Wave for HI3306XXX/15, 10MHz for HI3306XXX/10 (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNITS - -0.5 - mV/oC 650 1100 1550 Ω All Digital Inputs (Note 5) - - 0.3 x VDD V Maximum VIN , Logic 1 All Digital Inputs (Note 5) 0.7 x VDD - - V Digital Input Current Except CLK, VIN = 0V, 5V - ±1 ±5 µA Digital Input Current CLK Only - ±100 ±200 µA Zener Temperature Coefficient REFERENCE INPUTS Resistor Ladder Impedance DIGITAL INPUTS Maximum VIN , Logic 0 DIGITAL OUTPUTS Digital Output Three-State Leakage VOUT = 0V, 5V - ±1 ±5 µA Digital Output Source Current VOUT = 4.6V -1.6 - - mA Digital Output Sink Current VOUT = 0.4V 3.2 - - mA 50 - ∞ ns 33 - ∞ 33 - 5000 ns 22 - 5000 ns - 8 - ns - 100 - psP-P - 35 50 ns TIMING CHARACTERISTICS Auto Balance Time (φ1) HI3306XXX/10 HI3306XXX/15 Sample Time (φ2) HI3306XXX/10 (Note 5) HI3306XXX/15 Aperture Delay Aperture Jitter Output Data Valid Delay, tD HI3306XXX/10 HI3306XXX/15 - 30 40 ns 15 25 - ns Output Enable Time, tEN - 20 - ns Output Disable Time, tDIS - 15 - ns Continuous Conversion (Note 5) - 11 20 mA - 14 25 mA Continuous φ1 - 7.5 15 mA Output Data Hold Time, tH (Note 5) POWER SUPPLY CHARACTERISTICS IDD Current, Refer to Figure 4 HI3306XXX/10 HI3306XXX/15 IDD Current NOTES: 2. 3. 4. 5. OFFSET ERROR is the difference between the input voltage that causes the 00 to 01 output code transition and (VREF + - VREF -)/128. GAIN ERROR is the difference the input voltage that causes the 3F16 to overflow output code transition and (VREF + - VREF -) x 127/128. The total input voltage range, set by VREF + and VREF -, may be in the range of 1 to (VDD + 1) V. Parameter not tested, but guaranteed by design or characterization. Timing Waveforms COMPARATOR DATA IS LATCHED CLOCK IF PHASE IS HIGH φ2 CLOCK IF PHASE IS LOW DECODED DATA IS SHIFTED TO OUTPUT REGISTERS φ1 φ2 φ1 φ2 AUTO BALANCE SAMPLE N+1 AUTO BALANCE SAMPLE N+2 tD tH DATA N-2 DATA N-1 FIGURE 1. INPUT-TO-OUTPUT 4 DATA N HI3306 Timing Waveforms CE1 CE2 tDIS tEN tDIS tDIS HIGH IMPEDANCE HIGH IMPEDANCE DATA BITS 1-6 DATA DATA HIGH IMPEDANCE DATA OF DATA FIGURE 2. OUTPUT ENABLE SAMPLE ENDS SAMPLE ENDS φ1 φ2 CLOCK φ2 CLOCK φ1 φ2 φ1 φ2 tD tD NEW DATA OLD DATA OUTPUT φ1 OLD DATA OUTPUT OLD DATA +1 FIGURE 3A. NEW DATA FIGURE 3B. SAMPLE ENDS CLOCK φ2 φ1 φ2 φ1 φ2 tD OUTPUT INVALID DATA OLD DATA NEW DATA FIGURE 3C. FIGURE 3. PULSE MODE Typical Performance Curves 50 125 AMBIENT TEMPERATURE (oC) TA = 25oC, VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 40 IDD (mA) DISSIPATION LIMITED 30 VDD = 8V VDD = 7V VDD = 6V VDD = 5V 20 10 fCLK = 1MHz fCLK = 3MHz fCLK = 10MHz fCLK = 15MHz fCLK = 20MHz 100 MAXIMUM AMBIENT TEMPERATURE - PLASTIC 75 50 VREF + = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 ZENER NOT CONNECTED VDD = 3V 25 0.1 1 CLOCK FREQUENCY (MHz) 10 3 4 5 6 7 8 VDD (V) FIGURE 4. TYPICAL IDD AS A FUNCTION OF VDD FIGURE 5. TYPICAL MAXIMUM AMBIENT TEMPERATURE AS A FUNCTION OF SUPPLY VOLTAGE 5 HI3306 Typical Performance Curves (Continued) 0.35 TA = 25oC, VREF = 4.8V VDD = 5V 1.2 0.25 INTEGRAL NON-LINEARITY (LSB) NON-LINEARITY (LSB) 0.30 TA = 25oC, VDD = 5V fCLK = 15MHz 0.20 0.15 DIFFERENTIAL 0.10 0.05 0 0.1 1.0 0.8 INTEGRAL 0.6 0.4 DIFFERENTIAL 0.2 0 1 10 0 1 2 CLOCK FREQUENCY (MHz) FIGURE 6. TYPICAL NON-LINEARITY AS A FUNCTION OF CLOCK SPEED 5 fCLK = 15MHz, VREF + = VDD VREF - = VSS VREF + = VDD , VREF - = VSS +10 4 FIGURE 7. TYPICAL NON-LINEARITY AS A FUNCTION OF REFERENCE VOLTAGE +400 VDD = 8V VDD = 8V +5 INPUT CURRENT (µA) PEAK INPUT CURRENT (mA) +15 3 REFERENCE VOLTAGE (V) VDD = 5V 0 -5 -10 -15 +200 VDD = 5V 0 -200 -400 -600 -800 0 1 2 3 4 5 6 7 INPUT VOLTAGE (V) 8 0 FIGURE 8. TYPICAL PEAK INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE 1 2 3 4 5 6 7 INPUT VOLTAGE (V) 8 FIGURE 9. TYPICAL AVERAGE INPUT CURRENT AS A FUNCTION OF INPUT VOLTAGE 11 TA = 25oC, VREF+ = VDD VIN = 0 TO VREF + SINE WAVE AT fCLK/2 10 30 9 25 IDD (mA) DECODER LIMITED DISSIPATION LIMITED 20 8 7 15 6 10 5 5 4 0 3 4 5 6 SUPPLY VOLTAGE (V) 7 0 8 FIGURE 10. TYPICAL MAXIMUM CLOCK FREQUENCY AS A FUNCTION OF SUPPLY VOLTAGE 5 10 fS (MHz) 15 20 FIGURE 11. DEVICE CURRENT vs SAMPLE FREQUENCY 6 HI3306 Typical Performance Curves (Continued) 6.0 32.5 5.7 30.0 5.4 5.1 ENOB (LSB) 27.5 tD (ns) fS = 15MHz, fI = 1MHz 25.0 22.5 4.8 4.5 4.2 3.9 20.0 3.6 17.5 3.3 15.0 -50 -25 0 25 50 75 3.0 -40 -30 -20 -10 100 TEMPERATURE (oC) FIGURE 12. DATA DELAY vs TEMPERATURE 12.6 0.9 11.2 0.8 NON-LINEARITY (LSB) 1.0 9.8 7.0 5.6 4.2 80 90 DNL 0 10 20 30 40 50 TEMPERATURE (oC) 60 FIGURE 15. NON-LINEARITY vs TEMPERATURE fS = 15MHz 5.4 5.1 4.8 4.5 4.2 3.9 3.6 3.3 0.5 80 0.3 6.0 3.0 0.0 70 INL 0 -40 -30 -20 -10 90 FIGURE 14. IDD vs TEMPERATURE 5.7 90 0.4 0.1 70 80 0.5 1.4 60 70 fS = 15MHz 0.6 0.2 10 20 30 40 50 TEMPERATURE (oC) 60 0.7 2.8 ENOB (LSB) IDD (mA) 8.4 0 10 20 30 40 50 TEMPERATURE (oC) FIGURE 13. ENOB vs TEMPERATURE 14.0 0.0 -40 -30 -20 -10 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 fI (MHz) FIGURE 16. ENOB vs INPUT FREQUENCY 7 4.5 5.0 HI3306 Pin Descriptions PIN NUMBER PDIP SOIC 1 1 2 2 3 3, 4 4 5 5 6 6 7 7 8 8 9 9 10 11 12 13 14 15 16 17 18 NAME B6 OF VSS VZ CE2 CE1 CLK Phase 10 11 12 13, 14 15 16 17 18 19 20 DESCRIPTION Bit 6, Output (MSB). Overflow, Output. Digital Ground. Zener Reference Output. Three-State Output Enable Input, Active Low. See Table 1. Three-State Output Enable Input, Active High. See Table 1. Clock Input. Sample clock phase control input. When PHASE is low, “Sample Unknown” occurs when the clock is low and “Auto Balance” occurs when the clock is high (see text). Reference Voltage Positive Input. Reference Voltage Negative Input. Analog Signal Input. Power Supply, +5V. Bit 1, Output (LSB). Bit 2, Output. Bit 3, Output. Reference Ladder Midpoint. Bit 4, Output. Bit 5, Output. VREF + VREF VIN VDD B1 B2 B3 REF(CTR) B4 B5 TABLE 1. CHIP ENABLE TRUTH TABLE CE1 0 1 X X = Don’t care CE2 1 1 0 B1 - B6 Valid Three-State Three-State OF Valid Valid Three-State TABLE 2. OUTPUT CODE TABLE (NOTE 6) INPUT VOLTAGE BINARY OUTPUT CODE (LSB) CODE DESCRIPTION VREF 6.40 (V) VREF 5.12 (V) VREF 4.80 (V) VREF 3.20 (V) OF B6 B5 B4 B3 B2 B1 DECIMAL COUNT Zero 1 LSB 2 LSB 0.00 0.10 0.20 0.00 0.08 0.16 0.00 0.075 0.15 0.00 0.05 0.10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 2 • • • • 1/ Full Scale - 1 LSB 2 1/ Full Scale 2 1/ Full Scale + 1 LSB 2 • • • • 3.10 3.20 3.30 2.48 2.56 2.64 • • • • Full Scale - 1 LSB Full Scale Overflow • • • • 2.325 2.40 2.475 1.55 1.60 1.65 0 0 0 0 1 1 1 0 0 • • • • 6.20 6.30 6.40 4.96 5.04 5.12 1 0 0 • • • • 1 0 0 1 0 0 1 0 1 • • • • 4.65 4.725 4.80 3.10 3.15 3.20 0 0 1 1 1 1 1 1 1 1 1 1 • • • • 1 1 1 1 1 1 0 1 1 NOTE: 6. The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. 8 31 32 33 62 63 127 HI3306 Device Operation Continuous Clock Operation A sequential parallel technique is used by the HI3306 converter to obtain its high speed operation. The sequence consists of the “Auto Balance” phase φ1 and the “Sample Unknown” phase φ2. (Refer to the circuit diagram.) Each conversion takes one clock cycle (see Note). With the phase control low, the “Auto Balance” (φ1) occurs during the High period of the clock cycle, and the “Sample Unknown” (φ2) occurs during the low period of the clock cycle. One complete conversion cycle can be traced through the HI3306 via the following steps. (Refer to timing diagram, Figure 1.) With the phase control in a “High” state, the rising edge of the clock input will start a “sample” phase. During this entire “High” state of the clock, the 64 comparators will track the input voltage and the 64 latches will track the comparator outputs. At the falling edge of the clock, after the specified aperture delay, all 64 comparator outputs are captured by the 64 latches. This ends the “sample” phase and starts the “auto balance” phase for the comparators. During this “Low” state of the clock the output of the latches propagates through the decode array and a 7-bit code appears at the D inputs of the output registers. On the next rising edge of the clock, this 7-bit code is shifted into the output registers and appears with time delay to as valid data at the output of the three-state drivers. This also marks the start of a new “sample” phase, thereby repeating the conversion process for this next cycle. During the “Auto Balance” phase, a transmission-gate switch is used to connect each of 64 commutating capacitors to their associated ladder reference tap. Those tap voltages will be as follows: VTAP (N) = [(VREF/64) x N] - [VREF/(2 x 64)], = VREF[(2N - 1)/126], Where: VTAP (N) = reference ladder tap voltage at point N, VREF = voltage across VREF - to VREF +, Pulse Mode Operation N = tap number (I through 64). For sampling high speed nonrecurrent or transient data, the converter may be operated in a pulse mode in one of three ways. The fastest method is to keep the converter in the Sample Unknown phase, φ2, during the standby state. The device can now be pulsed through the Auto Balance phase with a single pulse. The analog value is captured on the leading edge of φ1 and is transferred into the output registers on the trailing edge of φ1. We are now back in the standby state, φ2, and another conversion can be started, but not later than 5µs due to the eventual droop of the commutating capacitors. Another advantage of this method is that it has the potential of having the lowest power drain. The larger the time ratio between φ2 and φ1, the lower the power consumption. (See Timing Waveform, Figure 3.) NOTE: This device requires only a single-phase clock. The terminology of φ1 and φ2 refers to the High and Low periods of the same clock. The other side of the capacitor is connected to a singlestage inverting amplifier whose output is shorted to its input by a switch. This biases the amplifier at its intrinsic trip point, which is approximately, (VDD - VSS)/2. The capacitors now charge to their associated tap voltages, priming the circuit for the next phase. In the “Sample Unknown” phase, all ladder tap switches are opened, the comparator amplifiers are no longer shorted, and VlN is switched to all 64 capacitors. Since the other end of the capacitor is now looking into an effectively open circuit, any voltage that differs from the previous tap voltage will appear as a voltage shift at the comparator amplifiers. All comparators whose tap voltages were lower than VlN will drive the comparator outputs to a “low” state. All comparators whose tap voltages were higher than VlN will drive the comparator outputs to a “high” state. A second, capacitor-coupled, autozeroed amplifier further amplifies the outputs. The second method uses the Auto Balance phase, φ1, as the standby state. In this state the converter can stay indefinitely waiting to start a conversion. A conversion is performed by strobing the clock input with two φ2 pulses. The first pulse starts a Sample Unknown phase and captures the analog value in the comparator latches on the trailing edge. A second φ2 pulse is needed to transfer the data into the output registers. This occurs on the leading edge of the second pulse. The conversion now takes slightly longer, but the repetition rate may be as slow as desired. The disadvantage to this method is the higher device dissipation due to the low ratio of φ2 to φ1. (See Timing Waveform, Figure 3B.) The status of all these comparator amplifiers are stored at the end of this phase (φ2), by a secondary latching amplifier stage. Once latched, the status of the 64 comparators is decoded by a 64-bit 7-bit decode array and the results are clocked into a storage register at the rising edge of the next φ2. For applications requiring both indefinite standby and lowest power, standby can be in the φ2 (Sample Unknown) state with two φ1 pulses to generate valid data (see Figure 3C). Valid data now appears two full clock cycles after starting the conversion process. A three-state buffer is used at the output of the 7 storage registers which are controlled by two chip-enable signals. CE1 will independently disable B1 through B6 when it is in a high state. CE2 will independently disable B1 through B6 and the overflow buffers when it is in the low state (Table 1). Analog Input Considerations To facilitate usage of this device a phase-control input is provided which can effectively complement the clock as it enters the chip. Also, an on-board Zener is provided for use as a reference voltage. The HI3306 input terminal is characterized by a small capacitance (see Specifications) and a small voltagedependent current (See Typical Performance Curves). The 9 HI3306 signal-source impedance should be kept low, however, when operating the HI3306 at high clock rates. ground will accomplish the adjustment. Set VlN to 1/2 LSB and trim the pot until the 0 to 1 transition occurs. The HI3306 outputs a short (less than 10ns) current spike of up to several mA amplitude (See Typical Performance Curves) at the beginning of the sample phase. (To a lesser extent, a spike also appears at the beginning of auto balance.) The driving source must recover from the spike by the end of the same phase, or a loss of accuracy will result. If VIN for the first transition is greater than the theoretical, then the 50Ω pot should be connected between VREF and a negative voltage of about 2 LSBs. The trim procedure is as stated previously. A locally terminated 50Ω or 75Ω source is generally sufficient to drive the HI3306. If gain is required, a high speed, fast settling operational amplifier, such as the HA-5033, HA-2542, or HA5020 is recommended. In general the gain trim can also be done in the preamp circuitry by introducing a gain adjustment for the operational amplifier. When this is not possible, then a gain adjustment circuit should be made to adjust the reference voltage. To perform this trim, VlN should be set to the 63 to overflow transition. That voltage is 1/2 LSB less than VREF+ and is calculated as follows: Gain Trim Digital Input And Output Interfacing The two chip-enable and the phase-control inputs are standard CMOS units. They should be driven from less than 0.3 x VDD to at least 0.7 x VDD . This can be done from 74HC series CMOS (QMOS), TTL with pull-up resistors, or, if VDD is greater than the logic supply, open collector or open drain drivers plus pull-ups. (See Figure 20.) VlN (63 to 64 transition) = VREF - VREF/128 = VREF(127/128) To perform the gain trim, first do the offset trim and then apply the required VlN for the 63 to overflow transition. Now adjust VREF+ until that transition occurs on the outputs. The clock input is more critical to timing variations, such as φ1 becoming too short, for instance. Pull-up resistors should generally be avoided in favor of active drivers. The clock input may be capacitively coupled, as it has an internal 50kΩ feedback resistor on the first buffer stage, and will seek its own trip point. A clock source of at least 1VP-P is adequate, but extremely non-symmetrical waveforms should be avoided. Midpoint Trim The reference center (RC) is available to the user as the midpoint of the resistor ladder. To trim the midpoint, the offset and gain trims should be done first. The theoretical transition from count 31 to 32 occurs at 311/2 LSBs. That voltage is as follows: The output drivers have full rail-to-rail capability. If driving CMOS systems with VDD below the VDD of the HI3306, a CD74HC4050 or CD74HC4049 should be used to step down the voltage. If driving LSTTL systems, no step-down should be necessary, as most LSTTLs will take input swings up to 10V to 15V. VlN (31 to 32 transition) = 31.5 (VREF/64) = VREF(63/128) An adjustable voltage follower can be connected to the RC pin or a 2kΩ pot can be connected between VREF+ and VREF- with the wiper connected to RC. Set VlN to the 31 to 32 transition voltage, then adjust the voltage follower or the pot until the transition occurs on the output bits. Although the output drivers are capable of handling typical data bus loading, the capacitor charging currents will produce local ground disturbances. For this reason, an external bus driver is recommended. The Reference Center point can also be used to create unique transfer functions. The user must remember, however, that there is approximately 120Ω in series with the RC pin. Increased Accuracy In most cases the accuracy of the HI3306 should be sufficient without any adjustments. In applications where accuracy is of utmost importance, three adjustments can be made to obtain better accuracy; i.e., offset trim, gain trim, and midpoint trim. Applications 7-Bit Resolution To obtain 7-bit resolution, two HI3306s can be wired together. Necessary ingredients include an open-ended ladder network, an overflow indicator, three-state outputs, and chipenabler controls - all of which are available on the HI3306. Offset Trim In general offset correction can be done in the preamp circuitry by introducing a DC shift to VlN or by the offset trim of the operational amplifier. When this is not possible the VREF- input can be adjusted to produce an offset trim. The theoretical input voltage to produce the first transition is 1/ LSB. The equation is as follows: 2 The first step for connecting a 7-bit circuit is to totem-pole the ladder networks, as illustrated in Figure 17. Since the absolute resistance value of each ladder may vary, external trim of the mid-reference voltage may be required. The overflow output of the lower device now becomes the seventh bit. When it goes high, all counts must come from the upper device. When it goes low, all counts must come from the lower device. This is done simply by connecting the lower overflow signal to the CE1 control of the lower A/D converter and the CE2 control of the upper A/D con- VIN (0 to 1 transition) = 1/2 LSB = 1/2(VREF/64) = VREF/128. If VlN for the first transition is less than the theoretical, then a single-turn 50Ω pot connected between VREF- and 10 HI3306 Signal-to-Noise (SNR) verter. The three-state outputs of the two devices (bits 1 through 6) are now connected in parallel to complete the circuitry. SNR is the measured RMS signal to RMS noise at a specified input and sampling frequency. The noise is the RMS sum of all of the spectral components except the fundamental and the first five harmonics. Doubled Sampling Speed The phase control and both positive and negative true chip enables allow the parallel connection of two HI3306s to double the sampling speed. Figure 18 shows this configuration. One converter samples on the positive phase of the clock, and the second on the negative. The outputs are also alternately enabled. Care should be taken to provide a near square-wave clock it operating at close to the maximum clock speed for the devices. Signal-to-Noise + Distortion Ratio (SINAD) SINAD is the measured RMS signal to RMS sum of all other spectral components below the Nyquist frequency excluding DC. Effective Number of Bits (ENOB) The effective number of bits (ENOB) is derived from the SINAD data. ENOB is calculated from: 8-Bit to 12-Bit Conversion Techniques ENOB = (SINAD - 1.76 + VCORR)/6.02, To obtain 8-bit to 12-bit resolution and accuracy, use a feed- forward conversion technique. Two A/D converters will be needed to convert up to 11 bits; three A/D converters to convert 12 bits. The high speed of the HI3306 allows 12-bit conversions in the 500ns to 900ns range. where: VCORR = 0.5dB. Total Harmonic Distortion (THD) THD is the ratio of the RMS sum of the first 5 harmonic components to the RMS value of the measured input signal. The circuit diagram of a high-speed 12-bit A/D converter is shown in Figure 19. In the feed-forward conversion method two sequential conversions are made. Converter A first does a coarse conversion to 6 bits. The output is applied to a 6-bit D/A converter whose accuracy level is good to 12 bits. The D/A converter output is then subtracted from the input voltage, multiplied by 32, and then converted by a second flash A/D converter, which is connected in a 7-bit configuration. The answers from the first and second conversions are added together with bit 1 of the first conversion overlapping bit 7 of the second conversion. Operating and Handling Considerations HANDLING When using this method, take care that: All inputs and outputs of Intersil CMOS devices have a network for electrostatic protection during handling. Recommended handling practices for CMOS devices are described in AN6525. “Guide to Better Handling and Operation of CMOS Integrated Circuits.” • The linearity of the first converter is better than 1/2 LSB. OPERATING • An offset bias of 1 LSB (1/64) Is subtracted from the first conversion since the second converter is unipolar. Operating Voltage During operation near the maximum supply voltage limit, care should be taken to avoid or suppress power supply turn-on and turn-off transients, power supply ripple, or ground noise; any of these conditions must not cause VDD - VSS to exceed the absolute maximum rating. • The D/A converter and its reference are accurate to the total number of bits desired for the final conversion (the A/D converter need only be accurate to 6 bits). The first converter can be offset-biased by adding a 20Ω resistor at the bottom of the ladder and increasing the reference voltage by 1 LSB. If a 6.4V reference is used in the system, for example, then the first HI3306 will require a 6.5V reference. Input Signals To prevent damage to the input protection circuit, input signals should never be greater than VDD nor less than VSS . Input currents must not exceed 20mA even when the power supply is off. The Zener (pin 4) is the only terminal allowed to exceed VDD . Definitions Dynamic Performance Definitions Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance of the converter. A low distortion sine wave is applied to the input, it is sampled, and the output is stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the dynamic performance of the A/D. The sine wave input to the part is -0.5dB down from full scale for all these tests. Unused Inputs A connection must be provided at every input terminal. All unused input terminals must be connected to either VDD or VSS , whichever is appropriate. Output Short Circuits Shorting of outputs to VDD or VSS may damage CMOS devices by exceeding the maximum device dissipation. 11 HI3306 Application Circuits OF B7 (MSB) B6 V+ B6 B5 B5 OF B4 B4 1kΩ RC VSS DATA OUTPUT 0.1µF HI3306 CLOCK INPUT VZ B3 CE2 B2 B3 B2 (LSB) CE1 B1 B1 V+ VDD CLK VSS 0.2µF 10µF PH VIN VREF + VREF 0.1µF ADJUST POT TO 1/2 VZ B6 B5 OF HI3306 B4 VSS RC 0.1µF VZ V+ CE2 B3 CE1 B2 CLK B1 VDD 0.2µF PH 10µF NOTE: VDD MUST BE ≥ VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ VIN VREF - SIGNAL INPUT VREF + 0.1µF FIGURE 17. TYPICAL HI3306 7-BIT RESOLUTION CONFIGURATION 12 HI3306 Application Circuits (Continued) (MSB) B6 V+ B6 B5 B5 OF B4 B4 RC VSS DATA OUTPUT 0.1µF HI3306 CLOCK INPUT VZ B3 CE2 B2 B3 B2 (LSB) CE1 B1 B1 V+ VDD CLK VSS 0.2µF 10µF PH VIN VREF + VREF 0.1µF ADJUST POT TO 1/2 VZ B6 B5 OF B4 HI3306 VSS RC 0.1µF VZ V+ B3 CE2 B2 CE1 CLK B1 V+ VDD 0.2µF V+ PH 10µF NOTE: VDD MUST BE ≥ VZ FOR CIRCUIT TO WORK WITH VZ CONNECTED TO VREF+ VIN VREF - SIGNAL INPUT VREF + 0.1µF FIGURE 18. TYPICAL HI3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY 13 HI3306 Application Circuits (Continued) BINARY ADDER B12 B6’ NO. 1 6-BIT FLASH ADC S/H, VIN B6 + 0 B5 + 0 B4 + 0 B3 + 0 B2 + 0 B1 + B7 B1’ B6 + ∑ - 6-BIT DAC (12-BIT ACCURACY) X32 B6 NO. 2 6-BIT FLASH ADC B1 B1 B7 NO. 3 6-BIT FLASH ADC B6 B1 CONTROL LOGIC FIGURE 19. TYPICAL HI3306, 800ns, 12-BIT ADC SYSTEM 5V HI3306 VDD VDD HI3306 INPUT TYPICAL FOR: 1kΩ HI3306 CLK 50kΩ 5V HI3306 INPUTS TYPICAL FOR: 0.01µF PHASE CE1 CE2 74LS04 7406 OPEN COLLECTOR DRIVER HI3306 OUTPUTS TYPICAL FOR: HI3306 VDD 5V B1 B2 B3 B4 B5 B6 OF CD74HC 4049 (INV.), OR CD74HC4050 (NON-INV.), OR ANY LOW POWER SCHOTTKY TTL WITH HIGH INPUT VOLTAGE RATING (MANY LS DEVICES ARE RATED TO ACCEPT VOLTAGES UP TO 15V). FIGURE 20. 5V LOGIC INTERFACE CIRCUIT FOR VDD > 5.5V 14 HI3306 Dual-In-Line Plastic Packages (PDIP) E18.3 (JEDEC MS-001-BC ISSUE D) N 18 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - -B-AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M A1 eC C A B S B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 D 0.845 0.880 21.47 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 15 e 0.100 BSC eA 0.300 BSC eB - L 0.115 N 0.204 18 0.355 22.35 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 18 5 6 7 4 9 Rev. 0 12/93 HI3306 Small Outline Plastic Packages (SOIC) M20.3 (JEDEC MS-013-AC ISSUE C) 20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.4961 0.5118 12.60 13.00 3 E 0.2914 0.2992 7.40 7.60 4 e α B S 0.050 BSC 1.27 BSC - H 0.394 0.419 10.00 10.65 - h 0.010 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 N NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. MILLIMETERS α 20 0o 20 8o 0o 7 8o Rev. 0 12/93 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 16