HM62G36256A Series
8M Synchronous Fast Static RAM
(256k-word × 36-bit)
ADE-203-1267A (Z)
Preliminary
Rev. 0.1
Jun. 4, 2001
Description
The HM62G36256A is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized
high speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
•
•
•
•
•
•
•
•
•
•
•
•
2.5 V ± 5% and 3.3 V ± 5% operation
Internal self-timed late write
Byte write control (4 byte write selects, one for each 9-bit)
Optional ×18 configuration
HSTL compatible I/O
Programmable impedance output drivers
User selective input trip-point
Differential, HSTL clock inputs
Asynchronous G output control
Asynchronous sleep mode
Limited set of boundary scan JTAG IEEE 1149.1 compatible
Protocol: Single clock register-register mode
Preliminary: The specification of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specification.
HM62G36256A Series
Ordering Information
Type No.
Access time
Cycle time
Package
HM62G36256ABP-30
HM62G36256ABP-33
HM62G36256ABP-40
1.7 ns
1.7 ns
2.0 ns
3.0 ns
3.3 ns
4.0 ns
119-bump 1. 27 mm
14 mm × 22 mm BGA (BP-119C)
Pin Arrangement
1
2
3
4
5
6
7
A
VDDQ
SA0
SA1
NC
SA13
SA12
VDDQ
B
NC
NC
SA2
NC
SA14
SA11
NC
C
NC
SA3
SA4
VDD
SA5
SA6
NC
D
DQc5
DQc0
VSS
ZQ
VSS
DQb0
DQb5
E
DQc4
DQc3
VSS
SS
VSS
DQb3
DQb4
F
VDDQ
DQc1
VSS
G
VSS
DQb1
VDDQ
G
DQc8
DQc6
SWEc
NC
SWEb
DQb6
DQb8
H
DQc7
DQc2
VSS
NC
VSS
DQb2
DQb7
J
VDDQ
VDD
VREF
VDD
VREF
VDD
VDDQ
K
DQd7
DQd2
VSS
K
VSS
DQa2
DQa7
L
DQd8
DQd6
SWEd
K
SWEa
DQa6
DQa8
M
VDDQ
DQd1
VSS
SWE
VSS
DQa1
VDDQ
N
DQd4
DQd3
VSS
SA8
VSS
DQa3
DQa4
P
DQd5
DQd0
VSS
SA10
VSS
DQa0
DQa5
R
NC
SA7
M1
VDD
M2
SA15
NC
T
NC
NC
SA9
SA16
SA17
NC
ZZ
U
VDDQ
TMS
TDI
TCK
TDO
NC
VDDQ
(Top view)
2
HM62G36256A Series
Pin Description
Name
I/O type
Descriptions
Notes
VDD
Supply
Core power supply
VSS
Supply
Ground
VDDQ
Supply
Output power supply
VREF
Supply
Input reference: provides input reference voltage
K
Input
Clock input. Active high.
K
Input
Clock input. Active low.
SS
Input
Synchronous chip select
SWE
Input
Synchronous write enable
SAn
Input
Synchronous address input
n = 0-17
SWEx
Input
Synchronous byte write enables
x = a, b, c, d
G
Input
Asynchronous output enable
ZZ
Input
Power down mode select
ZQ
Input
Output impedance control
1
DQxn
I/O
Synchronous data input/output
x = a, b, c, d
n = 0, 1, 2...8
M1, M2
Input
Output protocol mode select
TMS
Input
Boundary scan test mode select
TCK
Input
Boundary scan test clock
TDI
Input
Boundary scan test data input
TDO
Output
Boundary scan test data output
NC
—
No connection
M1
M2
Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to V SS via a resistance RQ where 175 Ω ≤ RQ ≤ 300 Ω. If ZQ = VDDQ or
open, output buffer impedance will be maximum.
2. There is 1 protocol with mode pin. For this application, M1 and M2 need to connect to V SS and
VDD, respectively. The state of the Mode control inputs must be set before power-up and must
not change during device operation. Mode control inputs are not standard inputs and may not
meet V IH or VIL specification. This SRAM is tested only in the synchronous register to register
operation.
3
HM62G36256A Series
Row decoder
Block Diagram
A0 to A17
JTAG
register
R-Add
register
18
W-Add
register
MUX
18
18
1
SS
JTAG
register
SWE
JTAG
register
SWEx
K
K
WA
SA
Match
SWEx
register
4
DOC
JTAG
register
D-in
register
JTAG
register
VREF
JTAG
register
ZQ
Impedance
contorol logic
JTAG
register
JTAG tap
controller
TDO
Multiplex
D-out
register
OB
CLK
control
JTAG
register
4
Column decoder
WRC
ZZ
TDI
TCK
TMS
(256k × 36)
SWE
register
4
JTAG
register
G
SS
register
Memory
cell array
36
DQa0-8
DQb0-8
DQc0-8
DQd0-8
HM62G36256A Series
Operation Table
ZZ
SS G
SWE
SWEa SWEb SWEc SWEd K
K
Operation
DQ (n)
DQ (n + 1)
H
×
×
×
×
×
×
×
×
×
sleep mode
High-Z
High-Z
L
H
×
×
×
×
×
×
L-H H-L Dead
(not selected)
×
High-Z
L
×
H
H
×
×
×
×
×
L
L
L
H
×
×
×
×
L-H H-L Read
L
L
×
L
L
L
L
L
L-H H-L Write a, b, c, d High-Z
byte
Din (a,b,c,d)0-8
L
L
×
L
H
L
L
L
L-H H-L Write b, c, d
byte
High-Z
Din (b,c,d)0-8
L
L
×
L
L
H
L
L
L-H H-L Write a, c, d
byte
High-Z
Din (a,c,d)0-8
L
L
×
L
L
L
H
L
L-H H-L Write a, b, d
byte
High-Z
Din (a,b,d)0-8
L
L
×
L
L
L
L
H
L-H H-L Write a, b, c
byte
High-Z
Din (a,b,c)0-8
L
L
×
L
H
H
L
L
L-H H-L Write c, d byte High-Z
Din (c,d)0-8
L
L
×
L
L
H
H
L
L-H H-L Write a, d byte High-Z
Din (a,d)0-8
L
L
×
L
L
L
H
H
L-H H-L Write a, b byte High-Z
Din (a,b)0-8
L
L
×
L
H
L
L
H
L-H H-L Write b, c byte High-Z
Din (b,c)0-8
L
L
×
L
H
H
H
L
L-H H-L Write d byte
High-Z
Din (d)0-8
L
L
×
L
H
H
L
H
L-H H-L Write c byte
High-Z
Din (c)0-8
L
L
×
L
H
L
H
H
L-H H-L Write b byte
High-Z
Din (b)0-8
L
L
×
L
L
H
H
H
L-H H-L Write a byte
High-Z
Din (a)0-8
×
Dead
High-Z
(Dummy read)
×
×
Dout
(a,b,c,d)0-8
Notes: 1. × means don’t care for synchronous inputs, and H or L for asynchronous inputs.
2. SWE, SS, SWEa to SWEd, SA are sampled at the rising edge of K clock.
3. Although differential clock operation is implied, this SRAM will operate properly with one clock
phase (either K or K) tied to V REF. Under such single-ended clock operation, all parameters
specified within this document will be met.
5
HM62G36256A Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Notes
Input voltage on any pin
VIN
–0.5 to VDDQ + 0.5
V
1, 4
Core supply voltage
VDD
–0.5 to 3.9
V
1
Output supply voltage
VDDQ
–0.5 to 2.2
V
1, 4
Operating temperature
TOPR
0 to 70
°C
Storage temperature
TSTG
–55 to 125
°C
Output short–circuit current
I OUT
25
mA
Latch up current
I LI
200
mA
Package junction to case thermal resistance
θJC
2
°C/W
5, 7
Package junction to ball thermal resistance
θJB
5
°C/W
6, 7
Notes: 1. All voltage is referred to VSS .
2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional
operation should be restricted the Operation Conditions. Exposure to higher than recommended
voltages for extended periods of time could affect device reliability.
3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown
in the tables after thermal equilibrium has been established.
4. The following supply voltage application sequence is recommended: V SS , VDD, VDDQ, VREF then
Vin. Remember, according to the Absolute Maximum Ratings table, VDDQ is not exceed 2.2 V,
whatever the instantaneous value of V DDQ.
5. θJC is measured at the center of mold surface in fluorocarbon (See Figure “Definition of
Measurement”).
6. θJB is measured on the center ball pad after removing the ball in fluorocarbon (See Figure
“Definition of Measurement”).
7. These thermal resistance values have error of ± 5°C/W.
θJC
θJB
T.C.
Fluorocarbon
T.C.
Definition of Measurement
6
Fluorocarbon
HM62G36256A Series
Note: The following the DC and AC specifications shown in the Tables, this device is tested under the
minimum transverse air flow exceeding 500 linear feet per minute.
DC Operating Conditions (Ta = 0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage (Core)
VDD
2.38
2.5
2.63
V
2.5 V part
VDD
3.14
3.3
3.47
V
3.3 V part
Supply voltage (I/O)
VDDQ
1.4
—
2.1
V
Input reference voltage (I/O)
VREF
0.65
—
1.0
V
Input high voltage
VIH
VREF + 0.1 —
VDDQ + 0.3
V
Input low voltage
VIL
–0.3
—
VREF – 0.1
V
Clock differential voltage
VDIF
0.1
—
VDDQ + 0.3
V
2, 3
Clock common mode voltage
VCM
0.6
—
0.90
V
3
1
Notes: 1. Peak to peak AC component superimposed on V REF may not exceed 5% of VREF.
2. Minimum differential input voltage required for differential input clock operation.
3. See following figure.
VDDQ
VDIF
VCM
VSS
Differential Voltage/Common Mode Voltage
7
HM62G36256A Series
DC Characteristics (Ta = 0 to 70°C, VDD = 2.5 V ± 5%, 3.3 V ± 5%)
Parameter
Symbol Min
Typ
Max
Unit Notes
Input leakage current
I LI
—
—
2
µA
1
Output leakage current I LO
—
—
5
µA
2
Standby current
—
—
100
mA
3
VDD operating current,
I DD4
excluding output drivers
4 ns cycle
—
—
500
mA
4
VDD operating current,
I DD3
excluding output drivers
3 ns and 3.3 ns cycle
—
—
600
mA
4
Quiescent active power I DD2
supply current
—
—
200
mA
5
Maximum Power
Dissipation,
including output data
—
—
2.3 at 2.5 V part
W
6
—
—
2.8 at 3.3 V part
W
6
I SBZZ
P
Output low voltage
VOL
VSS
—
VSS + 0.4
V
7
Output high voltage
VOH
VDDQ – 0.4
—
VDDQ
V
8
ZQ pin connect
resistance
RQ
—
250
—
Ω
Output low current
I OL
(VDDQ/2)/
[{(RQ/5 – 5 Ω)}-15%]
—
(VDDQ/2)/
[{(RQ/5 – 5Ω)}+15%]
mA
9, 11,
12
Output high current
I OH
(VDDQ/2)/
[{(RQ/5 – 5 Ω)} +15%]
—
(VDDQ/2)/
[{(RQ/5 – 5Ω)}-15%]
mA
10, 11,
12
Notes: 1. 0 ≤ Vin ≤ V DDQ for all input pins (except VREF, ZQ, M1, M2 pin).
2. 0 ≤ Vout ≤ V DDQ, DQ in High-Z.
3. All inputs (except clock) are held at either VIH or VIL, ZZ is held at VIH, Iout = 0 mA. Spec is
guaranteed at 75°C junction temperature.
4. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = minimum cycle.
5. Iout = 0 mA, read 50%/write 50%, VDD = VDD max, VIN = VIH or VIL, Frequency = 3 MHz.
6. Output drives a 12pF load and switches every cycle. This parameter should be used by the
SRAM designer to determine electrical and package requirements for the SRAM device.
7. RQ = 250 Ω, I OL = 8 mA at VDDQ/2 – 0.3 V.
8. RQ = 250 Ω, I OH = –8 mA at VDDQ/2 + 0.3 V.
9. Measured at V OL = 1/2 VDDQ for: 175 Ω ≤ RQ ≤ 300 Ω.
10. Measured at V OH = 1/2 VDDQ for: 175 Ω ≤ RQ ≤ 300 Ω.
11. Parameter tested with RQ = 250 Ω and VDDQ = 1.5 V.
8
HM62G36256A Series
12. Output buffer impedance can be programmed by terminating the ZQ pin to VSS through a
precision resister (RQ). The value of RQ is five times the output impedance desired. The
allowable range of RQ to guarantee impedance matching with a tolerance of 15% is 250 typical.
If the status of ZQ pin is open, output impedance is maximum. Maximum impedance occurs with
ZQ connected to VDDQ. The impedance update of the output driver occurs when the SRAM is in
High-Z. Write and Deselect operations will synchronously switch the SRAM into and out of HighZ, therefore triggering an update. The user may choose to invoke asynchronous G updates by
providing a G setup and hold about the K clock to guarantee the proper update. At power-up,
the output impedance defaults to minimum impedance. It will take 1024 cycles for the
impedance to be completely updated if the programmed impedance is much higher than
minimum impedance. The total external capacitance of ZQ pin must be less than 7.5 pF.
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter
Symbol
Min
Max
Unit
Note
Input capacitance (SAn, SS, SWE, SWEx)
CIN
—
4
pF
1
Input capacitance (K, K, G)
CCLK
—
5
pF
1
Input/Output capacitance (DQxn)
CIO
—
5
pF
1
Note:
1. This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 70°C, VDD = 2.5 V ± 5% and 3.3 V ± 5%)
Test Conditions
•
•
•
•
•
•
•
Input pulse levels (K, K): VDIF = 0.75 V, VCM = 0.75 V
Input timing reference level (K, K): Differential cross point
Input pulse levels (except K, K): VIL = 0.25 V, VIH = 1.25 V
Input and output timing reference levels (except K, K): VREF = 0.75 V
Input rise and fall time: 0.5 ns (10% to 90%)
Output load: See figure
Parameters are tested with RQ = 250 Ω and VDDQ = 1.5 V
16.7 Ω
0.75 V
16.7 Ω
DQ
50 Ω
50 Ω
5 pF
16.7 Ω
50 Ω
50 Ω
0.75 V
5 pF
0.75 V
9
HM62G36256A Series
AC Characteristics (Ta = 0 to 70°C, VDD = 2.5 V ± 5% and 3.3 V ± 5%)
Single Differential Clock Register-Register Mode (M1 = VSS, M2 = VDD )
HM62G36256A
-30
-33
-40
Parameter
Symbol Min
Max
Min
Max
Min
Max
Unit Notes
CK clock cycle time
t KHKH
3.0
—
3.3
—
4.0
—
ns
CK clock high width
t KHKL
1.2
—
1.3
—
1.5
—
ns
CK clock low width
t KLKH
1.2
—
1.3
—
1.5
—
ns
Address setup time
t AVKH
0.5
—
0.5
—
0.5
—
ns
2
Data setup time
t DVKH
0.5
—
0.5
—
0.5
—
ns
2
Address hold time
t KHAX
0.5
—
0.5
—
0.5
—
ns
2
Data hold time
t KHDX
0.5
—
0.5
—
0.5
—
ns
2
Clock high to output valid
t KHQV
—
1.7
—
1.7
—
2.0
ns
1
Clock high to output hold
t KHQX
0.5
—
0.5
—
0.5
—
ns
1, 2
Clock high to output Low-Z
(SS control)
t KHQX2
0.5
—
0.5
—
0.5
—
ns
1, 5
Clock high to output High-Z
t KHQZ
—
2.0
—
2.0
—
2.0
ns
1, 3
Output enable low to output Low-Z
t GLQX
0.5
—
0.5
—
0.5
—
ns
1, 2, 5
Output enable low to output valid
t GLQV
—
1.7
—
1.7
—
2.0
ns
1, 3
Output enable low to output High-Z
t GHQZ
—
1.5
—
1.5
—
1.5
ns
1, 3
Sleep mode recovery time
t ZZR
10.0
—
10.0
—
10.0
—
ns
6
Sleep mode enable time
t ZZE
—
9.0
—
9.0
—
9.0
ns
1, 3, 6
Notes: 1.
2.
3.
4.
See AC Test Loading figure.
Parameter is guaranteed by design.
Transitions are measured at start point of output high impedance from output low impedance.
Output driver impedance update specifications for G induced updates. Write and deselected
cycles will also induce output driver updates during High-Z.
5. Transitions are measured ±50 mV from steady state voltage.
6. When ZZ is switching, clock input K must be at same logic levels for reliable operation.
10
HM62G36256A Series
Timing Waveforms
Read Cycle-1
tKHKL
tKHKH
tKLKH
K
K
tAVKH
SA
A1
tKHAX
A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
A4
SS
SWE
SWEx
tKHQX
DQ
Do 0
Do 1
Do 2
tKHQV
Note: G, ZZ = VIL
11
HM62G36256A Series
Read Cycle-2 (SS Controlled)
tKHKL
tKHKH
tKLKH
K
K
tAVKH
SA
A1
tKHAX
A3
tAVKH
A4
tKHAX
SS
tAVKH
tKHAX
SWE
SWEx
tKHQZ
DQ
Do 0
Do 1
Do 3
tKHQX2
Note: G, ZZ = VIL
12
HM62G36256A Series
Read Cycle-3 (G Controlled)
tKHKL
tKHKH
tKLKH
K
K
tAVKH
SA
A1
tKHAX
A2
A3
tAVKH
tKHAX
tAVKH
tKHAX
A4
SS
SWE
SWEx
G
tGHQZ
DQ
Note: ZZ = VIL
Do 0
tGLQV
Do 1
Do 3
tGLQX
13
HM62G36256A Series
Write Cycle
tKHKL
tKHKH
tKLKH
K
K
tAVKH
SA
A1
tKHAX
A2
tAVKH
tKHAX
tAVKH
tKHAX
tAVKH
tKHAX
tDVKH
tKHDX
A3
A4
Di 2
Di 3
SS
SWE
SWEx
G
DQ
Di 0
Note: ZZ = VIL
14
Di 1
HM62G36256A Series
Read-Write Cycle
READ
READ
(G control)
tKHKL tKLKH
tKHKH
WRITE
READ
tAVKH
tKHAX
DEAD
(SS control)
WRITE
K
K
SA
A1
A3
tAVKH
A4
A6
A7
Do 4
Di 6
tKHAX
SS
tAVKH
tKHAX
tAVKH
tKHAX
SWE
SWEx
G
tGHQZ tDVKH
Do 0
DQ
Do 1
tKHDX
tGLQV
Di 3
tKHQX
tGLQX
tKHQZ
tKHQV
Note: ZZ = VIL
ZZ Control
tKHKL tKLKH
tKHKH
K
K
tAVKH
tKHAX
A1
SA
SS
tAVKH
tKHAX
SWE
SWEx
Sleep off
ZZ
Sleep active
Sleep active
Do 1
DQ
tZZR
tZZE
Note: G = VIL
15
HM62G36256A Series
Boundary Scan Test Access Port Operations
In order to perform the interconnect testing of the modules that include this SRAM, the serial boundary
scan test access port (TAP) is designed to operate in a manner consistent with IEEE Standard 1149.1 1990. But does not implement all of the functions required for 1149.1 compliance The HM62G series
contains a TAP controller. Instruction register, Boundary scans register, Bypass register and ID register.
Test Access Port Pins
Symbol I/O
Name
TCK
Test clock
TMS
Test mode select
TDI
Test data in
TDO
Test data out
Note: This Device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1.
To disable the TAP, TCK must be connected to V SS . TDO should be left unconnected.
To test Boundary scan, ZZ pin need to be kept below V REF – 0.4 V.
TAP DC Operating Conditions (Ta = 0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Boundary scan input high voltage
VIH
2.0
3.6
V
Boundary scan input low voltage
VIL
–0.3
0.8
V
Boundary scan input leakage current
I LI
–2
2
µA
1
Boundary scan output low voltage
VOL
—
0.4
V
2
Boundary scan output high voltage
VOH
2.4
—
V
3
Notes: 1. 0 ≤ Vin ≤ V DD for all logic input pin.
2. I OL = 8 mA at VDD = 3.3 V.
3. I OH = –8 mA at VDD = 3.3 V.
16
Notes
HM62G36256A Series
TAP AC Characteristics (Ta = 0 to 70°C)
Parameter
Symbol
Min
Max
Unit
Test clock cycle time
t THTH
67
—
ns
Test clock high pulse width
t THTL
30
—
ns
Test clock low pulse width
t TLTH
30
—
ns
Test mode select setup
t MVTH
10
—
ns
Test mode select hold
t THMX
10
—
ns
Capture setup
t CS
10
—
ns
1
Capture hold
t CH
10
—
ns
1
TDI valid to TCK high
t DVTH
10
—
ns
TCK high to TDI don’t care
t THDX
10
—
ns
TCK low to TDO unknown
t TLQX
0
—
ns
TCK low to TDO valid
t TLQV
—
20
ns
Note:
Note
1. t CS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture.
TAP Test Conditions (VDD = 3.3 V)
•
•
•
•
•
•
•
Tempreture: 0°C ≤ Ta ≤ 70°C
Input timing measurement reference level: 1.5 V
Input pulse levels: 0 to 3.0 V
Input rise and fall time: 2.0 ns typical (10% to 90%)
Output timing measurement reference level: 1.5 V
Test load termination supply voltage (VT ): 1.5 V
Output Load: See figures
VT = 1.5 V
DUT
50 Ω
Z0 = 50 Ω
TDO
17
HM62G36256A Series
TAP Controller Timing Diagram
tTHTH
tTHTL tTLTH
tMVTH
tTHMX
TCK
TMS
tDVTH
tTHDX
TDI
tTLQV
tTLQX
TDO
tCS
RAM
Address
tCH
Test Access Port Registers
Register name
Length
Symbol
Instruction register
3 bits
IR [0;2]
Bypass register
1 bit
BP
ID register
32 bits
ID [0;31]
Boundary scan register
70 bits
BS [1;70]
18
Note
HM62G36256A Series
TAP Controller Instruction Set
IR2
IR1
IR0
Instruction
Operation
0
0
0
SAMPLE-Z
Tristate all data drivers and capture the pad value
0
0
1
IDCODE
0
1
0
SAMPLE-Z
0
1
1
BYPASS
1
0
0
SAMPLE
1
0
1
BYPASS
1
1
0
BYPASS
1
1
1
BYPASS
Tristate all data drivers and capture the pad value
Note: This Device does not perform EXTEST, INTEST or the preload portion of the PRELOAD command
in IEEE 1149.1.
19
HM62G36256A Series
Boundary Scan Order
Bit No.
Bump ID
Signal name
Bit No.
Bump ID
Signal name
1
5R
M2
36
3B
SA
2
4P
SA
37
2B
NC
3
4T
SA
38
3A
SA
4
6R
SA
39
3C
SA
5
5T
SA
40
2C
SA
6
7T
ZZ
41
2A
SA
7
6P
DQa
42
2D
DQc
8
7P
DQa
43
1D
DQc
9
6N
DQa
44
2E
DQc
10
7N
DQa
45
1E
DQc
11
6M
DQa
46
2F
DQc
12
6L
DQa
47
2G
DQc
13
7L
DQa
48
1G
DQc
14
6K
DQa
49
2H
DQc
15
7K
DQa
50
1H
DQc
16
5L
SWEa
51
3G
SWEc
17
4L
K
52
4D
ZQ
18
4K
K
53
4E
SS
19
4F
G
54
4G
NC
20
5G
SWEb
55
4H
NC
21
7H
DQb
56
4M
SWE
22
6H
DQb
57
3L
SWEd
23
7G
DQb
58
1K
DQd
24
6G
DQb
59
2K
DQd
25
6F
DQb
60
1L
DQd
26
7E
DQb
61
2L
DQd
27
6E
DQb
62
2M
DQd
28
7D
DQb
63
1N
DQd
29
6D
DQb
64
2N
DQd
30
6A
SA
65
1P
DQd
31
6C
SA
66
2P
DQd
32
5C
SA
67
3T
SA
33
5A
SA
68
2R
SA
34
6B
SA
69
4N
SA
35
5B
SA
70
3R
M1
20
HM62G36256A Series
Notes: 1. Bit#1 is the first scan bit to exit the chip.
2. The NC pads listed in this table are indeed no connects, but are represented in the boundary
scan register by a “Place Holder”. Placeholder registers are internally connected to V SS .
3. In Boundary scan mode, differential input K and K are referenced to each other and must be at
opposite logic levels for reliable operation.
4. ZZ must remain at VIL during boundary scan.
5. In boundary scan mode, ZQ must be driven to V DDQ or VSS supply rail to ensure consistent results.
6.
M1 and M2 must be driven to VDD or VSS supply rail to ensure consistent results.
21
HM62G36256A Series
ID register
Part
Revision
Number
(31:28)
Device Density
Vendor Definition
and Configuration (17:12)
(27:18)
Vendor JEDEC Code Smart
(11:1)
Bit (0)
HM62G36256A
0010
0011000100
00000000111
xxxxxx
1
TAP Controller State Diagram
1
0
Test-LogicReset
0
Run-Test/
Idle
1
1
SelectDR-Scan
0
1
1
Capture-DR
Capture-IR
0
0
0
Shift-DR
1
1
Exit1-DR
1
Exit1-IR
0
0
Pause-DR
Pause-IR
0
1
0
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
0
Shift-IR
1
0
1
SelectIR-Scan
0
0
Update-IR
1
0
Note: The value adjacent to each state transition in this figure represents the signal present
at TMS at the time of a rising edge at TCK.
No matter what the original state of the controller, it will enter Test-Logic-Reset when
TMS is held high for at least five rising edges of TCK.
22
HM62G36256A Series
Package Dimensions
HM62G36256ABP Series (BP-119C)
0.20
Unit: mm
4×
0.20 C
0.35 C
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1.27
B
Y
7654321
A
13.88
22.00
14.00
C
1.27
2.02 ± 0.22
0.69 ± 0.08
(0.15)
13.00
119 × φ 0.88 ± 0.06
φ 0.30 M C A B
φ 0.15 M C
Details of the part Y
Hitachi Code
JEDEC
EIAJ
Mass
BP-119C
—
—
1.0 g
23
HM62G36256A Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
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6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
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7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
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Copyright © Hitachi, Ltd., 2001. All rights reserved. Printed in Japan.
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24