HV507 300V, 64-Channel Serial to Parallel Converter with High Voltage Push-Pull Outputs Ordering Information Package Options Device Recommended Operating VPP Max* 80-Lead Plastic Gullwing Die HV507 300V HV507PG HV507X * Please consult factory for higher voltage operation. Features General Description ❏ HVCMOS® technology The HV507 is a low voltage serial to high voltage parallel converter with 64 high voltage push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple high voltage outputs, low current sourcing and sinking capabilities. ❏ Operating output voltage of 300V ❏ Low power level shifting from 5V to 300V ❏ Shift register speed 8MHz @ VDD = 5V The device consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data In and DIOB is Data Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data In and DIOA is Data Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE, BL, or the POL inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low. ❏ 64 latched data outputs ❏ Output polarity and blanking ❏ CMOS compatible inputs ❏ Forward and reverse shifting options Absolute Maximum Ratings1 Supply voltage, VDD -0.5V to +6V Supply voltage, VPP VDD to 320V Logic input levels Ground -0.5V to VDD +0.5V current3 High voltage supply 0.5A current2 Continuous total power dissipation3 Operating temperature range Storage temperature range 0.5A 1200mW 0°C to +70°C -65°C to +150°C Notes: 1. All voltages are referenced to GND. 2. Connection to all power and ground pads is required. Duty cycle is limited by the total power dissipated in the package. 3. For operation above 25°C ambient derate linearly to 70°C at 26.7mW/°C. 12/13/01 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, HV507 Electrical Characteristics (for V DD = 5V, VPP = 300V, TA = 250C) DC Characteristics Symbol Parameter Min Typ VDD supply current IDD Max Units 15 mA Conditions fCLK = 8MHz, fDATA = 4MHz LE = LOW IDDQ Quiescent VDD supply current 200 µA All VIN = 0V or VDD IPP High voltage supply current 0.50 mA VPP = 300V All outputs high 0.50 mA VPP = 300V All outputs low IIH High-level logic input current 10 µA VIH = VDD IIL Low-level logic input current -10 µA VIL = 0V VOH High-level output 265 V VPP = 300V, IHVOUT = -1mA VDD -1V V IDOUT = -100µA HVOUT Data out VOL VOC Low-level output HVOUT 35 V VDD = 5V, IHVOUT = 1mA Data out 1.0 V IDOUT = 100µA VPP +1.5 V IOC = 1mA -30 V IOC = -1mA Max Units 8 MHz HVOUT clamp voltage AC Characteristics1 (For VDD = 5V, VPP = 300V, TA = 25°C) Symbol fCLK Parameter Min Typ Clock frequency tW Clock width high and low 62 ns tSU Data setup time before clock rises 35 ns tH Data hold time after clock rises 30 ns tWLE Width of latch enable pulse 80 ns tDLE LE delay time after rising edge of clock 35 ns tSLE LE setup time before rising edge of clock 40 ns tON, tOFF Time from latch enable to HVOUT Conditions 4 µs CL = 20pF tDHL Delay time clock to data out high to low 125 ns CL = 20pF tDLH Delay time clock to data out low to high 125 ns CL = 20pF tr, tf All logic inputs 5 ns Note: 1. Shift register speed can be as low as DC as long as Data Set-up and Hold Time meet the spec. Recommended Operating Conditions Symbol Parameter Min Typ Max Units 5.0 5.5 V VDD Logic supply voltage 4.5 VPP High voltage supply 60 300 V VIH High-level input voltage VDD -0.9 VDD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature 0 +70 °C Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. 5. The VPP should not drop below VDD or float during operation. Power-down sequence should be the reverse of the above. 2 HV507 Input and Output Equivalent Circuits Switching Waveforms VIH Data In (DIOA/DIOB) 50% Data Valid 50% VIL tSU tH VIH CLK 50% 50% 50% tWL 50% VIL tWH VOH 50% VOL tDLH Data Out (D IOA/D IOB) VOH 50% VOL tDHL LE VIH 50% 50% VOL tDLE tWLE tSLE 90% 10% HV OUT w/ S/R LOW VOH VOL tOFF HV OUT w/ S/R HIGH 10% tON 3 90% VOH VOL HV507 Functional Block Diagram POL VPP BL LE DIOA L/T HVOUT1 CLK L/T HVOUT2 L/T • • • 60 Additional Outputs • • • HVOUT63 L/T HVOUT64 DIR 64-bit Static Shift Register 64 Latches DIOB L/T = Level Translator Function Table Inputs Function Data CLK LE Outputs BL POL DIR Shift Reg HV Outputs 1 2…64 1 2…64 Data Out * All on X X X L L X * *…* H H…H * All off X X X L H X * *…* L L…L * Invert mode X X L H L X * *…* * *…* * Load S/R H or L ↑ L H H X H or L *…* * *…* * Store data in latches X X ↓ H H X * *…* * *…* * X X ↓ H L X * *…* * *…* * Transparent latch mode L ↑ H H H X L *…* L *…* * H ↑ H H H X H *…* H *…* * DIOA ↑ X X X L Qn→ Qn-1 — DIOB DIOB ↑ X X X H Qn→ Qn+1 — DIOA I/O relation Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition, ↓ = high-to-low transition. * = dependent on previous stage’s state before the last CLK or last LE high. 4 HV507 Package Outline Pin Configurations HV507 80 Pin Gullwing Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Function HVOUT 41 HVOUT 42 HVOUT 43 HVOUT 44 HVOUT 45 HVOUT 46 HVOUT 47 HVOUT 48 HVOUT 49 HVOUT 50 HVOUT 51 HVOUT 52 HVOUT 53 HVOUT 54 HVOUT 55 HVOUT 56 HVOUT 57 HVOUT 58 HVOUT 59 HVOUT 60 HVOUT 61 HVOUT 62 HVOUT 63 HVOUT 64 VPP DIOA N/C N/C BL POL VDD DIR GND HVGND N/C N/C CLK LE DIOB VPP Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 41 64 Function HVOUT 1 HVOUT 2 HVOUT 3 HVOUT 4 HVOUT 5 HVOUT 6 HVOUT 7 HVOUT 8 HVOUT 9 HVOUT 10 HVOUT 11 HVOUT 12 HVOUT 13 HVOUT 14 HVOUT 15 HVOUT 16 HVOUT 17 HVOUT 18 HVOUT 19 HVOUT 20 HVOUT 21 HVOUT 22 HVOUT 23 HVOUT 24 HVOUT 25 HVOUT 26 HVOUT 27 HVOUT 28 HVOUT 29 HVOUT 30 HVOUT 31 HVOUT 32 HVOUT 33 HVOUT 34 HVOUT 35 HVOUT 36 HVOUT 37 HVOUT 38 HVOUT 39 HVOUT 40 40 65 Index 25 80 24 1 top view 80-pin Gullwing Package 12/13/010 ©2001 Supertex Inc. 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