HV66 32-Channel LCD Driver with Separate Backplane Output Ordering Information Package Options Device 44 Lead Quad Plastic Gullwing HV66 HV66PG 44 J-Lead Quad Plastic Chip Carrier HV66PJ Die in waffle pack HV66X Features General Description ❏ Processed with HVCMOS® technology Not recommended for new designs. ❏ 32 push-pull CMOS output up to 32V The HV66 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible. ❏ Low power level shifting ❏ Source/sink current minimum 1mA ❏ Shift register speed 5MHz ❏ Latched data outputs ❏ Bidirectional shift register (DIR) ❏ Backplane output Absolute Maximum Ratings1 Supply voltage, VDD2 -0.5V to +7.0V VPP2 -0.5V to +35V Output voltage, Logic input levels2 Ground -0.5V to VDD + 0.5V current3 Continuous total power The device consists of a 32-bit shift register, 32 latches, and control logic to perform blanking and polarity control of the outputs. HVout1 is connected to the first stage of the shift register. Data is shifted through the shift register on the logic rising transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to VDD. A data output buffer is provided for cascading devices. This output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable), BL (blank) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transitions from high to low. The blank signal, BL, when pulled low, will set all outputs to the same state as the BPOUT. If this signal is left open then the BL defaults to a high state. 1.5A dissipation4 Operating temperature range Storage temperature range Lead temperature 1.6mm (1/16 inch) from case for 10 seconds 1200mW -40°C to +85°C -65°C to +125°C 260°C Notes: 1. Device will survive (but operation may not be specified or guaranteed) at these extremes. 2. All voltages are referenced to VSS. 3. Duty cycle is limited by the total power dissipated in the package. 4. For operation above 25°C ambient derate linearly to 85°C at 20mW/°C. 02/96/022 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, 1 refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. HV66 Electrical Characteristics (over recommended operating conditions unless noted) DC Characteristics (VDD = 5V, VPP = 32V, VSS = GND) Symbol Parameter Min IDD VDD supply current 15 mA VDD = VDD max fCLK = 5MHz IPPQ High voltage supply current 0.5 mA Outputs high 0.5 mA Outputs low 0.5 mA All VIN = VSS or VDD IDDQ Quiescent VDD supply current VOH High-level output VOL Low-level output Max Units Conditions Q 22 V IO= 1mA, VPP = 24V Data out 4.6 V IO= -100µA 2 V IO= 1mA 0.4 V IO= 100µA Q Data out IIH High-level logic input current 1 µA VIH = VDD IIL Low-level logic input current -1 µA VIL = 0V VOLBP Low-level output voltage, backplane 3 V IO = 10mA VOHBP High-level output voltage, backplane V IO = -10mA 29 AC Characteristics (VDD = 5V, VPP = 32V, TC = 25°C), logic input rises/fall time = 10ns. Symbol Parameter fCLK Clock frequency tW Clock width high or low tSU Min Max Units 5 MHz Conditions 100 ns Data set-up time before clock rises 25 ns tH Data hold time after clock rises 50 ns tON, tOFF Time from latch enable or POL to HVOUT 500 ns CL = 20pF tON, tOFF Time from POL to BP output 500 ns CL = 20pF tDHL Delay time clock to data high to low 200 ns CL = 10pF tDLH Delay time clock to data low to high 200 ns CL = 10pF tDLE Delay time clock to LE low to high tWLE Width of LE pulse tSLE 50 ns 100 ns LE set-up time before clock rises 50 ns tBR, tBF BPOUT rise/fall time 10 tBR - tBF BPOUT rise and fall difference 1000 µs CL = 350nF 100 µs CL = 350nF Recommended Operating Conditions Symbol Parameter Min Max Units 4.5 5.5 V 0 32 V VDD V V VDD Logic supply voltage VPP Output voltage* VIH High-level input voltage VIL Low-level input voltage 0 0.8 fCLK Clock frequency 0 5 TA Operating free-air temperature -40 +85 °C IOD Allowable current through output diodes 200 mA Notes: *Output will not switch below 12V. Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. Power-down sequence should be the reverse of the above. The VPP should not drop below VDD during operation. 2.4 3. 4. Set all inputs (Data, CLK, Enable, etc.) to a known state. Apply VPP. 2 MHz HV66 Switching Waveforms VIH Data Input 50% Data Valid 50% VIL tH tSU VIH Clock 50% 50% tWL 50% 50% VIL tWH VOH 50% VOL tDLH Data Out VOH 50% VOL tDHL VIH 50% 50% Latch Enable tDLE VOL tWLE tSLE VOH HVOUT w/ S/R LOW 50% VOL tOFF VOH HVOUT w/ S/R HIGH 50% VOL tON POL (ASYNCH w/ Clock) BPOUT 50% 50% tOFF tON 50% 50% 10% VOLBP tBR 3 VOHBP 90% tBF HV66 Functional Block Diagram VPP Polarity Blank Latch Enable VDD Data Input Clock Latch HVOUT1 Latch HVOUT2 32-Bit Shift Register DIR (Outputs 3 to 30 not shown) Latch HVOUT31 Latch HVOUT32 Data Out BPOUT GND Function Table Inputs Function Data CLK LE Outputs BL POL DIR 1 Load S/R Shift Reg 2…32 HV Outputs 1 2…32 Data Out 2…32 BPOUT * H or L ↑ L H H X H or L *…* * *…* * H X H or L L H H X * *…* * *…* * H X H or L L H L X * *…* * *…* * L L ↑ H H H X L *…* H *…* * H H ↑ H H H X H *…* L *…* * H L ↑ H H L X L *…* L *…* * L H ↑ H H L X H *…* H *…* * L X ↑ X H X H Qn → Qn+1 * *…* Q32 X ↑ X H X L Qn → Qn-1 * *…* Q1 Blank X X X L L X * *…* L L…L * L Control X X X L H X * *…* H H…H * H Load latches Transparent Mode R/L Shift Notes: H = high level, L = low level, X = irrelevant, ↑ = low-to-high transition. * = dependent on previous stage’s state before the last CLK or last LE high. 4 HV66 Pin Configuration Package Outline HV66 44 Pin Plastic Gullwing (QFP) Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function Pin Function HVOUT22/11 HVOUT21/12 HVOUT20/13 HVOUT19/14 HVOUT18/15 HVOUT17/16 HVOUT16/17 HVOUT15/18 HVOUT14/19 HVOUT13/20 HVOUT12/21 HVOUT11/22 HVOUT10/23 HVOUT9/24 HVOUT8/25 HVOUT7/26 HVOUT6/27 HVOUT5/28 HVOUT4/29 HVOUT3/30 HVOUT2/31 HVOUT1/32 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Data Out GND N/C BL POL LE VDD Clock DIR Data In VPP BP Out HVOUT32/1 HVOUT31/2 HVOUT30/3 HVOUT29/4 HVOUT28/5 HVOUT27/6 HVOUT26/7 HVOUT25/8 HVOUT24/9 HVOUT23/10 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 top view 44-pin PQFP Package Note: Pin designation for DIR = H/L Example: for DIR = H, Pin 1 is HVOUT 22 for DIR = L, Pin 1 is HVOUT 11 5 HV66 Pin Configuration Package Outline HV66 44 Pin J-Lead Package Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function HVOUT 17/16 HVOUT 16/17 HVOUT 15/18 HVOUT 14/19 HVOUT 13/20 HVOUT 12/21 HVOUT 11/22 HVOUT 10/23 HVOUT 9/24 HVOUT 8/25 HVOUT 7/26 HVOUT 6/27 HVOUT 5/28 HVOUT 4/29 HVOUT 3/30 HVOUT 2/31 HVOUT 1/32 Data Out GND N/C BL POL Pin 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function LE VDD Clock DIR Data In VPP BP Out HVOUT 32/1 HVOUT 31/2 HVOUT 30/3 HVOUT 29/4 HVOUT 28/5 HVOUT 27/6 HVOUT 26/7 HVOUT 25/8 HVOUT 24/9 HVOUT 23/10 HVOUT 22/11 HVOUT 21/12 HVOUT 20/13 HVOUT 19/14 HVOUT 18/15 39 38 37 36 35 34 33 32 31 30 29 40 28 41 27 42 26 43 25 44 24 1 23 2 22 3 21 4 20 5 19 6 18 7 8 9 10 11 12 13 14 15 16 17 top view 44-pin PLCC Note: 1. Pin designation for DIR = H/L Example: for DIR = H, Pin 1 = HVOUT 17 for DIR = L, Pin 1 = HVOUT 16 02/06//02 ©2002 Supertex Inc. All rights reserved. Unauthorized use or reproduction prohibited. 6 1235 Bordeaux Drive, Sunnyvale, CA 94089 TEL: (408) 744-0100 • FAX: (408) 222-4895 www.supertex.com