HV582 HV582 Advance Information 96-Channel AC Plasma Display Data Driver with High Voltage Push-Pull Outputs Features General Description ❑ HVCMOS© technology The HV582 is a low voltage to high voltage converter with 96 high voltage push-pull outputs. This device has been designed to operate as a data driver for AC plasma display panels. ❑ Operating output voltage of 90V ❑ Data clock speed 30MHz @ VDD=5V The device is loaded at up to 30MHz using six parallel data inputs, achieving an effective 180MHz data load rate. A direction pin (DIR) is provided to control the data load sequence. Once data is latched into the output latches, the outputs will be controlled based on the latch contents, polarity (POL) pin and output enable (OE) pin inputs. All outputs may be temporarily forced high by asserting a ‘low’ on the OHB input. Alternatively, all outputs may be temporarily forced low by asserting a ‘low’ on the OLB input. This versatility allows the outputs to be individually controlled, all set high or low, or all set to a highZ state. ❑ Six interleaved inputs and outputs ❑ Data directional loading control ❑ Outputs: enable, polarity, all Hi, all Lo ❑ CMOS compatible inputs Application ❑ AC plasma display data column driver Circuitry assures a break-before-make interval when switching the output transistors, preventing output cross-conduction, thereby increasing power efficiency. Functional Block Diagram 6 HVOUT1 RGB DIN 6 Shift Registers CLK 96-bit Latch Output Control Level Translators and HVOUT Buffers 6 RGB DOUT HVOUT96 LE POL OLB OHB OE 09/16/02 Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website. 1 HV582 Absolute Maximum Ratings* Ordering Info Supply Voltage, VDD -0.5V to 6V Supply Voltage, VPP VDD to 100V Logic input levels Device -0.5V to VDD+0.5V Ground current TBD A High voltage supply current TBD A Continuous total power dissipation Operating temperature range Storage temperature range Recommended Operating VPP Max Package Options 90V HV582X HV582 Die * Contact Factory TBD mW -40°C to +85°C -65°C +150°C * All voltages are referenced to device ground. Notes: Power-up sequence should be the following: 1. Connect ground. 2. Apply VDD. 3. Set all inputs (Data, CLK, Enable, etc.) to a known state. 4. Apply VPP. Power-down sequence should be the reverse of the above. DC Electrical Characteristics (Over operating supply voltages unless otherwise noted) Symbol Parameter Min Typ Max Units Conditions IDD VDD supply current 25 mA fCLK=30MHz, LE*=LOW IDDQ Quiescent VDD supply current 100 µA All VIN=0V or VDD IPP High voltage supply current TBD mA VPP=90V, all outputs high IIH High-level logic input current 1.0 µA VIH=VDD IIL -1.0 µA VIL=0V VOH Low-level logic input current Pull-down resistance (DIR, POL, [not]OE, OH, OL) HVOUT High-level output VOL Low-level output VOC HVOUT clamp voltage IOH Output source current RIN VPP=90V, all outputs low TBD Data out VPP-10 V VDD-1 HVOUT 10 Data out 1.0 V V 100 mA 2 VPP =90V, IHVOUT=-75mA IDOUT=-4.0mA VDD =5.0V, IHVOUT=75mA IDOUT=-4.0mA IOH=75mA IOL=-75mA VPP=100V HV582 AC Electrical Characteristics (Over operating supply voltages unless otherwise noted) Symbol Parameter Min Typ Max Units 30 MHz fCLK Clock frequency tW Clock width high and low 16.5 tSU Data setup time before clock rises 5.0 ns tH Data hold time after clock rises 15 ns tDO Delay time for Data Out tWLE Width of latch enable pulse 15 ns tDLE LE delay time after rising edge of clock 15 ns tSLE LE setup time before rising edge of clock 15 tD Delay time for output to start rise/fall Conditions ns 25 ns CL=20pF ns TBD ns tR Output rise time, 10% to 90% 200 ns CL=170pF, VPP=80V tF Output fall time, 90% to 10% 200 ns CL=170pF, VDD=4.5V tDPOL Delay time for 10% output change from POL TBD ns Delay time for 10% output change from HI-Z TBD ns 5.0 ns tDHIZ Logic input rise/fall time Operating Supply Voltages Symbol Parameter Min Typ Max Units 5.0 5.5 V 90 V VDD Logic supply voltage, VDD 4.5 VPP High voltage supply, VPP 60 VIH High-level input voltage VDD – VDD V VIL Low-level input voltage 0 0.9 V TA Operating free-air temperature -40 +85 °C 0.9 Input and Output Equivalent Circuits VDD VDD VPP Data Out Input GND GND Logic Inputs HVOUT GND Logic Data Output 3 High Voltage Outputs HV582 Switching Waveforms DIN tSU tH tWH tWL CLK tDO DOUT tDLE tSLE tWLE LE tD HVOUT tR/tF Note: Waveform levels are arbitrary and subject to change. 4 HV582 Functional Block Diagram VDD GND DRinA DRoutA DGinA DGoutA DBinA DBoutA DRinB DRoutB DGinB DGoutB DBinB CLK DBoutB VPP D1 16 bit shirt register D91 LD1 Decoder D2 HVout1 Level Xlator 16 bit shirt register D92 HVGND D3 16 bit shirt register D93 96 bit latch D4 16 bit shirt register D94 D5 16 bit shirt register D95 VPP D6 16 bit shirt register D96 Decoder LD96 HVout96 Level Xlator LE POL OLB OHB OE HVGND Function Table Input Outputs Data CLK LE OE POL OLB OHB Shift Reg 1 2...16 HV Outputs 1 2...6 Data Out All low X X X H X L X * *…* L L…L * All high X X X H X H L * *…* H H…H * Outputs Hi-Z X X X L X X X * *…* Z Z…Z * Invert mode X X L H H H H * *…* * *…* (b) * Load S/R H or L ➔ L H L H H H or L *…* * *…* * Store Data in latches X X L H H * *…* * *…* * X X ➔ ➔ H H H H H * *…* * *…* (b) * Transparent Mode L ➔ ➔ Function H H L H H L *…* L *…* * H H L H H H *…* H *…* * H DIR is direction control: L shifts in CCW direction, QN➔QN-1; H shifts in CW direction, QN➔QN+1 H = high level, L = low level, X = irrelevant, ➔ Notes: = low-to-high transition, (b) indicates inversion * = dependent on previous stage’s state before the last CLK or last LE high. 5 HV582 Pad Coordinates Pin Function Coord Pin Function Coord Pin Function Coord 1 VDD -2052, -3892 49 HVOUT54 -2066, +2965 97 HVOUT20 +2121, -140 2 HVGND -2052, -3692 50 HVOUT53 -2066, +3100 98 HVOUT19 +2121, -275 3 HVGND -2052, -3492 51 HVOUT52 -2066, +3235 99 HVOUT18 +2121, -410 4 VPP -2051, -3293 52 HVOUT51 -2066, +3370 100 HVOUT17 +2121, -545 5 VPP -2051, -3093 53 HVOUT50 -2066, +3505 101 HVOUT16 +2121, -680 6 VPP -2051, -2893 54 HVOUT49 -2066, +3640 102 HVOUT15 +2121, -815 7 HVOUT96 -2066, -2705 55 VPP -2052, +3828 103 HVOUT14 +2121, -950 8 HVOUT95 -2066, -2570 56 VPP -2052, +4028 104 HVOUT13 +2121, -1085 9 HVOUT94 -2066, -2435 57 VPP -1728, +4028 105 HVOUT12 +2121, -1220 10 HVOUT93 -2066, -2300 58 VPP -1403, +4028 106 HVOUT11 +2121, -1355 11 HVOUT92 -2066, -2165 59 HVGND -832, +3884 107 HVOUT10 +2121, -1490 12 HVOUT91 -2066, -2030 60 HVGND -632, +3884 108 HVOUT09 +2121, -1625 13 HVOUT90 -2066, -1895 61 HVGND -79, +3884 109 HVOUT08 +2121, -1760 14 HVOUT89 -2066, -1760 62 HVGND +121, +3884 110 HVOUT07 +2121, -1895 15 HVOUT88 -2066, -1625 63 HVGND +686, +3884 111 HVOUT06 +2121, -2030 16 HVOUT87 -2066, -1490 64 HVGND +886, +3884 112 HVOUT05 +2121, -2165 17 HVOUT86 -2066, -1355 65 VPP +1457, +4028 113 HVOUT04 +2121, -2300 18 HVOUT85 -2066, -1220 66 VPP +1782, +4028 114 HVOUT03 +2121, -2435 19 HVOUT84 -2066, -1085 67 VPP +2106, +4028 115 HVOUT02 +2121, -2570 +2121, -2705 20 HVOUT83 -2066, -950 68 VPP +2106, +3828 116 HVOUT01 21 HVOUT82 -2066, -815 69 HVOUT48 +2121, +3640 117 VPP +2106, -2893 22 HVOUT81 -2066, -680 70 HVOUT47 +2121, +3505 118 VPP +2106, -3093 23 HVOUT80 -2066, -545 71 HVOUT46 +2121, +3370 119 VPP +2106, -3293 24 HVOUT79 -2066, -410 72 HVOUT45 +2121, +3235 120 HVGND +2106, -3492 25 HVOUT78 -2066, -275 73 HVOUT44 +2121, +3100 121 HVGND +2106, -3692 26 HVOUT77 -2066, -140 74 HVOUT43 +2121, +2965 122 GND +2106, -3892 27 HVOUT76 -2066, -5 75 HVOUT42 +2121, +2830 123 DRINA +1650, -4087 28 HVOUT75 -2066, +130 76 HVOUT41 +2121, +2695 124 DGINA +1505, -4087 29 HVOUT74 -2066, +265 77 HVOUT40 +2121, +2560 125 DBINA +1360, -4087 30 HVOUT73 -2066, +400 78 HVOUT39 +2121, +2425 126 DRINB +1215, -4087 +1070, -4087 31 HVOUT72 -2066, +535 79 HVOUT38 +2121, +2290 127 DGINB 32 HVOUT71 -2066, +670 80 HVOUT37 +2121, +2155 128 DBINB +925, -4087 33 HVOUT70 -2066, +805 81 HVOUT36 +2121, +2020 129 CLK +780, -4087 34 HVOUT69 -2066, +940 82 HVOUT35 +2121, +1885 130 LE +635, -4087 35 HVOUT68 -2066, +1075 83 HVOUT34 +2121, +1750 131 RESET +490, -4087 36 HVOUT67 -2066, +1210 84 HVOUT33 +2121, +1615 132 GND +300, -4086 37 HVOUT66 -2066, +1345 85 HVOUT32 +2121, +1480 133 DIR +110, -4085 38 HVOUT65 -2066, +1480 86 HVOUT31 +2121, +1345 134 VDD -80, -4086 39 HVOUT64 -2066, +1615 87 HVOUT30 +2121, +1210 135 OHB -270, -4087 40 HVOUT63 -2066, +1750 88 HVOUT29 +2121, +1075 136 OLB -415, -4087 41 HVOUT62 -2066, +1885 89 HVOUT28 +2121, +940 137 OE -560, -4087 42 HVOUT61 -2066, +2020 90 HVOUT27 +2121, +805 138 POL -705, -4087 43 HVOUT60 -2066, +2155 91 HVOUT26 +2121, +670 139 DROUTA -850, -4087 44 HVOUT59 -2066, +2290 92 HVOUT25 +2121, +535 140 DGOUTA -995, -4087 45 HVOUT58 -2066, +2425 93 HVOUT24 +2121, +400 141 DBOUTA -1140, -4087 46 HVOUT57 -2066, +2560 94 HVOUT23 +2121, +265 142 DROUTB -1285, -4087 47 HVOUT56 -2066, +2695 95 HVOUT22 +2121, +130 143 DGOUTB -1430, -4087 48 HVOUT55 -2066, +2830 96 HVOUT21 +2121, -5 144 DBOUTB -1575, -4087 6 HV582 Pad Layout 61 62 57 58 56 59 60 65 66 67 63 64 55 68 54 69 53 70 52 71 51 72 50 73 49 74 48 75 47 76 46 77 45 78 44 79 43 80 42 81 41 82 40 83 39 84 38 85 37 86 36 87 35 88 34 89 33 90 32 91 31 92 HV582 30 93 29 94 28 95 27 96 26 97 25 98 24 99 23 100 22 101 21 102 20 103 19 104 18 105 17 106 16 107 15 108 14 109 13 110 12 111 11 112 10 113 9 114 8 115 7 116 6 117 5 118 4 119 3 120 2 121 1 122 143 144 141 142 139 140 137 138 135 136 133 134 7 131 132 129 130 127 128 125 126 123 124 HV582 Pin List Name Function Description CLK Shift register clock Rising edge triggered LE Transparent latch enable input L = Hold data, H = Transparent RESET Power on reset 1 = Resets all shift registers and latches to Low DIR Shift register direction input L = CCW, Q96->Q1; H = CW, Q1->Q96 POL Polarity input Invert output of latches OE High impedance control L = HV output in Hi-Z state, H = normal OLB All outputs low Active low OHB All outputs high Active low DRINA, DRINB, DGINA, DGINB, DBINA, DBINB Red/green/blue A/B input/output DIR = 0 "input", DIR = 1 "output" DROUTA, DROUTB, DGOUTA, DGOUTB, DBOUTA, DBOUTB Red/green/blue A/B output/input DIR = 0 "output", DIR = 1 "input" HVOUT1-96 High voltage outputs GND Logic ground VDD Logic power HVGND High voltage ground VPP High voltage power 09/16/02rev.2 ©2002 Supertex Inc. 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