HY512260 128Kx16, CMOS DRAM with /2CAS DESCRIPTION This family is a 2M bit dynamic RAM organized 131,072 x 16-bit configuration with CMOS DRAMs. The circuit and process design allow this device to achieve high performance and low power dissipation. Independent read and write of upper and lower byte is controlled by 2 separate CAS inputs. Optional features are access time(50, 60 or 70ns) and power onsumption (Normal or Low power with self refresh). Hyundai’s advanced circuit design and process technology allow this device to achieve high bandwidth, low power consumption and high reliability. FEATURES Ÿ Fast page mode operation Ÿ Read-modify-write Capability Ÿ 2/CAS inputs for upper and lower byte control Ÿ TTL compatible inputs and outputs Ÿ /CAS-before-/RAS, /RAS-only, Hidden and Self refresh capability Ÿ JEDEC standard pinout Ÿ 40-pin Plastic SOJ (400mil) Ÿ Single power supply of 5V ± 10% Ÿ Early Write or output enable controlled write Ÿ Max. Active power dissipation Ÿ Fast access time and cycle time Speed Power Speed tRAC tCAC tPC 50 605mW 50 50ns 15ns 35ns 60 550mW 60 60ns 15ns 40ns 70 495mW 70 70ns 20ns 45ns Ÿ Refresh cycle Part number Refresh Normal SL-part HY512260 512 8ms 128ms ORDERING INFORMATION Part Name Refresh Power Package HY512260JC 512 40Pin SOJ HY512260LJC 512 L-part 40Pin SOJ HY512260SLJC 512 SL-part 40Pin SOJ *SL : Low power with self refresh This document is a general product description and is subject to change without notice. Hyundai electronics does not assume any responsibility for use of circuits described. No patent licences are implied Hyundai Semiconductor Rev.10 / Jan.97 1 HY512260 FUNCTIONAL BLOCK DIAGRAM DQ0 ~ DQ15 8 8 8 Data Input Buffer 8 Data Output Buffer OE DQ0~7 DQ8~15 DQ0~7 DQ8~15 8 8 8 8 WE LCAS UCAS CAS Clock Generator 16 Cloumn Predecoder (8) A0 A1 8 CAS Clock Generator A3 A4 A5 A6 Address Buffer A2 Sense Amp I/O Gate Column Controller Refresh Counter (9) Row Decoder A7 A8 RAS Memory Array 131,077 x 16 9 Row Predecoder (9) RAS Clock Generator Substrate Bias Generator 128Kx16,FP DRAM Rev.10 / Jan.97 2 VCC VSS HY512260 PIN CONFIGURATION (Marking Side) VCC DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 N.C N.C WE RAS N.C A0 A1 A2 A3 Vcc 44 43 42 41 40 39 38 37 36 35 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 21 22 VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A8 A7 A6 A5 A4 Vss 40 Pin Plastic SOJ (400mil) PIN DESCRIPTION Pin Name Parameter /RAS Row Address Strobe /CAS Column Address Strobe /WE Write Enable /OE Output Enable A0~A8 Address Input DQ0~DQ15 Data In/Out Vcc Power (5V) Vss Ground 128Kx16,FP DRAM Rev.10 / Jan.97 3 HY512260 ABSOLUTE MAXIMUM RATING Symbol Parameter Rating Unit TA Ambient Temperature 0 to 70 °C TSTG Storage Temperature -55 to 150 °C VIN, VOUT Voltage on Any Pin relative to VSS -1.0 to 7.0 V VCC Voltage on VCC relative to VSS -1.0 to 7.0 V IOS Short Circuit Output Current 50 mA PD Power Dissipation 1 W TSOLDER Soldering Temperature Ÿ Time 260 Ÿ 10 °C Ÿ sec Note : Operation at or above Absolute Maximum Ratings can adversely affect device reliability RECOMMENDED DC OPERATING CONDITIONS (TA = 0°C to 70°C ) Symbol Parameter Min Typ Max UNIT VCC Power Supply Voltage 4.5 5.0 5.5 V VIH Input High Voltage 2.4 - VCC+1.0 V VIL Input Low Voltage -1.0 - 0.8 V Note : All voltages are referenced to VSS. DC OPERATING CHARACTERISTIC Symbol Parameter Test condition Min Max Unit ILI Input Leakage Current (Any input) VSS ≤ VIN ≤ VCC + 1.0 All other pins not under test = VSS -10 10 µA ILO Output Leakage Current (Any input) VSS ≤ VOUT ≤ VCC /RAS & /CAS at VIH -10 10 µA VOL Output Low Voltage IOL = 4.2mA - 0.4 V VOH Output High Voltage IOH = -5.0mA 2.4 - V 128Kx16,FP DRAM Rev.10 / Jan.97 4 HY512260 DC CHARACTERISTICS (TA = 0°C to 70°C , VCC = 5V ± 10%, VSS = 0V, unless otherwise noted.) Symbol Parameter Test condition Speed Max. Unit 50 60 70 110 100 90 mA 2 mA ICC1 Operating Current /RAS, /CAS Cycling tRC = tRC(min.) ICC2 TTL Standby Current /RAS, /CAS ≥ VIH(min) Other inputs ≥ VSS ICC3 /RAS-only Refresh Current /RAS Cycling,/CAS = VIH tRC = tRC(min.) 50 60 70 110 100 90 mA ICC4 Fast Page mode Current /CAS Cycling, /RAS = VIL tPC = tPC(min.) 50 60 70 80 70 60 mA ICC5 CMOS Standby Current /RAS = /CAS ≥ VCC - 0.2V L-part 1 200 mA µA ICC6 /CAS-before-/RAS Refresh Current /RAS & /CAS = 0.2V tRC = tRC(min.) 50 60 70 100 100 90 mA ICC7 Battery Back-up Current (SL-part) tRC=125µs /CAS = CBR cycling or 0.2V /OE & /WE = VCC - 0.2V Address = Vcc-0.2V or 0.2V DQ0~DQ15 = Vcc-0.2, 0.2V or Open tRAS ≤ 1µs 400 µA Self Refresh Current (SL-part) /RAS & /CAS = 0.2V Other pins are same as ICC7 400 µA ICC8 Note 1. ICC1, ICC3, ICC4 and ICC6 depend on output loading and cycle rates(tRC and tPC). 2. Specified values are obtained with output unloaded. 3. ICC is specified as an average current. In ICC1, ICC3, ICC6, address can be changed only once while /RAS=VIL. In ICC4, address can be changed maximum once while /CAS=VIH within one Fast Page mode cycle time tPC. 4. Only tRAS(max) = 1µs is applied to refresh of battery backup but tRAS(max) = 10µs is to applied to normal functional operation. 5. Icc5(max.), Icc7 and Icc8 are applied to L-part only. 6. Operating condition for 50ns part is Vcc=5V¡ ¾5%,Cout 30pF. 128Kx16,FP DRAM Rev.10 / Jan.97 5 HY512260 AC CHARACTERISTICS (TA = 0 °C to 70 °C, VCC = 5V ± 10% , VSS = 0V, unless otherwise noted.) 60ns 50ns Symbol 70ns Parameter Unit Min Max Min Max Min Max Note tRC Random read or write cycle time 90 - 110 - 130 - ns tRWC Read-modify-write cycle time 130 - 155 - 185 - ns tPC Fast Page mode cycle time 35 - 40 - 45 - ns tPRWC Fast Page mode read-modify-write cycle time 75 - 80 - 95 - ns tRAC Access time from /RAS - 50 - 60 - 70 ns 4,9,10 tCAC Access time from /CAS - 15 - 15 - 20 ns 4,9 tAA Access time from column address - 25 - 30 - 35 ns 4,10 tCPA Access time from /CAS precharge - 30 - 35 - 40 ns 4,15 tCLZ /CAS to output low impedance 0 - 0 - 0 - ns 4 tT Transition time(rise and fall) 3 50 3 50 3 50 ns 3 tRP /RAS precharge time 30 - 40 - 50 - ns tRAS /RAS pulse width 50 10K 60 10K 70 10K ns tRASP /RAS pulse width(Fast Page mode) 50 100K 60 100K 70 100K ns tRSH /RAS hold time 15 - 15 - 20 - ns tCSH /CAS hold time 50 - 60 - 70 - ns tCAS /CAS pulse width 15 10K 15 10K 20 10K ns tRCD /RAS to /CAS delay time 15 35 20 45 20 50 ns 9 tRAD /RAS to column address delay time 10 25 15 30 15 35 ns 10 tCRP /CAS to /RAS precharge time 5 - 5 - 5 - ns tCP /CAS precharge time 10 - 10 - 10 - ns tASR Row address set-up time 0 - 0 - 0 - ns tRAH Row address hold time 8 - 10 - 10 - ns tASC Column address set-up time 0 - 0 - 0 - ns tCAH Column address hold time 15 - 15 - 15 - ns tAR Column address hold time from /CAS 40 - 50 - 55 - ns tRAL Column address to /RAS lead time 25 - 30 - 35 - ns tRCS Read command set-up time 0 - 0 - 0 - ns tRCH Read command hold time referenced to /CAS 0 - 0 - 0 - ns 6 tRRH Read command hold time referenced to /RAS 0 - 0 - 0 - ns 6 tWCH Write command hold time 10 - 10 - 15 - ns tWCR Write command hold time from /RAS 40 - 45 - 55 - ns tWP Write command pulse width 10 - 10 - 15 - ns tRWL Write command to /RAS lead time 15 - 15 - 20 - ns 128Kx16,FP DRAM Rev.10 / Jan.97 6 14 HY512260 AC CHARACTERISTICS Continued 60ns 50ns Symbol 70ns Parameter Unit Min Max Min Max Min Max Note tCWL Write command to /CAS lead time 15 - 15 - 20 - ns tDS Data-in set-up time 0 - 0 - 0 - ns 7 tDH Data-in hold time 15 - 15 - 15 - ns 7 tDHR Data-in hold time Referenced to /RAS 40 - 50 - 55 - ns Refresh period(512 cycles) - 8 - 8 - 8 ms 11 Refresh period(SL-part) - 128 - 128 - 128 ms 11 tWCS Write command set-up time 0 - 0 - 0 - ns 8 tCWD /CAS to /WE delay time 35 - 40 - 50 - ns 8 tRWD /RAS to /WE delay time 70 - 85 - 100 - ns 8 tAWD Column address to /WE delay time 45 - 55 - 65 - ns 8 tCSR /CAS set-up time(CBR cycle) 5 - 5 - 5 - ns tCHR /CAS hold time(CBR cycle) 10 - 10 - 10 - ns tRPC /RAS to /CAS precharge time 5 - 5 - 5 - ns tCPT /CAS precharge time(CBR counter test) 20 - 20 - 25 - ns tROH /RAS hold time referenced to /OE 0 - 0 - 0 - ns tOEA /OE access time - 15 - 15 - 20 ns tOED /OE to data delay 15 - 15 - 20 - ns tOEZ Output buffer turn-off delay time from /OE 0 15 0 15 0 20 ns tOEH /OE command hold time 15 - 15 - 20 - ns tCPWD /WE delay time from /CAS precharge 50 - 55 - 65 - ns tRHCP /RAS hold time from /CAS precharge 35 - 35 - 40 - ns tRASS /RAS pulse width(self refresh) 100 - 100 - 100 - ns tRPS /RAS Precharge Time (Self refresh) 120 - 130 - 150 - ns tCHS /CAS Hold Time (Self refresh) -50 - -50 - -50 - ns tREF 128Kx16,FP DRAM Rev.10 / Jan.97 7 5 8 HY512260 NOTE 1. An initial pause of 200µs is required after power-up followed by 8 /RAS only refresh cycles before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CBR refresh cycles instead of 8 /RAS-only refresh cycles are required. 2. If /RAS=Vss during power-up,the HY512264 could begin an active cycle. This condition results in higher current than necessary current which is demanded from the power supply during power-up. It is recommended that /RAS and /CAS track with Vcc during power-up or be held at a valid VIH in other to minimize the power-up current. 3. VIH(min.) and VIL(max.) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min.) and VIL(max.),and are assumed to be 2ns for all inputs. 4. Measured at VOH=2.0V and VOL=0.8V with a load equivalent to 2TTL loads and 30pF. 5. tCEZ(max.) and tOEZ define the time at which the output achieves the open circuit conditions and is not referenced to output voltage levels. 6. Either tRCD or tRRH must be satisfied for a read cycle. 7 These parameters are referenced to /LCAS or /UCAS leading edge in early write cycles and to /WE leading edge in read-modify-write cycles 8. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(min.), the cycle is an early write cycle and data out pin will remain open circuit (high impedance) through the entire cycle. If tRWD ≥ tRWD(min.), tCWD ≥ tCWD(min.), tAWD ≥ tAWD(min), and tCPWD ≥ tCPWD(min.), the cycle is a read-modify-write cycle and data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 9. Operation within the tRCD(max.) limit ensures that tRAC(max.) can be met. tRCD(max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(max.) limit, then access time is controlled by tCAC. 10.Operation within the tRAD(max.) limit ensures that tRAC(max.) can be met. tRAD(max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(max.) limit, then access time is controlled by tAA. 11.tREF(max.)=128ms is aren;t to L-parts and SL-parts. 12.A burst of 512 CBR refresh cycles must be executed within 8ms (128ms for SL-part) after exiting self refresh. 13.When both /LCAS and /UCAS go low at the same time, all 16-bits data are written into the device. /LCAS and /UCAS must be transited simultaneously withen a same read or write cycle. 14.These parameters are determined by the earlier falling edge of /LCAS and /UCAS. 15.These parameters are determined by the later rising edge of /LCAS or /UCAS. 16.tCWL must be satisfied by both /LCAS and /UCAS for 16-bits access cycles. 17.tCP and tCPT are measured when both /LCAS and /UCAS are high state. 18.Operating condition for 50ns part is Vcc=5V¡ ¾5%, Cout=30pF. CAPACITANCE (TA = 25°C, VCC = 5V ± 10%, VSS = 0V and f=1MHz, unless otherwise noted.) Symbol Parameter Typ. Max Unit CIN1 Input Capacitance (A0~A8) - 5 pF CIN2 Input Capacitance (/RAS, /LCAS,/UCAS, /WE, /OE) - 7 pF CDQ Data Input / Output Capacitance (DQ0~DQ15) - 7 pF 128Kx16,FP DRAM Rev.10 / Jan.97 8