HYNIX HY64LD16162M-I

HY64LD16162M Series
Document Title
1M x 16 bit Low Low Power 1T/1C Pseudo SRAM
Revision history
Revision No. History
Draft Date
Remark
1.0
Initial
Jan. 04. ’ 01
Preliminary
1.1
Revised
Jul. 03. ’ 01
Preliminary
Jul.18. ’ 01
Preliminary
Oct. 07. ‘ 01
Preliminary
Nov. 14. ’ 01
Preliminary
Dec. 20. ‘ 01
Preliminary
Feb. 27. ‘ 02
Preliminary
Mar. 11. ‘ 02
Final
- Change Pin Connection
- Improve tOE from 45ns to 30ns
- Correct State Diagram
1.2
Revised
- Correct Package Dimension
- Change Absolute Maximum Ratings
1.3
Revised
- DC Electrical Characteristics ( IDPD,ICC1)
- State Diagram
- Power Up Sequence
- Deep Power Down Sequence
- Read/Write Cycle Note
1.4
Revised
- DC Electrical Characteristics ( ICC1: 3mA - > 5mA)
1.5
Revised
- Improve Standby Current ISB1 from 100uA to 80uA
- Power Up Sequence
1.6
Revised
- Improve ISB1 80uA to 75uA
- Improve ICC2 30mA to 20mA
- Improve Ambient Temperature C/E to E/I
(0°C~85°C/-25°C~85°C → -25°C~85°C/-40°C~85°C)
- Improve Maximum Absolute Ratings
(Vdd : -0.3V to 3.3V → -0.3V to 3.6V)
- Improve tOE 30ns to 20ns
1.7
Revised
- Pin Description
- Power Up & Deep Power Down Exit Sequence
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.7
March. 2002
1
HY64LD16162M Series
1M x 16 bit Low Low Power 1T/1C SRAM
DESCRIPTION
FEATURES
The HY64LD16162M is a 16Mbit 1T/1C SRAM
featured by high-speed operation and super low
power consumption. The HY64LD16162M adopts
one transistor memory cell and is organized as
1,048,576 words by 16bits. The HY64LD16162M
operates in the extended range of temperature and
supports a wide operating voltage range. The
HY64LD16162M also supports the deep power
down mode for a super low standby current. The
HY64LD16162M delivers the high-density low
power SRAM capability to the high-speed low power
system.
• CMOS Process Technology
• 1M x 16 bit Organization
• TTL compatible and Tri-state outputs
• Deep Power Down : Memory cell data hold invalid
• Standard pin configuration : 48-FBGA
• Data mask function by /LB, /UB
PRODUCT FAMILY
Power Dissipation
Product No.
Voltage
[V]
Mode
HY64LD16162M-DF85E
HY64LD16162M-DF85I
2.3~2.7
2.3~2.7
1CS with /UB,/LB:tCS1
1CS with /UB,/LB:tCS1
(ISB1,Max) (IDPD,Max) (ICC2,Max)
75µA
2µA
20mA
75µA
2µA
20mA
Speed
tRC[ns]
Temp.
[°C]
85
85
-25~85
-40~85
Note 1. tCS - /UB,/LB=High : Chip Deselect.
PIN CONNECTION (Top View)
/OE
A0
A1
A2
ROW
DECODER
CS2
A0
IO10 IO11
A5
A6
IO2
IO3
Vss
IO12
A17
A7
IO4
Vdd
Vdd
IO13 DNU
A16
IO5
Vss
A19
IO15 IO14
A14
A15
IO6
IO7
IO16
A19
A12
A13
/WE
IO8
A18
A8
A9
A10
A11
NC
/CS1
CS2
/WE
/OE
/LB
/UB
MEMORY ARRAY
1,024K x 16
IO8
DATA I/O
BUFFER
IO1
WRITE DRIVER
/CS1
BLOCK
DECODER
A4
PRE DECODER
A3
ADD INPUT
BUFFER
/UB
COLUMN
DECODER
IO9
IO1
SENSE AMP
/LB
BLOCK DIAGRAM
IO9
IO16
CONTROL
LOGIC
PIN DESCRIPTION
Pin Name
/CS1
CS2
/WE
/LB
/UB
DNU
NC
Pin Function
Chip Select
Deep Power Down
Write Enable
Lower Byte(IO1~IO8)
Upper Byte(IO9~IO16)
Do Not Use
No Connection
Pin Name
/OE
IO1~IO8
IO9~IO16
A0~A19
Vdd
Vss
Pin Function
Output Enable
Lower Data Inputs/Outputs
Upper Data Inputs/Outputs
Address Inputs
Power(2.3V~2.7V)
Ground
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Revision 1.7
March. 2002
2
HY64LD16162M Series
ORDERING INFORMATION
Part Number
Speed
HY64LD16162M-E
85
HY64LD16162M-I
85
Note
1. E : Extended Temp. (-25°C ~ 85°C)
2. I : Industrial Temp. (-40°C ~ 85°C)
Power
LL-Part
LL-Part
Temperature
E1
I2
Package
FBGA
FBGA
ABSOLUTE MAXIMUM RATINGS 1
Symbol
VIN,VOUT
Vdd
Parameter
Input/Output Voltage
Power Supply
TA
Rating
-0.3 to Vdd+0.3
Ambient Temperature
TSTG
PD
Storage Temperature
Power Dissipation
Ball Soldering Temperature & Time
TSOLDER
-0.3 to 3.6
-25 to 85
-40 to 85
-55 to 150
1.0
260•10
Unit
V
V
°C
°C
°C
W
°C•sec
Remark
HY64LD16162M-E
HY64LD16162M-I
Note
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent
damage to the device. This is stress rating only and the functional operation of the device under these or
any other conditions above those indicated in the operation of this specification is not implied. Exposure
to the absolute maximum rating conditions for extended period may affect reliability.
TRUTH TABLE
/CS1 CS2
H
X
X
L
L
L
L
L
L
L
L
L
H
L
H
H
H
H
H
H
H
H
H
H
/WE
/OE
/LB
/UB
Mode
X
X
X
L
H
H
L
H
H
L
H
H
X
X
X
X
L
H
X
L
H
X
L
H
X
X
H
L
L
L
H
H
H
L
L
L
X
X
H
H
H
H
L
L
L
L
L
L
Deselected
Deselected
Deselected
Write
Read
Output Disabled
Write
Read
Output Disabled
Write
Read
Output Disabled
I/O Pin
Power
I/O1~I/O8
I/O9~I/O16
High-Z
High-Z
Standby
High-Z
High-Z
Deep Power Down
High-Z
High-Z
Standby
DIN
High-Z
Active
DOUT
High-Z
Active
High-Z
High-Z
Active
High-Z
DIN
Active
High-Z
DOUT
Active
High-Z
High-Z
Active
DIN
DIN
Active
DOUT
DOUT
Active
High-Z
High-Z
Active
Note
1. H=VIH, L=VIL, X=don’ t care(VIL or VIH)
2. /UB, /LB(Upper, Lower Byte enable)
These active LOW inputs allow individual bytes to be written or read.
When /LB is LOW, data is written or read to the lower byte, I/O1 - I/O8.
When /UB is LOW, data is written or read to the upper byte, I/O9 - I/O16.
Revision 1.7
March. 2002
3
HY64LD16162M Series
RECOMMENDED DC OPERATING CONDITION
Symbol
Vdd
VSS
VIH
VIL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
2.3
0
2.0
-0.31
Typ.
2.5
-
Max.
2.7
0
Vdd+0.3
0.6
Unit
V
V
V
V
Note 1. VIL=-1.5V for pulse width less than 10ns
Undershoot is sampled, not 100% tested.
DC ELECTRICAL CHARACTERISTICS
Vdd=2.3~2.7V, TA= -25°C to 85°C(E) / -240°C to 85°C(I)
Sym.
Parameter
Test Condition
ILI
Input Leakage Current
VSS≤VIN≤Vdd
ILO
Output Leakage Current
VSS≤VOUT≤Vdd,
/CS1=VIH, CS2=VIH,
/OE=VIH or /WE=VIL
ICC
Operating Power Supply Current
Average Operating Current
ICC1
ICC2
ISB
TTL Standby Current
ISB1
Standby Current(CMOS Input)
IDPD
VOL
VOH
Deep Power Down Current
Output Low Voltage
Output High Voltage
Min. Typ. Max. Unit
-1
1
µA
-1
-
1
µA
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL, II/O=0mA
-
-
3
mA
/CS1≤ 0.2V, CS2 ≥Vdd-0.2V,
VIN ≤0.2V or VIN≥Vdd-0.2V,
Cycle Time=1µs.
100% Duty, II/O=0mA
-
-
5
mA
/CS1=VIL, CS2=VIH,
VIN=VIH or VIL, Cycle Time=Min.
100% Duty, II/O=0mA
-
-
20
mA
-
-
0.5
mA
-
-
75
µA
2.0
-
2
0.4
-
µA
V
V
/CS1,CS2=VIH or /UB,/LB= VIH
/CS1, CS2≥Vdd-0.2V
or /UB,/LB ≥Vdd-0.2V
CS2≤VSS+0.2V
IOL=0.5mA
IOH=-0.5mA
CAPACITANCE
(Temp = 25°C, f=1.0MHz)
Symbol
Parameter
CIN
Input Capacitance(Add, /CS1, CS2, /WE, /OE, /UB, /LB)
COUT
Output Capacitance(I/O)
Condition
VIN=0V
VI/O=0V
Max. Unit
8
pF
10 pF
Note : These parameters are sampled and not 100% tested
Revision 1.7
March. 2002
4
HY64LD16162M Series
AC CHARACTERISTICS
Vdd=2.3V~2.7V, TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
-85
#
Symbol
Parameter
Min.
Max.
Read Cycle
1
tRC
Read Cycle Time
85
2
tAA
Address Access Time
85
3
tACS
Chip Select Access Time
85
4
tOE
Output Enable to Output Valid
20
5
tBA
/LB, /UB Access Time
85
6
tCLZ
Chip Select to Output in Low Z
10
7
tOLZ
Output Enable to Output in Low Z
5
8
tBLZ
/LB, /UB Enable to Output in Low Z
10
9
tCHZ
Chip Disable to Output in High Z
0
30
10
tOHZ
Out Disable to Output in High Z
0
30
11
tBHZ
/LB, /UB Disable to Output in High Z
0
30
12
tOH
Output Hold from Address Change
10
Write Cycle
13
tWC
Write Cycle Time
85
14
tCW
Chip Selection to End of Write
70
15
tAW
Address Valid to End of Write
70
16
tBW
/LB, /UB Valid to End of Write
70
17
tAS
Address Set-up Time
0
18
tWP
Write Pulse Width
60
19
tWR
Write Recovery Time
0
20
tWHZ
Write to Output in High Z
0
30
21
tDW
Data to Write Time Overlap
30
22
tDH
Data Hold from Write Time
0
23
tOW
Output Active from End of Write
5
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AC TEST CONDITIONS
TA = -25°C to 85°C(E) / -40°C to 85°C(I), unless otherwise specified
Parameter
Value
Input Pulse Level
0.4V to 2.2V
Input Rising and Fall Time
5ns
Input and Output Timing Reference Level
1.1V
Output Load
See Below
AC TEST LOADS
RL=50 Ohm
DOUT
VL=1.1 V
Z0=50 Ohm
CL1 =30 pF
Note
1. Including jig and scope capacitance.
Revision 1.7
March. 2002
5
HY64LD16162M Series
Power-Up Sequence
1. Supply power.
2. Maintain stable power for longer than 200µs.
Deep Power Down Entry Sequence
1. Keep CS2 low state.
Deep power down mode is maintained while CS2 is low state.
Deep Power Down Exit Sequence
1. Keep CS2 high state.
2. Maintain stable power for longer than 200µs.
STATE DIAGRAM
/ CS1=VIL, CS2=VIH,
/UB&/LB≠VIH
Deep Power Down Exit
Sequence
Power-Up
Sequence
Power
Power On
On
CS2=VIH
Wait
µs
200
Wait 200µ
200µs
Active
Active
CS2=VIL
CS2=VIH, /CS1=VIH
or /UB,/LB=VIH
Standby
Standby
Mode
Mode
Deep
Deep Power
Power
Down
Down Mode
Mode
CS2=VIL
Deep Power Down
Entry Sequence
STANDBY MODE CHARACTERISTICS
Mode
Memory Cell Data
Standby Current[µA]
Wait Time[µs]
Standby
Valid
75
0
Deep Power Down
Invalid
2
200
Revision 1.7
March. 2002
6
HY64LD16162M Series
TIMING DIAGRAM
READ CYCLE 1 ( Note 1, 4 )
tRC
ADD
tAA
tOH
tACS
/CS1
tCHZ(3)
CS2
Vih
tBA
/UB, /LB
tBHZ(3)
tOE
/OE
tOHZ(3)
tOLZ(3)
tBLZ(3)
tCLZ(3)
Data Out
High-Z
Data Valid
READ CYCLE 2 ( Note 1, 2, 4 )( CS2=Vih )
tRC
ADD
tAA
tOH
tOH
Data Out
Previous Data
Data Valid
READ CYCLE 3 ( Note 1, 2, 4 )( CS2=Vih )
/CS1
/UB, /LB
tACS
tCHZ(3)
tCLZ(3)
Data Out
High-Z
Data Valid
Notes :
1. Read Cycle occurs whenever a high on the /WE and /OE is low, while /UB and/or /LB and /CS1 and CS2 are in active status.
2. /OE = VIL
3. tCHZ, tBHZ and tOHZ are defined as the time at which the outputs achieve the high impedance state and tOLZ,tBLZ and tCLZ
are defined as the time at which the outputs achieve the low impedance state.
These are not referenced to output voltage levels.
4. /CS1 in high for the standby, low for active.
/UB and /LB in high for the standby, low for active.
Revision 1.7
March. 2002
7
HY64LD16162M Series
WRITE CYCLE 1 ( Note 1, 4, 5, 9, 10 ) ( /WE Controlled )
tWC
ADD
tWR(2)
tCW
/CS1
CS2
Vih
tAW
tBW
/UB, /LB
/WE
tWP
tAS
tDW
Data In
High-Z
tDH
Data Valid
tWHZ(3,8)
tOW
(6)
(7)
Data Out
WRITE CYCLE 2 ( Note 1, 4, 5, 9, 10 ) ( /CS1 Controlled )
tWC
ADD
tAS
tWR(2)
tCW
/CS1
CS2
Vih
tAW
tBW
/UB, /LB
tWP
/WE
tDW
Data In
Data Out
High-Z
tDH
Data Valid
High-Z
Notes :
1. A write occurs during the overlap of low /CS1, low /WE and low /UB and/or /LB.
2. tWR is measured from the earlier of /CS1, /LB, /UB, or /WE going high to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be applied.
4. If the /CS1, /LB and /UB low transition occur simultaneously with the /WE low transition or after the
/WE transition, outputs remain in a high impedance state.
5. /OE is continuously low (/OE=VIL)
6. Q(data out) is the invalid data.
7. Q(data out) is the read data of the next address.
8. tWHZ is defined as the time at which the outputs achieve the high impedance state.
It is not referenced to output voltage levels.
9. /CS1 in high for the standby, low for active. /UB and /LB in high for the standby, low for active.
10. Do not input data to the I/O pins while they are in the output state.
Revision 1.7
March. 2002
8
HY64LD16162M Series
AVOID TIMING
Hynix 1T/1C SRAM has a timing which is not supported at read operation. If your system has multiple
invalid address signal shorter than tRC during over 10us at read operation which showed in abnormal
timing, Hynix 1T/1C SRAM needs a normal read timing at least during 10us which showed in avoidable
timing(1) or toggle the /CS1 to high(≥tRC) one time at least which showed in avoidable timing(2)
ABNORMAL TIMING
/CS1
≥ 10us
/WE
< tRC
ADD
AVOIDABLE TIMING(1)
/CS1
≥ 10us
/WE
≥ tRC
ADD
≥ tRC
AVOIDABLE TIMING(2)
/CS1
≥ 10us
/WE
< tRC
ADD
Revision 1.7
March. 2002
9
HY64LD16162M Series
PACKAGE DIMENSION
48ball Fine Pitch Ball Grid Array Package(F)
BOTTOM
BOTTOM VIEW
VIEW
TOP
TOP VIEW
VIEW
A1 CORNER
INDEX AREA
A1 INDEX
MARK
B1
B
A
A
A
B
C
C
D
C1
E
F
C/2
G
H
6
5
4
3
2
1
B/2
SIDE
SIDE VIEW
VIEW
5
E1
E
C
E2 SEATING PLANE
A
4
R
3 D(DIAMETER)
unit : mm
NOTE.
Symbol
Min.
Typ.
Max.
A
B
6.90
0.75
7.00
7.10
B1
C
7.90
3.75
8.00
8.10
3. DIMENSION “D” IS MEASURED AT THE MAXIMUM SOLDER
BALL DIAMETER IN A PLANE PARALLEL TO DATUM C.
C1
D
0.30
5.25
0.35
0.40
4. PRIMARY DATUM C(SEATING PLANE) IS DEFINED BY THE
CROWN OF THE SOLDER BALLS.
E
-
1.00
1.10
E1
E2
0.20
0.75
0.25
0.30
R
-
-
0.08
Revision 1.7
March. 2002
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE MILLIMETERS.
5. THIS IS A CONTROLLING DIMENSION.
10
HY64LD16162M Series
MARKING INFORMATION
Package
FBGA
Marking Example
H
Y
L
D
c
s
s
t
x
x
x
x
1
6
1
6
2
M
y
y
w
w
p
K
O
R
x
Index
• HYLD16162M
HY
L
D
16
16
2
M
: Part Name
: HYNIX
: Power Supply
: Tech. + Classification
: Bit Organization
: Density
: Mode
: Version
• c
• ss
• t
: Power Consumption
: Speed
: Temperature
• yy
• ww
• p
: Year (ex : 01 = year 2001, 02= year 2002)
: Work Week ( ex : 12 = work week 12 )
: Process Code
• xxxxx
: Lot No.
• KOR
: Origin Country
Note
- Capital Letter
- Small Letter
: Fixed Item
: Non-fixed Item
Revision 1.7
March. 2002
: 2.5V(2.3V~2.7V)
: 1T+1C
: x16
: 16M
: 1CS with /UB,/LB;tCS
: 1st Generation
: D – Low Low Power
: 85 – 85ns
: E – Extended(-25 ~ 85°C)
I – Industrial(-40 ~ 85°C)
11