HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM 64-MBit Synchronous DRAM • High Performance: • Full page (optional) for sequential wrap around • Multiple Burst Read with Single Write Operation -7.5 -8 Units fCKMAX 133 125 MHz tCK3 7.5 8 ns • Automatic and Controlled Precharge Command tAC3 5.4 6 ns • Data Mask for Read/Write Control (x4, x8) tCK2 10 10 ns • Auto Refresh (CBR) and Self Refresh tAC2 6 6 ns • Suspend Mode and Power Down Mode • 4096 Refresh Cycles / 64 ms • Fully Synchronous to Positive Clock Edge • Random Column Address every CLK (1-N Rule) • 0 to 70 °C operating temperature • Single 3.3 V ± 0.3 V Power Supply • Four Banks controlled by BA0 & BA1 • LVTTL Interface • Programmable CAS Latency: 2, 3 • Plastic Packages: P-TSOPII-54 400mil width (x4, x8) • Programmable Wrap Sequence: Sequential or Interleave • -7.5 version for PC133 3-3-3 application -8 version for PC100 2-2-2 applications • Programmable Burst Length: 1, 2, 4, 8 The HYB 39S64400/800CT are four bank Synchronous DRAM’s organized as 4 banks × 4 MBit × 4 and 4 banks × 2 MBit × 8 respectively. These synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using the Infineon advanced 0.19 µm 64 MBit DRAM process technology. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3 V ± 0.3 V power supply and are available in TSOPII packages. Data Book 1 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Ordering Information Type Ordering Code Package Description HYB 39S64400CT-7.5 PC133-333 P-TSOP-54-2 (400mil) 133 MHz 4B × 4M x4 SDRAM HYB 39S64400CT-8 PC100-222 P-TSOP-54-2 (400mil) 125 MHz 4B × 4M x4 SDRAM HYB 39S64800CT-7.5 PC133-333 P-TSOP-54-2 (400mil) 133 MHz 4B × 2M x8 SDRAM HYB 39S64800CT-8 P-TSOP-54-2 (400mil) 125 MHz 4B × 2M x8 SDRAM PC100-222 HYB 39S64xxx0CTL-8 PC100-222 P-TSOP-54-2 (400mil) Low Power (L-versions) Pin Definitions and Functions CLK Clock Input DQ Data Input/Output CKE Clock Enable DQM Data Mask CS Chip Select VDD Power (+ 3.3 V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQ’s (+ 3.3 V) WE Write Enable VSSQ Ground for DQ’s A0 - A11 Address Inputs N.C. Not connected BA0, BA1 Bank Select Data Book 2 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM TSOPII-54 (10.16 mm × 22.22 mm, 0.8 mm pitch) 8Mx8 16 M x 4 VDD VDD DQ0 N.C. VDDQ VDDQ N.C. DQ1 N.C. DQ0 VSSQ VSSQ N.C. DQ2 N.C. N.C. VDDQ VDDQ N.C. DQ3 N.C. DQ1 VSSQ VSSQ N.C. N.C. VDD VDD N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 N.C. WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A3 VDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS VSS N.C. DQ7 VSSQ VSSQ N.C. DQ3 N.C. DQ6 VDDQ VDDQ N.C. N.C. N.C. DQ5 VSSQ VSSQ N.C. DQ2 N.C. DQ4 VDDQ VDDQ N.C. N.C. VSS VSS N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4 N.C. DQM CLK CKE N.C. A11 A9 A8 A7 A6 A5 A4 VSS VSS SPP04201 Pin Configuration for x4 and x8 Organized 64M-SDRAMs Data Book 3 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Functional Block Diagrams Row Addresses A0 - A9, AP, BA0, BA1 A0 - A11, BA0, BA1 Column Address Buffer Row Address Buffer 4096 x 1024 x 4 Bit Row Decoder Memory Array Bank 1 4096 x 1024 x 4 Bit Input Buffer Memory Array Bank 2 4096 x 1024 x 4 Bit Output Buffer DQ0 - DQ3 Row Decoder Column Decoder Sense Amplifier & I(O) Bus Bank 0 Column Decoder Sense Amplifier & I(O) Bus Column Decoder Sense Amplifier & I(O) Bus Memory Array Refresh Counter Memory Array Bank 3 4096 x 1024 x 4 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM Row Decoder Row Decoder Column Decoder Sense Amplifier & I(O) Bus Column Address Counter Column Addresses SPB03696 Block Diagram: 4 Bank × 4M x4 SDRAM Data Book 4 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Row Addresses A0 - A8, AP, BA0, BA1 A0 - A11, BA0, BA1 Column Address Buffer Row Address Buffer 4096 x 512 x 8 Bit Row Decoder Memory Array Bank 1 4096 x 512 x 8 Bit Input Buffer Memory Array Bank 2 4096 x 512 x 8 Bit Output Buffer DQ0 - DQ7 Row Decoder Column Decoder Sense Amplifier & I(O) Bus Bank 0 Refresh Counter Memory Array Bank 3 4096 x 512 x 8 Bit Control Logic & Timing Generator CLK CKE CS RAS CAS WE DQM Memory Array Row Decoder Column Decoder Sense Amplifier & I(O) Bus Column Decoder Sense Amplifier & I(O) Bus Row Decoder Column Decoder Sense Amplifier & I(O) Bus Column Address Counter Column Addresses SPB03697 Block Diagram: 4 Bank × 2M x8 SDRAM Data Book 5 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Signal Pin Description Pin Type Signal Polarity Function CLK Input Pulse Positive The system clock input. All of the SDRAM inputs are Edge sampled on the rising edge of the clock. CKE Input Level Active High Activates the CLK signal when high and deactivates the CLK signal when low, thereby initiates either the Power Down mode, Suspend mode, or the Self Refresh mode. CS Input Pulse Active Low CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the command to be executed by the SDRAM. A0 - A11 Input Level – During a Bank Activate command cycle, A0 - A11 define the row address (RA0 - RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0 - An define the column address (CA0 - CAn) when sampled at the rising clock edge.CAn depends from the SDRAM organization: 16M x4 SDRAM CAn = CA9 (Page Length = 1024 bits) 8M x8 SDRAM CAn = CA8 (Page Length = 512 bits) In addition to the column address, A10(= AP) is used to invoke autoprecharge operation at the end of the burst read or write cycle. If A10 is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 (= AP) is used in conjunction with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all four banks will be precharged regardless of the state of BA0 and BA1. If A10 is low, then BA0 and BA1 are used to define which bank to precharge. BA0, BA1 Input DQx Data Book Level – Bank Select Inputs. Selects which bank is to be active. Input Level Output – Data Input/Output pins operate in the same manner as on conventional DRAMs. 6 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Signal Pin Description (cont’d) Pin Type Signal Polarity Function DQM Input Pulse VDD VSS Active High The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. One DQM input it present in x4 and x8 SDRAMs. Supply – – Power and ground for the input buffers and the core logic. VDDQ VSSQ Supply – – Isolated power supply and ground for the output buffers to provide improved noise immunity. VREF Input – Reference voltage for SDRAM versions supporting SSTL interface. Data Book Level 7 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Operation Definition All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge of the clock. The following list shows the truth table for the operation commands. Operation Device State Row Activate (ACT) Idle3 CKE n-1 CKE n CS RAS CAS WE DQ M A0-9, A10 A11 BA0 BA1 H X L L H H X V V V Active 3 H X L H L H X V L V Read w/ Autoprecharge (READA) Active 3 H X L H L H X V H V Write (WRITE) Active3 H X L H L L X V L V 3 H X L H L L X V H V Read (READ) Write w/ Autoprecharge (WRITEA) Active Row Precharge (PRE) Any H X L L H L X X L V Precharge All (PREA) Any H X L L H L X X H X Mode Register Set (MRS) Idle H X L L L L X V V V No Operation (NOP) Any H X L H H H X X X X Device Deselect (INHBT) Any H X H X X X X X X X Auto Refresh (REFA) Idle H H L L L H X X X X Self Refresh Entry (REFS-EN) Idle H L L L L H X X X X H X X X L H L H H X X X X X H X X X H L L H H X X X X X Any (Power Down) H X X X L H L H H L X X X X Data Write/Output Enable Active H X X X X X L X X X Data Write/Output Disable Active H X X X X X H X X X Self Refresh Exit (REFS-EX) Power Down Entry (PDN-EN) Power Down Exit (PDN-EX) Idle (Self Refr.) Idle Active5 Note: 1. V = Valid, x = Don’t Care, L = Low Level, H = High Level 2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are provided. 3. This is the state of the banks designated by BA0, BA1 signals. 4. Device state is Full Page Burst operation. 5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode cycle device is clock suspend mode. Data Book 8 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Address Input for Mode Set (Mode Register Operation) BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A3 A4 A2 A0 A1 Address Bus (Ax) Operation Mode CAS Latency Burst Length BT Mode Register (Mx) Operation Mode Burst Type Mode M3 Type 0 burst read / burst write 0 Sequential 1 Interleave 0 burst read / single write BA1 BA0 M11 M10 M9 M8 M7 0 0 0 0 0 0 0 0 0 1 CAS Latency M6 M5 M4 0 0 Burst Length Length Latency M2 M1 M0 Sequential Interleave 0 1 1 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 0 Reserved 0 0 1 Reserved 0 0 0 1 0 2 0 0 1 1 3 1 0 0 1 0 1 1 1 1 1 Reserved Reserved Reserved Full Page*) *) optional SPS03409 Data Book 9 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Power On and Initialization The default power on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner.During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause of 200 µs is required followed by a precharge of both banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register The Mode register designates the operation mode at the read or write cycle. This register is divided into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency Field to set the access time at clock cycle and a Operation mode field to differentiate between normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode. The mode set operation must be done before any activate command after the initial power up. Any content of the mode register can be altered by re-executing the mode set command. All banks must be in precharged state and CKE must be high at least one clock before the mode set operation. After the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate the mode set operation. Address input data at this timing defines parameters to be set as shown in the previous table. Read and Write Operation When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either a read (WE = H) or a write (WE = L) at this stage. SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. Column addresses are segmented by the burst length and serial data accesses are done within this boundary. The first column address to be accessed is supplied at the CAS timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. Full page burst operation is only possible using the sequential burst type and page length is a function of the I/O organization and column addressing. Full page burst operation do not self Data Book 10 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM terminate once the burst length has been reached. In other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command. Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the refresh interval time limits the number of random column accesses. A new burst access can be done even before the previous burst ends. The interrupt operation at every clock cycle is supported. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. An interrupt which accompanies an operation change from a read to a write is possible by exploiting DQM to avoid bus contention. When two or more banks are activated sequentially, interleaved bank read or write operations are possible. With the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. Once two or more banks are activated, column to column interleave operation can be done between different pages. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Burst Addressing (decimal) Interleave Burst Addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4 x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 Full Page (optional) nnn 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 Cn, Cn+1, Cn+2,..... 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 not supported Refresh Mode SDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS -before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any refresh mode. An on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are held high at a clock timing. The mode restores word line after the refresh and no external precharge Data Book 11 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM command is necessary. A minimum tRC time is required between two automatic refreshes in a burst refresh mode. The same rule applies to any access command after the automatic refresh operation. The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS, CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to any access command. DQM Function DQM has two functions for data I/O read and write operations. During reads, when it turns to “high” at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks). Suspend Mode During normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the internal clock and extends data read and write operations. One clock delay is required for mode entry and exit (Clock Suspend Latency tCSL). Power Down In order to reduce standby power consumption, a power down mode is available. All banks must be precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is required for mode entry and exit. Auto Precharge Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS timing accepts one extra address, CA10, to determine whether the chip restores or not after the operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function is initiated. If CA10 is high when a Write Command is issued, the Write with AutoPrecharge function is initiated. The SDRAM automatically enters the precharge operation two clocks after the last data in. Precharge Command There is also a separate precharge command available. When RAS and WE are low and CAS is high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are used to define banks as shown in the following list. The precharge command can be imposed one clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS latency = 3. Writes require a time delay tWR from the last data out to apply the precharge command. Data Book 12 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Bank Selection by Address Bits A10 BA0 BA1 0 0 0 Bank 0 0 0 1 Bank 1 0 1 0 Bank 2 0 1 1 Bank 3 1 x x all Banks Burst Termination Once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. These methods include using another Read or Write Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank. When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. If a Burst Stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered will be written to the memory. Data Book 13 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Electrical Characteristics Absolute Maximum Ratings Operating Temperature Range.......................................................................................0 to + 70 °C Storage Temperature Range .................................................................................. – 55 to + 150 °C Input/Output Voltage......................................................................................... – 0.3 to VDD + 0.3 V Power Supply Voltage VDD/VDDQ .............................................................................. – 0.3 to + 4.6 V Power Dissipation ....................................................................................................................... 1 W Data out Current (short circuit) ............................................................................................... 50 mA Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operation and DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values min. max. Unit Notes Input High Voltage VIH 2.0 VDD + 0.3 V 1, 2 Input Low Voltage VIL – 0.3 0.8 V 1, 2 Output High Voltage (IOUT = – 4.0 mA) VOH 2.4 – V – Output Low Voltage (IOUT = 4.0 mA) VOL – 0.4 V – Input Leakage Current, any input (0 V < VIN < VDDQ , all other inputs = 0 V) II(L) –5 5 µA – Output Leakage Current (DQ is disabled, 0 V < VOUT < VDD) IO(L) –5 5 µA – Notes 1. All voltages are referenced to VSS 2. VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to – 2.0 V for pulse width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference. Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Values min. max. Unit Input Capacitance (CLK) CI1 2.5 3.5 pF Input Capacitance (A0 - A11, BA0, BA1, RAS, CAS, WE, CS, CKE, DQM) CI2 2.5 3.8 pF Input/Output Capacitance (DQ) CIO 4.0 6.0 pF Data Book 14 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Operating Currents TA = 0 to 70 °C, VDD = 3.3 V ± 0.3 V (Recommended Operating Conditions unless otherwise noted) Parameter & Test Condition Symb. -7.5 -8 Unit Note max. ICC1 Operating Current tRC = tRC(MIN.), tCK = tCK(MIN.) Outputs open, Burst Length = 4, CL=3 All banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access – Precharge standby current in Power Down Mode CS = VIH (MIN.), CKE ≤ VIL(MAX.) tCK = min ICC2P 2 tCK = infinity ICC2PS Precharge standby current in Non Power Down Mode CS = VIH (MIN.), CKE ≥ VIH(MIN.) tCK = min mA mA 3 2 mA 3 1.5 1.5 mA 3 ICC2N 40 35 mA 3 tCK = infinity ICC2NS 15 15 mA 3 No operating current tCK = min., CS = VIH (MIN.), active state (max. 4 banks) CKE ≥ VIH(MIN.) ICC3N 50 45 mA 3 CKE ≤ VIL(MAX.) ICC3P 8 8 mA 3 Burst Operating Current tCK = min Read command cycling – ICC4 70 80 60 70 mA mA 3, 4 Auto Refresh Current tCK = min Auto Refresh command cycling – ICC5 140 130 mA 3 Self Refresh Current Self Refresh Mode CKE = 0.2 V standard version ICC6 1 3 x4 110 100 x8 120 110 x4 x8 L-version 1 mA 500 500 µA 3 Notes 3. These parameters depend on the cycle rate and these values are measured at 133 MHz for -7.5 and at 100 MHz for -8 parts. Input signals are changed once during tCK, excepts for ICC6 and for standby currents when tCK = infinity. 4. These parameters are measured with continuous data stream during read access and all DQ toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded. Data Book 15 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM AC Characteristics 1, 2 TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symb. Limit Values -7.5 Unit Note -8 min. max. min. max. CAS Latency = 3 tCK CAS Latency = 2 7.5 10 – – 8 10 – – ns ns CAS Latency = 3 tCK CAS Latency = 2 133 100 – – – – 125 100 MHz MHz Clock and Clock Enable – Clock Cycle Time – Clock frequency Access Time from Clock CAS Latency = 3 tAC CAS Latency = 2 2, 3 – – 5.4 6 – – 6 6 ns ns Clock High Pulse Width tCH 2.5 – 3 – ns – Clock Low Pulse Width tCL 2.5 – 3 – ns – Transition Time tT 0.3 1.2 0.5 10 ns – Input Setup Time tIS 1.5 – 2 – ns 4 Input Hold Time tIH 0.8 – 1 – ns 4 CKE Setup Time tCKS 1.5 – 2 – ns 4 CKE Hold Time tCKH 0.8 – 1 – ns 4 Mode Register Set-up Time tRSC 2 – 2 – CLK – Power Down Mode Entry Time tSB 0 7 0 8 ns – Row to Column Delay Time tRCD 20 – 20 – ns 5 Row Precharge Time tRP 20 – 20 – ns 5 Row Active Time tRAS 45 100k 48 100k ns 5 Row Cycle Time tRC 67 – 70 – ns 5 Activate(a) to Activate(b) Command Period tRRD 14 – 16 – ns 5 CAS(a) to CAS(b) Command Period tCCD 1 – 1 – CLK – Setup and Hold Times Common Parameters Data Book 16 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM AC Characteristics (cont’d)1, 2 TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns Parameter Symb. Limit Values -7.5 Unit Note -8 min. max. min. max. Refresh Cycle Refresh Period (4096 cycles) tREF – 64 – 64 ms – Self Refresh Exit Time tSREX 1 – 1 – CLK 6 Data Out Hold Time tOH 3 – 3 – ns 2 Data Out to Low Impedance Time tLZ 1 – 0 – ns – Data Out to High Impedance Time tHZ 3 7 3 8 ns – DQM Data Out Disable Latency tDQZ – 2 – 2 CLK – Write Recovery Time tWR 2 – 2 – CLK – DQM Write Mask Latency tDQW 0 – 0 – CLK – Read Cycle Write Cycle Data Book 17 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Notes 1. For proper power-up see the operation section of this data sheet. 2. AC timing have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8 V and 2.0 V. t CH 2.4 V 0.4 V CLOCK t CL t SETUP tT t HOLD INPUT 1.4 V t AC t LZ t AC t OH OUTPUT 1.4 V I/O 50 pF t HZ SPT03404 Measurement conditions for tAC and tOH 3. If clock rising time is longer than 1 ns, a time (tT/2 − 0.5) ns has to be added to this parameter. 4. If tT is longer than 1 ns, a time (tT − 1) ns has to be added to this parameter. 5. These parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) 6. Self Refresh Exit is a synchronous operation and begins on the second positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. Data Book 18 12.99 HYB 39S64400/800CT(L) 64-MBit Synchronous DRAM Package Outlines 0.8 15˚±5˚ 26x 0.8 = 20.8 3) 0.1 54x 0.5 ±0.1 11.76 ±0.2 0.2 M 54x 54 28 1 2.5 max 27 6 max 0.35 +0.1 -0.05 10.16 ±0.13 2) 0.15 +0.06 -0.03 1±0.05 15˚±5˚ 0.1±0.05 Plastic Package, P-TSOPII-54 (400 mil, 0.8 mm lead pitch) Thin Small Outline Package, SMD 22.22 ±0.13 1) GPX09039 Index Marking 1) Does not include plastic or metal protrusion of 0.15 max per side Does not include plastic protrusion of 0.25 max per side 3) Does not include dambar protrusion of 0.13 max per side 2) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Book 19 Dimensions in mm 12.99 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM Timing Diagrams 1. Bank Activate Command Cycle 2. Burst Read Operation 3. Read Interrupted by a Read 4. Read to Write Interval 4.1 Read to Write Interval 4.2 Minimum Read to Write Interval 4.3 Non-Minimum Read to Write Interval 5. Burst Write Operation 6. Write and Read Interrupt 6.1 Write Interrupted by a Write 6.2 Write Interrupted by Read 7. Burst Write & Read with Auto-Precharge 7.1 Burst Write with Auto-Precharge 7.2 Burst Read with Auto-Precharge 8. Burst Termination 8.1 Termination of a full Page Burst Write Operation 8.2 Termination of a full Page Burst Write Operation 9. AC- Parameters 9.1 AC Parameters for a Write Timing 9.2 AC Parameters for a Read Timing 10. Mode Register Set 11. Power on Sequence and Auto Refresh (CBR) 12. Clock Suspension (using CKE) 12. 1 Clock Suspension During Burst Read CAS Latency = 2 12. 2 Clock Suspension During Burst Read CAS Latency = 3 12. 3 Clock Suspension During Burst Write CAS Latency = 2 12. 4 Clock Suspension During Burst Write CAS Latency = 3 13. Power Down Mode and Clock Suspend 14. Self Refresh ( Entry and Exit ) 15. Auto Refresh ( CBR ) 16. Random Column Read ( Page within same Bank) 16.1 CAS Latency = 2 16.2 CAS Latency = 3 17. Random Column Write ( Page within same Bank) 17.1 CAS Latency = 2 17.2 CAS Latency = 3 Semiconductor Group 20 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM Timing Diagrams (cont’d) 18. Random Row Read ( Interleaving Banks) with Precharge 18.1 CAS Latency = 2 18.2 CAS Latency = 3 19. Random Row Write ( Interleaving Banks) with Precharge 19.1 CAS Latency = 2 19.2 CAS Latency = 3 20. Full Page Read Cycle 20.1 CAS Latency = 2 20.2 CAS Latency = 3 21. Full Page Write Cycle 21.1 CAS Latency = 2 21.2 CAS Latency = 3 22. Precharge Termination of a Burst Semiconductor Group 21 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 1. Bank Activate Command Cycle (CAS latency = 3) T0 T1 T T T T T CLK Bank B Row Addr. Address Bank B Col. Addr. t RCD Bank B Activate Command NOP Bank B Row Addr. Bank A Row Addr. t RRD NOP Write B with Auto Precharge Bank A Activate NOP Bank B Activate t RC "H" or "L" SPT03784 2. Burst Read Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A NOP NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s CAS latency = 3 t CK3 , DQ’s Semiconductor Group DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 DOUT A3 SPT03712 22 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 3. Read Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Read A Read B NOP NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 SPT03713 4. Read to Write Intrerval 4.1 Read to Write Interval (Burst Length = 4, CAS latency = 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK Minimum delay between the Read and Write Commands = 4 + 1 = 5 cycles Write latency t DQW of DQMx DQMx t DQZ Command NOP Read A DQ’s NOP NOP NOP DOUT A0 NOP Write B NOP NOP DIN B0 DIN B1 DIN B2 Must be Hi-Z before the Write Command "H" or "L" Semiconductor Group SPT03787 23 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 4 2. Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 Write A NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 CLK t DQW DQM t DQZ 1 Clk Interval Command NOP NOP Bank A Activate NOP Read A Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s "H" or "L" SPT03939 4. 3. Non-Minimum Read to Write Interval (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP NOP CLK t DQW DQM t DQZ Command NOP Read A NOP NOP Read A NOP Write B Must be Hi-Z before the Write Command CAS latency = 2 t CK2 , DQ’s DOUT A0 DOUT A1 DIN B0 DIN B1 DIN B2 CAS latency = 3 t CK3 , DQ’s DOUT A0 DIN B0 DIN B1 DIN B2 "H" or "L" Semiconductor Group SPT03940 24 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 5. Burst Write Operation (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A NOP NOP NOP NOP NOP NOP NOP DIN A0 DIN A1 DIN A2 DIN A3 don’t care CLK Command DQ’s Extra data is ignored after termination of a Burst. The first data element and the Write are registered on the same clock edge. Semiconductor Group 25 SPT03790 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 6. Write and Read Interrupt 6.1 Write Interrupted by a Write (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 Write B NOP NOP NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 CLK 1 Clk Interval Command NOP Write A 1 Clk Interval DQ’s DIN A0 DIN B0 SPT03791 6.2 Write Interrupted by a Read (Burst Length = 4, CAS latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 NOP Write A Read B NOP NOP NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s DIN A0 don’t care CAS latency = 3 t CK3 , DQ’s DIN A0 don’t care DOUT B0 DOUT B1 DOUT B2 DOUT B3 don’t care Input data for the Write is ignored. DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQ’s at least one clock cycle before the Read data appears on the outputs to avoid data contention. SPT03719 Semiconductor Group 26 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 7. Burst Write and Read with Auto Precharge 7.1 Burst Write with Auto-Precharge (Burst Length = 4, CAS latency = 2,3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND BANK A ACTIVE NOP NOP WRITE A Auto-Precharge NOP NOP NOP DIN A0 DQ’s * DIN A1 tWR CAS latency = 3 DIN A0 NOP tRP tWR CAS latency = 2 NOP DIN A1 tRP * DQ’s * Begin Autoprecharge Bank can be reactivated after trp 7.2 Burst Read with Auto-Precharge (Burst Length = 4, CAS latency = 2,3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A with AP CAS latency = 2 tCK2, DQ’s CAS latency = 3 tCK3, DQ’s NOP NOP DOUT A0 NOP NOP DOUT A1 DOUT A0 DOUT A2 DOUT A1 NOP NOP NOP NOP tRP * DOUT A3 * tRP DOUT A2 DOUT A3 * Begin Autoprecharge Bank can be reactivated after trp Semiconductor Group 27 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 8. Burst Termination 8.1 Termination of a Full Page Burst Read Operation (CAS latency = 2, 3) T0 T1 T2 T3 Read A NOP NOP NOP T4 T5 T6 T7 T8 NOP NOP NOP NOP CLK Command CAS latency = 2 t CK2 , DQ’s Burst Terminate DOUT A0 DOUT A1 DOUT A2 DOUT A3 CAS latency = 3 t CK3 , DQ’s DOUT A0 DOUT A1 DOUT A2 DOUT A3 The burst ends after a delay equal to the CAS latency. SPT03722 8.2 Termination of a Full Page Burst Write Operation ( (CAS latency = 2, 3) T0 T1 T2 T3 T4 NOP Write A NOP NOP Burst Terminate DIN A0 DIN A1 DIN A2 don’t care T5 T6 T7 T8 NOP NOP NOP NOP CLK Command CAS latency = 2, 3 DQ’s Input data for the Write is masked. Semiconductor Group 28 SPT03419 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 9. AC Parameters 9.1 AC Parameters for a Write Timing Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CH t CK2 t CL CKE t CKS t CH t CKH Begin Auto Precharge Bank B Begin Auto Precharge Bank A t CS CS RAS CAS WE BS t AH AP RAx RBx RAy RAz RBy RAz RBy t AS Addr. RAx CAx RBx CBx RAy RAy DQM t DS t RCD t DH t RC DQ Hi-Z t WR t RP Ax0 Ax1 Ax2 Ax3 Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Write with Auto Precharge Command Bank A Semiconductor Group Activate Command Bank B Activate Command Bank A Write with Auto Precharge Command Bank B Write Command Bank A Precharge Command Bank A t RRD Activate Command Bank A Activate Command Bank B SPT03910 29 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 9.2 AC Parameters for a Read Timing Burst Length = 2, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 CLK t CH t CK2 t CL CKE t CKH t CS Begin Auto Precharge Bank A t CKS t CH Begin Auto Precharge Bank B CS RAS CAS WE BS t AH AP RAx RBx RAy t AS Addr. RAx CAx RBx RAy RBx t RRD t RAS t RC DQM t AC2 t LZ t RCD DQ t OH Hi-Z Read with Auto Precharge Command Bank A Activate Command Bank B 30 t RP t AC2 Ax0 Activate Command Bank A Semiconductor Group t HZ t HZ Ax1 Read with Auto Precharge Command Bank B Bx0 Precharge Command Bank A Bx1 Activate Command Bank A SPT03911 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 10. Mode Register Set CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK CKE t RSC CS RAS CAS WE BS0, BS1 A10, A11 Address Key A0-A9 Precharge Command All Banks Any Command Mode Register Set Command Semiconductor Group SPT03912 31 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 11. Power on Sequence and Auto Refresh (CBR) T2 T3 T4 CKE T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ ~ ~ ~ ~ CLK T1 ~ ~ T0 2 Clock min. Minimum of 8 Refresh Cycles are required ~ ~ ~ ~ High Level is required ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ AP ~ ~ ~ ~ BS ~ ~ ~ ~ ~ ~ WE ~ ~ ~ ~ ~ ~ ~ ~ CAS ~ ~ ~ ~ ~ ~ ~ ~ RAS ~ ~ ~ ~ CS ~ ~ ~ ~ ~ ~ ~ ~ Addr. ~ ~ ~ ~ Address Key DQM t RC ~ ~ DQ ~ ~ t RP Hi-Z 8th Auto Refresh Command Precharge Command All Banks Inputs must be stable for 200 µs Semiconductor Group 1st Auto Refresh Command Mode Register Set Command Any Command SPT03913 32 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 12. Clock Suspension ( Using CKE) 12.1 Clock Suspension During Burst Read CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t CSL t CSL DQ Hi-Z Ax0 Read Activate Command Command Bank A Bank A Semiconductor Group t HZ t CSL Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 33 SPT03914 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 12.2 Clock Suspension During Burst Read CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx t CSL t CSL DQM t CSL t HZ DQ Hi-Z Ax0 Activate Command Bank A Semiconductor Group Read Command Bank A Ax1 Ax2 Ax3 Clock Suspend 1 Cycle Clock Suspend 2 Cycles Clock Suspend 3 Cycles 34 SPT03915 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 12.3 Clock Suspension During Burst Write CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles DAx3 Clock Suspend 3 Cycles Write Command Bank A Semiconductor Group SPT03916 35 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 12.4 Clock Suspension During Burst Write CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BA A8/AP RAx Addr. RAx CAx DQMx DQ Hi-Z DAx0 Activate Command Bank A DAx1 Clock Suspend 1 Cycle DAx2 Clock Suspend 2 Cycles Clock Suspend 3 Cycles Write Command Bank A Semiconductor Group DAx3 SPT03917 36 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 13. Power Down Mode and Clock Suspend Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CKS t CK2 t CKS CKE CS RAS CAS WE BS AP RAx Addr. RAx CAx DQM t HZ DQ Hi-Z Ax0 Ax1 Activate Command Bank A Active Standby Clock Suspend Mode Entry Read Command Bank A Ax2 Clock Mask Start Clock Suspend Mode Exit Clock Mask End Ax3 Precharge Command Bank A Precharge Standby Power Down Mode Entry Any Command Power Down Mode Exit SPT03918 Semiconductor Group 37 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 14. Self Refresh (Entry and Exit) T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ T0 CKE t CKS ~ ~ t CKS ~ ~ ~ ~ CLK ~ ~ ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS ~ ~ ~ ~ AP ~ ~ Addr. t SREX Hi-Z All Banks must be idle ~ ~ DQ t RC ~ ~ DQM Self Refresh Entry Any Command Begin Self Refresh Exit Command Self Refresh Exit Command issued Self Refresh Exit SPT03919 Semiconductor Group 38 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 15. Auto Refresh (CBR) Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAx Addr. RAx t RP DQM DQ t RC (Minimum Interval) CAx t RC Hi-Z Ax0 Ax1 Ax2 Ax3 Precharge Command All Banks Auto Refresh Command Auto Refresh Command Activate Command Bank A Read Command Bank A SPT03920 Semiconductor Group 39 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 16. Random Column Read (Page within same Bank) 16.1 CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Semiconductor Group Read Command Bank A Read Command Bank A Read Command Bank A 40 Precharge Command Bank A Activate Command Bank A Az0 Az1 Az2 Az3 Read Command Bank A SPT03921 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 16.2 CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z Aw0 Aw1 Aw2 Aw3 Ax0 Ax1 Ay0 Ay1 Ay2 Ay3 Activate Command Bank A Semiconductor Group Read Command Bank A Read Command Bank A Read Command Bank A 41 Precharge Command Bank A Activate Command Bank A Read Command Bank A SPT03922 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 17. Random Column write (Page within same Bank) 17.1 CAS Latency = 2 Burst Length = 4, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE BS AP RAw Addr. RAw RAz CAw CAx CAy RAz CAz DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank A Write Command Bank B Write Command Bank B Write Command Bank B Precharge Command Bank B DBz0 DBz1 DBz2 DBz3 Activate Read Command Command Bank B Bank B SPT03923 Semiconductor Group 42 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 17.2. CAS Latency = 3 Burst Length = 4, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE BS AP RBz Addr. RBz RBz CBz CBx CBy RBz CBz DQM DQ Hi Z DBw0 DBw1 DBw2 DBw3 DBx0 DBx1 DBy0 DBy1 DBy2 DBy3 Activate Command Bank B Semiconductor Group Write Command Bank B Write Command Bank B Write Command Bank B 43 DBz0 DBz1 Precharge Command Bank B Activate Command Bank B Write Command Bank B SPT03924 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 18. Random Row Read (Interleaving Banks) with Precharge 18.1 CAS Latency = 2 Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RBy RAx CBx RAx CAx RBy t RCD CBy t RP DQM t AC2 DQ Hi-Z Activate Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 Read Command Bank B Precharge Activate Command Command Bank B Bank B Activate Command Bank A Read Command Bank A Semiconductor Group 44 By0 By1 Read Command Bank B SPT03925 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 18.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE BS AP RBx Addr. RBx RAx CBx RBy RAx CAx RBy t AC3 t RCD CBy t RP DQM DQ Hi-Z Activate Command Bank B Bx0 Bx1 Bx2 Bx3 Bx4 Bx5 Bx6 Bx7 Ax0 Ax1 Ax2 Ax3 Ax4 Ax5 Ax6 Ax7 By0 Read Command Bank B Activate Command Bank A Read Command Bank A Precharge Command Bank B Activate Command Bank B Read Command Bank B Precharge Command Bank A SPT03926 Semiconductor Group 45 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 19. Random Row Write (Interleaving Banks) with Precharge 19.1 CAS Latency = 2 Burst Length = 8, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RBx CAx RAy RBx CBx t RCD RAy t WR CAy t RP t WR DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 DAy4 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Semiconductor Group 46 Activate Command Bank A Precharge Command Bank B Write Command Bank A SPT03927 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 19.2 CAS Latency = 3 Burst Length = 8, CAS Latency = 3 T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 CLK t CK3 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAy RBx CAx RBx CBx t RCD RAy t WR t RP CAy t WR DQM DQ Hi-Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 Write Command Bank A Activate Command Bank B Write Command Bank B Precharge Command Bank A Activate Command Bank A Write Command Bank A Precharge Command Bank B SPT03928 Semiconductor Group 47 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM \ 20. Full Page Read Cycle 20.1 CAS Latency = 2 Burst Length = Full Page, CAS Latency = 2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ T0 ~ ~ CLK ~ ~ t CK2 High ~ ~ CKE ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS RAx Addr. RAx RBx RBy ~ ~ ~ ~ AP RBx CBx RBy ~ ~ CAx t RP Hi-Z Ax Ax +1 Ax + 2 Ax - 2 ~ ~ DQ ~ ~ ~ ~ DQM Activate Command Bank A Read Command Bank A Activate Command Bank B Ax -1 Ax+1 Bx Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval. Semiconductor Group Ax Bx+1 Bx+2 Bx + 3 Bx+ 4 Bx+ 5 Bx + 6 Burst Stop Precharge Command Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 48 Activate Command Bank B SPT03929 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 20.2 CAS Latency = 3 Burst Length = Full Page, CAS Latency = 3 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ T0 ~ ~ CLK ~ ~ t CK3 High ~ ~ CKE ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS RAx Addr. RAx RBx RBy ~ ~ ~ ~ AP RBx CBx RBy ~ ~ CAx t RRD Hi-Z Ax Activate Command Bank B Activate Command Bank A Read Command Bank A Semiconductor Group Ax +1 Ax+ 2 Ax - 2 ~ ~ DQ ~ ~ ~ ~ DQM Ax -1 Read Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval. 49 Ax Ax +1 Bx Bx +1 Bx +2 Bx + 3 Bx+ 4 Bx + 5 Burst Stop Precharge Command Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. Activate Command Bank B SPT03930 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 21. Full Page Write Cycle 21.1 CAS Latency = 2 Burst Length = Full Page, CAS Latency = 2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ T0 ~ ~ CLK ~ ~ t CK2 High ~ ~ CKE ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS RAx Addr. RAx RBx RBx CBx RBy ~ ~ CAx ~ ~ ~ ~ DQM Hi-Z DAx DAx+1 DAx+2 DAx+3 DAx- 1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+ 3 DBx+ 4 DBx+ 5 DBx+6 ~ ~ DQ RBy ~ ~ ~ ~ AP Activate Command Bank A Write Command Bank A Activate Command Bank B The burst counter wraps from the highest order page address back to zero during this time interval. Semiconductor Group Write Command Bank B Data is ignored. Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 50 Burst Stop Command Activate Command Bank B Precharge Command Bank B SPT03931 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 21.2 CAS Latency = 3 Burst Length = Full Page, CAS Latency = 3 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ~ ~ T0 ~ ~ CLK ~ ~ t CK3 High ~ ~ CKE ~ ~ CS ~ ~ ~ ~ RAS ~ ~ ~ ~ CAS ~ ~ ~ ~ WE ~ ~ ~ ~ BS RAx Addr. RAx RBx RBx CBx RBy ~ ~ CAx DAx DAx+1 DAx+2 DAx+3 DAx-1 DAx DAx+ 1 DBx DBx+1 DBx+ 2 DBx+ 3 DBx+ 4 DBx+5 ~ ~ Hi Z ~ ~ ~ ~ DQM DQ RBy ~ ~ ~ ~ AP Activate Command Bank A Activate Command Bank B Write Command Bank B Data is ignored. Burst Stop Command Precharge Command Bank B Write Command Bank A The burst counter wraps from the highest order page address back to zero during this time interval. Semiconductor Group Activate Command Bank B Full Page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues bursting beginning with the starting address. 51 SPT03932 HYB39S64400/800/160CT(L) 64MBit Synchronous DRAM 22. Precharge termination of a Burst 22.1 CAS Latency = 2 Burst Length = 8 or Full Page, CAS Latency = 2 T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 CLK t CK2 CKE High CS RAS CAS WE BS AP RAx Addr. RAx RAz RAy CAx RAy CAy t RP RAz CAz t RP t RP Ay0 Ay1 Ay2 Az0 Az1 Az2 DQM DQ Hi Z Activate Command Bank A DAx0 DAx1 DAx2 DAx3 Write Command Bank A Precharge Termination of a Write Burst. Write Data is masked. Precharge Command Bank A Read Command Bank A Activate Command Bank A Precharge Command Bank A Read Command Bank A Activate Command Bank A Precharge Command Bank A Precharge Termination of a Read Burst. SPT03933 Semiconductor Group 52