3.3V 2M x 64/72-Bit 1 BANK SDRAM Module 3.3V 4M x 64/72-Bit 2 BANK SDRAM Module HYS64/72V2200GU-8/-10 HYS64/72V4220GU-8/-10 168 pin unbuffered DIMM Modules • 168 Pin PC100 and PC66 compatible unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications • 1 bank 2M x 64, 2M x 72 and 2 bank 4M x 64, 4M x 72 organisation • Optimized for byte-write non-parity or ECC applications • JEDEC standard Synchronous DRAMs (SDRAM) • Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification • SDRAM Performance: • fCK Clock frequency (max.) tAC Clock access time -8 -8-3 -10 Units 100 100 66 MHz 6 6 8 ns Programmed Latencies : Product Speed CL tRCD tRP -8 PC100 2 2 2 -8-3 PC100 3 2 3 -10 PC66 2 2 2 • Single +3.3V(± 0.3V ) power supply • Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) • Auto Refresh (CBR) and Self Refresh • Decoupling capacitors mounted on substrate • All inputs, outputs are LVTTL compatible • Serial Presence Detect with E 2PROM • Utilizes 2M x 8 SDRAMs in TSOPII-44 packages • 4096 refresh cycles every 64 ms • 133,35 mm x 31.75 mm x 4,00 mm card size with gold contact pads Semiconductor Group 1 6.98 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules The HYS64(72)2200 and HYS64(72)4220 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organised as 2M x 64, 2M x 72 in 1 bank and 4M x 64 and 4M x 72 in two banks high speed memory arrays designed with Synchronous DRAMs (SDRAMs) for non-parity and ECC applications. The DIMMs use -8 speed sort 2M x 8 SDRAM devices in TSOP44 packages to meet the PC100 requirement. Modules which use -10 parts are suitable for PC66 applications only. Decoupling capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC SDRAM Rev.1.0 module specification. The DIMMs have a serial presence detect, implemented with a serial E 2PROM using the two pin I2C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are available to the end user. All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133,35 mm long footprint, with 1,25“( 31,75 mm) height Ordering Information Type Ordering Code Package Descriptions Module Height HYS 64V2200GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-8 PC100-222-620 L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-8 PC100-222-620 L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module 1,25“ HYS 64V2200GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-8-3 PC100-323-620 L-DIM-168-29 100 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-8-3 PC100-323-620 L-DIM-168-29 100 Mhz 4M x 72 2 bank SDRAM module 1,25“ HYS 64V2200GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 2M x 64 1 bank SDRAM module 1,25“ HYS 72V2200GU-10 PC66-222-920 L-DIM-168-29 66 MHz 2M x 72 1 bank SDRAM module 1,25“ HYS 64V4220GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 4M x 64 2 bank SDRAM module 1,25“ HYS 72V4220GU-10 PC66-222-920 L-DIM-168-29 66 Mhz 4M x 72 2 bank SDRAM module 1,25“ Pin Names A0-A10 BA DQ0 - DQ63 CB0-CB7 Address Inputs Bank Address Data Input/Output Check Bits (x72 organisation only) RAS Row Address Strobe CAS Column Address Strobe Read / Write Input WE CKE0, CKE1 Clock Enable CLK0 - CLK3 DQMB0 - DQMB7 CS0 - CS3 Vcc Vss SCL SDA N.C. Clock Input Data Mask Chip Select Power (+3.3 Volt) Ground Clock for Presence Detect Serial Data Out for Presence Detect No Connection Address Format: 2M x 64 2M x 72 4M x 64 4M x 72 Part Number HYS 64V2200GU HYS 72V2200GU HYS 64V4220GU HYS 72V4220GU Semiconductor Group Rows 11 11 11 11 Columns 9 9 9 9 2 Banks 1 1 1 1 Refresh 4k 4k 4k 4k Period 64 ms 64 ms 64 ms 64 ms Interval 15,6 µs 15,6 µs 15,6 µs 15,6 µs HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Pin Configuration PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Symbol VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 NC (CB0) NC (CB1) VSS NC NC VCC WE DQMB0 DQMB1 CS0 DU VSS A0 A2 A4 A6 A8 A10 NC VCC VCC CLK0 PIN # 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Symbol PIN # VSS DU CS2 DQMB2 DQMB3 DU VCC NC NC NC (CB2) NC (CB3) VSS DQ16 DQ17 DQ18 DQ19 VCC DQ20 NC DU CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS CLK2 NC WP SDA SCL VCC 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Note : Pinnames in brackets are for the x72 ECC versions Semiconductor Group 3 Symbol VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 NC (CB4) NC (CB5) VSS NC NC VCC CAS DQMB4 DQMB5 CS1 RAS VSS A1 A3 A5 A7 A9 BA NC VCC CLK1 NC PIN # 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Symbol VSS CKE0 CS3 DQMB6 DQMB7 NC VCC NC NC CB6 CB7 VSS DQ48 DQ49 DQ50 DQ51 VCC DQ52 NC DU NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS CLK3 NC SA0 SA1 SA2 VCC HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules WE CS0 CS WE CS WE DQMB0 DQM DQ(7:0) DQ0-DQ7 DQMB4 DQM DQ(39:32) DQ0-DQ7 D4 D0 CS WE DQMB1 DQM DQ(15:8) DQ0-DQ7 CS WE DQM DQMB5 DQ0-DQ7 DQ(47:40) D1 D5 CS WE DQM CB(7:0) DQ0-DQ7 D8 CS2 DQMB2 DQ(23:16) CS WE CS WE DQM DQ0-DQ7 D2 DQMB6 DQM DQ(55:48) DQ0-DQ7 DQMB7 DQM DQ(63:56) DQ0-DQ7 D6 CS WE DQMB3 DQ(31:24) A0-A10,BA CS WE DQM DQ0-DQ7 D3 D7 E2PROM (256wordx8bit) D0 - D7,(D8) VCC D0 - D7,(D8) C0-C7,(C8) VSS D0 - D7,(D8) RAS D0 - D7,(D8) CAS D0 - D7,(D8) CKE0 D0 - D7,(D8) CLK0 CLK1 CLK2 CLK3 Note: D8 is only used in the x72 ECC version SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP Clock Wiring 2M x 64 2M x 72 4 SDRAM+3.3pF 5 SDRAM Termination Termination 4 SDRAM+3.3pF 4 SDRAM+3.3pF Termination Termination Block Diagram for 2M x 64/72 SDRAM DIMM modules (HYS64/72V2200GU) Semiconductor Group 4 47k HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules CS1 CS0 CS CS CS CS DQMB0 DQM DQM DQMB4 DQM DQM DQ(7:0) DQ0-DQ7 D0 DQ0-DQ7 D8 DQ(39:32) DQ0-DQ7 D4 DQ0-DQ7 D12 DQMB1 DQM DQMB5 DQM DQ(15:8) DQ0-DQ7 DQ0-DQ7 D1 D9 DQ(47:40) DQ0-DQ7 DQ0-DQ7 D5 D13 CS CS DQM CS CS DQM DQ0-DQ7 D16 DQ0-DQ7 D17 DQM CB(7:0) CS CS DQM CS3 CS2 CS CS CS CS DQMB2 DQM DQM DQMB6 DQM DQM DQ(23:16) DQ0-DQ7 D2 DQ0-DQ7 D10 DQ(55:48) DQ0-DQ7 D6 DQ0-DQ7 D14 DQMB3 DQM DQM DQMB7 DQM DQM DQ(31:24) DQ0-DQ7 D3 DQ0-DQ7 D11 DQ(63:56) DQ0-DQ7 D7 DQ0-DQ7 D15 CS CS VDD D0 - D15,(D16,D17) C0-C31,(C32..C35) D0 - D7,(D8) RAS, CAS, WE CKE0 SA0 SA1 SA2 SCL SA0 SA1 SA2 SCL SDA WP 47k D0 - D15,(D16,D17) D0 - D7,(D16) CLK0 CLK1 CLK2 CLK3 VDD 10k CKE1 CS E2PROM (256wordx8bit) D0 - D15,(D16,D17) A0-A10,BA VSS CS D9 - D15,(D17) Clock Wiring 4M x 64 4M x 72 4 SDRAM+3.3pF 5 SDRAM 4 SDRAM+3.3pF 5 SDRAM 4 SDRAM+3.3pF 4 SDRAM+3.3pF 4 SDRAM+3.3pF 4 SDRAM+3.3pF Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ohms except otherwise noted. Block Diagram for 4M x 64/72 SDRAM DIMM modules (HYS64/72V4220GU) Semiconductor Group 5 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V Parameter Symbol Limit Values Unit min. max. Input high voltage VIH 2.0 Vcc+0.3 V Input low voltage VIL – 0.5 0.8 V Output high voltage ( IOUT = – 2.0 mA) VOH 2.4 – V Output low voltage ( IOUT = 2.0 mA) VOL – 0.4 V Input leakage current, any input (0 V < VIN < 3.6 V, all other inputs = 0 V) II(L) – 40 40 µA Output leakage current (DQ is disabled, 0 V < VOUT < VCC) IO(L) – 40 40 µA Capacitance TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz Parameter Symbol Limit Values Unit max. max. max. max. 2Mx64 2Mx72 4Mx64 4Mx72 CI1 45 55 80 90 pF Input capacitance (CS0 -CS3 ) CI2 20 25 30 35 pF Input capacitance ( CLK0 - CLK3) CICL 22 38 22 38 pF Input capacitance (CKE0, CKE1) CI3 22 38 50 55 pF Input capacitance (DQMB0 - DQMB7) CI4 13 13 20 20 pF Input / Output capacitance CIO 13 12 20 20 pF Input Capacitance (SCL,SA0-2) Csc 8 8 8 8 pF Input/Output Capacitance Csd 10 10 10 10 pF Input capacitance (A0 to A10, BA, RAS, CAS, WE) (DQ0-DQ63,CB0-CB7) Semiconductor Group 6 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Standby and Refresh Currents (Ta = 0 to 70 oC, VCC = 3.3V ± 0.3V) 1) Parameter Symbol Test Condition X64 X72 Note max. 800 900 mA CKE<=VIL(max), tck>=tck(min.) 24 27 mA CKE<=VIL(max), tck=infinite 16 18 mA 160 180 mA CS= High CKE>=VIH(min), tck=infinite, no input change 80 90 mA CKE<=VIL(max), tck>=tck(min.) 24 27 mA CKE<=VIL(max), tck=infinite 16 18 mA CKE>=VIH(min), tck>=tck (min.) input changed one time 200 225 mA CS= High Icc3NS CKE=>VIH(min),tck=infinite, no input change 120 135 mA Burst Operating Current Icc4 Burst length = full page, trc = infinite, CL = 3, tck>=tck (min.), Io = 0 mA 2 banks activated 760 855 mA 1,2 Auto (CBR) Refresh Current Icc5 trc>=trc(min) 720 810 mA 1,2 Self Refresh Current Icc6 CKE=<0,2V 16 18 mA 1,2 Operating Current Precharged Standby Current in Power Down Mode Precharged Standby Current in Nonpower Down Mode Active Standby Current in Power Down Mode Active Standby Current in Nonpower Down Mode Semiconductor Group Icc1 Icc2P Icc2PS Icc2N Icc2NS Icc3P Icc3PS Icc3N Burst length = 4, CL=3 trc>=trc(min.), tck>=tck(min.), Io=0 mA 2 bank interleave operation CKE>=VIH(min), tck>=tck (min.), input changed once in 3 cycles 7 1,2 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules AC Characteristics 3)4) TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns Parameter Limit Values Symbol -8 PC100 2-2-2 Unit -8-3 PC100 3-2-3 Note -10 PC66 2-2-2 min. max. min. max. min. max. Clock and Clock Enable Clock Cycle Time tCK CAS Latency = 3 CAS Latency = 2 10 10 fCK System Frequency CAS Latency = 3 CAS Latency = 2 – – 100 100 – – 100 100 – – 100 66 tAC Clock Access Time CAS Latency = 3 CAS Latency = 2 – – 6 6 – – 6 7 – – 8 9 ns ns 4,5) Clock High Pulse Width tCH 3 – 3 – 3.5 – ns 6) Clock Low Pulse Width tCL 3 – 3 – 3.5 – ns 6) Input Setup time tCS 2 – 2 – 3 – ns 7) Input Hold Time tCH 1 – 1 – 1 – ns 7) CKE Setup Time (Power down mode) tCKSP 2.5 – 2.5 – 3 – ns 8) CKE Setup Time (Self Refresh Exit) tCKSR 8 – 8 – 8 – ns 9) Transition time (rise and fall) tT 1 – 1 – 1 – ns RAS to CAS delay tRCD 20 – 20 – 30 – ns Cycle Time tRC 70 120k 70 120k 75 Active Command Period tRAS 45 – 45 – 45 – ns Precharge Time tRP 20 – 30 – 30 – ns Bank to Bank Delay Time tRRD 16 – 20 – 20 – ns CAS to CAS delay time (same bank) tCCD 1 – 1 – 1 – CLK 10 10 10 15 ns ns MHz MHz Common Parameters Semiconductor Group 8 120k ns HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Parameter Limit Values Symbol -8 PC100 2-2-2 -8-3 PC100 3-2-3 Unit Note -10 PC66 2-2-2 min. max. min. max. min. max. Refresh Cycle Self Refresh Exit Time tSREX 10 – 10 – 10 – ns 9) Refresh Period (4096 cycles) tREF 64 – 64 – 64 – ms 8) Data Out Hold Time tOH 3 – 3 – 3 – ns 4) Data Out to Low Impedance Time tLZ 0 – 0 – 0 – ns Data Out to High Impedance Time tHZ 3 9 3 9 3 9 ns DQM Data Out Disable Latency tDQZ 2 – 2 – 2 – CLK Data input to Precharge (write recovery) tDPL 2 – 2 – 2 – CLK Data In to Active/refresh tDAL 5 – 5 – 5 – CLK DQM Write Mask Latency tDQW 0 – 0 – 0 – CLK Read Cycle 10) Write Cycle Semiconductor Group 9 11) HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules Notes: 1. The specified values are valid when addresses are changed no more than once during tck(min.) and when No Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module bank. 2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.). 3. All AC characteristics are shown for device level. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin. 4. AC timing tests have V il = 0.4 V and V ih = 2.4 V with the timing referenced to the 1.4 V crossover point. The transition time is measured between V ih and Vil. All AC measurements assume t T=1ns with the AC output load circuit show. Specified tac and toh parameters are measured with a 50 pF only, without any resistive termination and with a input signal of 1V / ns edge rate between 0.8V and 2.0 V. tCH + 1.4 V 2.4 V CLOCK 50 Ohm 0.4 V tCL tSETUP tT Z=50 Ohm tHOLD I/O 50 pF 1.4V INPUT tAC tAC tLZ I/O tOH 50 pF 1.4V OUTPUT Measurement conditions for tac and toh tHZ fig.1 If clock rising time is longer than 1ns, a time (t T/2 -0.5) ns has to be added to this parameter. Rated at 1.5 V If tT is longen than 1 ns, a time (t T -1) ns has to be added to this parameter. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to “wake-up“the device. 9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied once the Self Refresh Exit command is registered. 10.Referenced to the time which the output achieves the open circuit condition, not to output voltage levels. 11.tDAL is equivalent to t DPL + tRP. 5. 6. 7. 8. Semiconductor Group 10 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules A serial presence detect storage device - E 2PROM - is assembled onto the module. Information about the module configuration, speed, etc. is written into the E 2PROM device during module production using a serial presence detect protocol ( I 2C synchronous 2-wire bus) SPD-Table: Byte# Description SPD Entry Value 0 1 2 3 4 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 11 9 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD Semiconductor Group Hex 2Mx64 2Mx72 4Mx64 4Mx72 -8 -8 -8 -8 80 80 80 80 08 08 08 08 04 04 04 04 0B 0B 0B 0B 09 09 09 09 1/2 64 / 72 0 LVTTL 10.0 ns 6.0 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 tccd = 1 CLK 01 40 00 01 A0 60 00 80 01 48 00 01 A0 60 02 80 02 40 00 01 A0 60 00 80 02 48 00 01 A0 60 02 80 08 00 01 08 08 01 08 00 01 08 08 01 1, 2, 4, 8 & full page 2 CAS lat. = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 10.0 ns 6.0 ns not supported not supported 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 06 A0 60 FF FF 06 A0 60 FF FF 06 A0 60 FF FF 06 A0 60 FF FF 20 ns 16 ns 14 10 14 10 14 10 14 10 11 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules SPD-Table (cont’d): Byte# Description SPD Entry Value 29 30 31 32 33 34 35 36-61 Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Frequency Specification 127 Details of 100 MHz Support 128+ Unused storage locations Semiconductor Group 20 ns 45 ns 16 MByte 2 ns 1 ns 2 ns 1 ns 12 Hex 2Mx64 2Mx72 4Mx64 4Mx72 -8 -8 -8 -8 14 14 14 14 2D 2D 2D 2D 04 04 04 04 20 20 20 20 10 10 10 10 20 20 20 20 10 10 10 10 FF FF FF FF Revision 1.2 12 C9 XX 12 DB XX 12 CA XX 12 DC XX 100 MHz 64 AF FF 64 AF FF 64 FF FF 64 FF FF HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules SPD-Table: Byte# Description SPD Entry Value 0 1 2 3 4 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 11 9 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD Semiconductor Group Hex 2Mx64 2Mx72 4Mx64 4Mx72 -8-3 -8-3 -8-3 -8-3 80 80 80 80 08 08 08 08 04 04 04 04 0B 0B 0B 0B 09 09 09 09 1/2 64 / 72 0 LVTTL 10.0 ns 6.0 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 tccd = 1 CLK 01 40 00 01 A0 60 00 80 01 48 00 01 A0 60 02 80 02 40 00 01 A0 60 00 80 02 48 00 01 A0 60 02 80 08 00 01 08 08 01 08 00 01 08 08 01 1, 2, 4, 8 & full page 2 CAS lat. = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 10.0 ns 7.0 ns not supported not supported 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 06 A0 70 FF FF 06 A0 70 FF FF 06 A0 70 FF FF 06 A0 70 FF FF 30 ns 20 ns 1E 14 1E 14 1E 14 1E 14 13 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules SPD-Table (cont’d): Byte# Description SPD Entry Value 29 30 31 32 33 34 35 36-61 Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Frequency Specification 127 Details of 100 MHz Support 128+ Unused storage locations Semiconductor Group 20 ns 45 ns 16 MByte 2 ns 1 ns 2 ns 1 ns 14 Hex 2Mx64 2Mx72 4Mx64 4Mx72 -8-3 -8-3 -8-3 -8-3 14 14 14 14 2D 2D 2D 2D 04 04 04 04 20 20 20 20 10 10 10 10 20 20 20 20 10 10 10 10 FF FF FF FF Revision 1.2 12 E7 XX 12 F9 XX 12 E8 XX 12 FA XX 100 MHz 64 AD FF 64 AD FF 64 FD FF 64 FD FF HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules SPD-Table: Byte# Description SPD Entry Value 0 1 2 3 4 Number of SPD bytes Total bytes in Serial PD Memory Type Number of Row Addresses (without BS bits) Number of Column Addresses (for x8 SDRAM) Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL=3 SDRAM Access time from Clock at CL=3 Dimm Config (Error Det/Corr.) Refresh Rate/Type 128 256 SDRAM 11 9 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 SDRAM width, Primary Error Checking SDRAM data width Minimum clock delay for back-to-back random column address Burst Length supported Number of SDRAM banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM module attributes SDRAM Device Attributes :General Min. Clock Cycle Time at CAS Latency = 2 Max. data access time from Clock for CL=2 Minimum Clock Cycle Time at CL = 1 Maximum Data Access Time from Clock at CL=1 Minimum Row Precharge Time Minimum Row Active to Row Active delay tRRD Semiconductor Group Hex 2Mx64 2Mx72 4Mx64 4Mx72 -10 -10 -10 -10 80 80 80 80 08 08 08 08 04 04 04 04 0B 0B 0B 0B 09 09 09 09 1/2 64 / 72 0 LVTTL 10.0 ns 8.0 ns none / ECC Self-Refresh, 15.6µs x8 n/a / x8 tccd = 1 CLK 01 40 00 01 A0 80 00 80 01 48 00 01 A0 80 02 80 02 40 00 01 A0 80 00 80 02 48 00 01 A0 80 02 80 08 00 01 08 08 01 08 00 01 08 08 01 1, 2, 4, 8 & full page 2 CAS lat. = 2 & 3 CS latency = 0 Write latency = 0 non buffered/non reg. Vcc tol +/- 10% 15.0 ns 9.0 ns not supported not supported 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 8F 02 06 01 01 00 06 F0 90 FF FF 06 F0 90 FF FF 06 F0 90 FF FF 06 F0 90 FF FF 30 ns 20 ns 1E 14 1E 14 1E 14 1E 14 15 HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules SPD-Table (cont’d): Byte# Description SPD Entry Value 29 30 31 32 33 34 35 36-61 Minimum RAS to CAS delay tRCD Minimum RAS pulse width tRAS Module Bank Density (per bank) SDRAM input setup time SDRAM input hold time SDRAM data input setup time SDRAM data input hold time Superset information (may be used in future) 62 SPD Revision 63 Checksum for bytes 0 - 62 64- Manufacturers information (optional) 125 (FFh if not used) 126 Frequency Specification 127 Details 128+ Unused storage locations Semiconductor Group 30 ns 45 ns 16 MByte 3 ns 1 ns 3 ns 1 ns 16 Hex 2Mx64 2Mx72 4Mx64 4Mx72 -10 -10 -10 -10 1E 1E 1E 1E 2D 2D 2D 2D 04 04 04 04 30 30 30 30 10 10 10 10 30 30 30 30 10 10 10 10 FF FF FF FF Revision 1.2 12 A1 XX 12 B3 XX 12 A2 XX 12 B4 XX 66 MHz 66 AF FF 66 AF FF 66 FF FF 66 FF FF HYS64(72)V2200/4220GU-8/-10 SDRAM-Modules L-DIM-168-29 SDRAM DIMM Module package 133,35 127,35 3,0 1 10 11 40 84 41 17,78 x) 31.75 4,0 42,18 66,68 A 85 C B 94 95 124 125 168 x) D 6,35 6,35 Detail A 8.25 4.45 2,0 2.26 1,0 + - 0.5 2,54 min. 3,125 3,125 1,27 2,0 0,2 + - 0,15 Detail C Detail B DM168-29.WMF RADIUS x) on ECC modules only 1.27 + 0.10 Detail D Semiconductor Group 17