HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules 512 MByte & 1024 MByte Modules PC1600, PC2100 & PC2700 Preliminary datasheet rev. 0.81 • Auto Refresh (CBR) and Self Refresh • 184-pin Unbuffered 8-Byte Dual-In-Line DDR-I SDRAM non-parity and ECC-Modules for PC and Server main memory applications • All inputs and outputs SSTL_2 compatible • Serial Presence Detect with E2PROM • One bank 64M x 64, 64M x 72 and two bank 128M x 64, 128M × 72 organization • Jedec standard MO-206 form factor: 133.35 mm × 31.75 mm × 4.00 mm max. • JEDEC standard Double Data Rate Synchronous DRAMs (DDR-I SDRAM) Single + 2.5 V (± 0.2 V) power supply • Jedec standard reference layout • Gold plated contacts • Built with 512 Mbit DDR-I SDRAMs organized as 64Mb x 8 in 66-Lead TSOPII package • Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) • Performance: -6 -7 -8 Unit Component Speed Grade DDR333B DDR266A DDR200 Module Speed Grade PC2700 PC2100 PC1600 fCK Clock Frequency (max.) @ CL = 2.5 166 143 125 MHz fCK Clock Frequency (max.) @ CL = 2 133 133 100 MHz The HYS64/72D64000GU and HYS64/72D128020GU are industry standard 184-pin 8-byte Dual in-line Memory Modules (DIMMs) organized as 64M × 64 and 128M × 64 for non-parity and 64M x 72 and 128M x 72 for ECC main memory applications. The memory array is designed with 512Mbit Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. INFINEON Technologies 1 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules Ordering Information Type Compliance Code Description SDRAM Technology PC2700 (CL=2.5): HYS64D128320GU-6-A PC2700-25330-B1 two banks 1024 MB DIMM 512 MBit HYS72D128320GU-6-A PC2700-25330-B1 two banks 1024 MB ECC-DIMM 512 MBit HYS64D64000GU-7-A PC2100-20330-A1 one bank 512 MB DIMM 512 MBit HYS72D64000GU-7-A PC2100-20330-A1 one bank 512 MB ECC-DIMM 512 Mbit HYS64D128020GU-7-A PC2100-20330-B1 two banks 1024 MB DIMM 512 MBit HYS72D128020GU-7-A PC2100-20330-B1 two banks 1024 MB ECC-DIMM 512 MBit HYS64D64000GU-8-A PC1600-20220-A1 one bank 512 MB DIMM 512 MBit HYS72D64000GU-8-A PC1600-20220-A1 one bank 512 MB ECC-DIMM 512 Mbit PC2100 (CL=2): PC1600 (CL=2): HYS64D128020GU-8-A PC1600-20220-B1 two banks 1024 MB DIMM 512 MBit HYS72D128020GU-8-A PC1600-20220-B1 two banks 1024 MB ECC-DIMM 512 MBit Note: All part numbers end with a place code, designating the silicon-die revision. Reference information available on request. Example: HYS 72D64000GU-8-A, indicating Rev.A dies are used for the SDRAM components. The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card used for this module. INFINEON Technologies 2 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Pin Definitions and Functions A0 - A12 Address Inputs S0, S1 Chip Selects BA0, BA1 Bank Selects VDD Power (+ 2.5 V) DQ0 - DQ63 Data Input/Output VSS Ground CB0 - CB7 Check Bits (x72 organization only) VDDQ I/O Driver power supply RAS Row Address Strobe VDDID VDD Indentification flag CAS Column Address Strobe VREF I/O reference supply WE Read/Write Input VDDSPD Serial EEPROM power supply CKE0 - CKE1 Clock Enable SCL Serial bus clock DQS0 - DQS8 SDRAM low data strobes SDA Serial bus data line CLK0 - CLK2, SDRAM clock (positive lines) SA0 - SA2 slave address select CLK0 - CLK2 SDRAM clock (negative lines) NC no connect DM0 - DM8 DQS9 - DQS17 SDRAM low data mask/ high data strobes note: S1 and CKE1 are used on two bank modules only Address Format Density Organization Memory Banks SDRAMs # of SDRAMs # of row/bank/ columns bits Refresh Period Interval 512 MB 64M x 64 1 64M x 8 8 13/2/11 8k 64 ms 7.8 µs 512 MB 64M x 72 1 64M x 8 9 13/2/11 8k 64 ms 7.8 µs 1024 MB 128M × 64 2 64M x 8 16 13/2/11 8k 64 ms 7.8 µs 1024 MB 128M × 72 2 64M x 8 18 13/2/11 8k 64 ms 7.8 µs INFINEON Technologies 3 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules Pin Configuration PIN# Frontside Symbol PIN# Frontside Symbol PIN# Backside Symbol PIN# Backside Symbol 1 2 VREF DQ0 48 49 A0 NC / CB2 93 94 VSS DQ4 140 141 NC / DM8/DQS17 A10 3 4 VSS DQ1 50 51 VSS NC / CB3 95 96 DQ5 VDDQ 142 143 NC / CB6 VDDQ 5 6 DQS0 DQ2 52 BA1 KEY 97 98 DM0/DQS9 DQ6 144 NC / CB7 KEY 7 8 VDD DQ3 53 54 DQ32 VDDQ 99 100 DQ7 VSS 145 146 VSS DQ36 9 10 NC NC 55 56 DQ33 DQS4 101 102 NC NC 147 148 DQ37 VDD 11 12 VSS DQ8 57 58 DQ34 VSS 103 104 NC VDDQ 149 150 DM4/DQS13 DQ38 13 14 DQ9 DQS1 59 60 BA0 DQ35 105 106 DQ12 DQ13 151 152 DQ39 VSS 15 16 VDDQ CLK1 61 62 DQ40 VDDQ 107 108 DM1/DQS10 VDD 153 154 DQ44 RAS 17 CLK1 63 WE 109 DQ14 155 DQ45 18 19 VSS DQ10 64 65 DQ41 CAS 110 111 DQ15 CKE1 156 157 VDDQ S0 20 21 DQ11 CKE0 66 67 VSS DQS5 112 113 VDDQ NC (BA2) 158 159 S1 DM5/DQS14 22 23 VDDQ DQ16 68 69 DQ42 DQ43 114 115 DQ20 NC / A12 160 161 VSS DQ46 24 25 DQ17 DQS2 70 71 VDD NC 116 117 VSS DQ21 162 163 DQ47 NC 26 27 VSS A9 72 73 DQ48 DQ49 118 119 A11 DM2/DQS11 164 165 VDDQ DQ52 28 29 DQ18 A7 74 75 VSS CLK2 120 121 VDD DQ22 166 167 DQ53 NC (A13) 30 31 VDDQ DQ19 76 77 CLK2 VDDQ 122 123 A8 DQ23 168 169 VDD DM6/DQS15 32 33 A5 DQ24 78 79 DQS6 DQ50 124 125 VSS A6 170 171 DQ54 DQ55 34 35 VSS DQ25 80 81 DQ51 VSS 126 127 DQ28 DQ29 172 173 VDDQ NC 36 37 DQS3 A4 82 83 VDDID DQ56 128 129 VDDQ DM3/DQS12 174 175 DQ60 DQ61 38 39 VDD DQ26 84 85 DQ57 VDD 130 131 A3 DQ30 176 177 VSS DM7/DQS16 40 41 DQ27 A2 86 87 DQS7 DQ58 132 133 VSS DQ31 178 179 DQ62 DQ63 42 43 VSS A1 88 89 DQ59 VSS 134 135 NC / CB4 NC / CB5 180 181 VDDQ SA0 44 45 NC / CB0 NC / CB1 90 91 NC SDA 136 137 VDDQ CK0 182 183 SA1 SA2 46 47 VDD NC / DQS8 92 SCL 138 139 CK0 VSS 184 VDDSPD Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC modules. INFINEON Technologies 4 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules S0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS CS D0 DQS D4 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DQS D5 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DQS3 DM3/DQS12 DQS D6 DQS7 DM7/DQS16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQS D7 * Clock Wiring Serial PD SDA SCL A0 A1 A2 SA0 SA1 SA2 BA0 - BA1 BA0, BA1: SDRAMs D0 - D7 A0 -A11, A12 A0 - A11,A12: SDRAMs D0 - D7 RAS VDD, VDDQ D0 - D7 VREF D0 - D7 VSS D0 - D7 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 2 SDRAMs 3 SDRAMs 3 SDRAMs * Wire per Clock Loading Table/W iring Diagrams RAS: SDRAMs D0 - D7 CAS CAS: SDRAMs D0 - D7 CKE0 CKE: SDRAMs D0 - D7 WE WE : SDRAMs D0 - D7 VDDID Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: One Bank 64M x 64 DDR-I SDRAM DIMM Module HYS64D64000GU using x8 organized SDRAMs INFINEON Technologies 5 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS D4 CS DQS D12 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS D5 CS DQS D13 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS D6 CS DQS D14 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS D7 CS DQS D15 * Clock Wiring BA0, BA1 BA0, BA1: SDRAMs D0, D15 A0 - A12 A0 - A12: SDRAMs D0 - D15 VDD, VDDQ VREF VSS Serial PD SDA D0 - D15 SCL A0 A1 A2 SA0 SA1 SA2 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 4 SDRAMs 6 SDRAMs 6 SDRAMs * W ire per Clock Loading Table/Wiring Diagrams D0 - D15 D0 - D15 VDDID CKE1 CKE: SDRAMs D8 - D15 RAS RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 CKE0 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: Two Bank 128M x 64 DDR-I SDRAM DIMM Modules HYS64D128020GU using x8 Organized SDRAMs INFINEON Technologies 6 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules S0 DQS0 DM0/DQS9 DQS4 DM4/DQS13 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DQS D0 DQS D4 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D1 DQS D5 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D2 DQS3 DM3/DQS12 DQS D6 DQS7 DM7/DQS16 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D3 DQS D7 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS SDA SCL BA0, BA1 BA0, BA1: SDRAMs D0 - D8 A0 - A11,A12 A0 - A11, A12: SDRAMs D0 - D8 VDD, VDDQ VREF VSS Serial PD DQS D8 D0 - D8 D0 - D8 D0 - D8 A0 A1 A2 SA0 SA1 SA2 * Clock Wiring RAS RAS: SDRAMs D0 - D8 CAS CAS: SDRAMs D0 - D8 CKE0 CKE: SDRAMs D0 - D8 WE WE: SDRAMs D0 - D8 VDDID Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 3 SDRAMs 3 SDRAMs 3 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: One Bank 64M x 72 DDR-I SDRAM DIMM Module HYS72D64000GU using x8 organized SDRAMs INFINEON Technologies 7 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules S1 S0 DQS4 DM4/DQS13 DQS0 DM0/DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D0 CS DQS D9 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS CS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D1 CS DQS D10 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D2 CS DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D11 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D15 DQS7 DM7/DQS16 DQS3 DM3/DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS D4 DQS6 DM6/DQS15 DQS2 DM2/DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQS5 DM5/DQS14 DQS1 DM1/DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 D3 CS DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D12 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D7 CS DQS D16 DQS8 DM8/DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D8 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D17 * Clock Wiring BA0, BA1 BA0, BA1: SDRAMs D0 - D17 A0 - A12 A0 - A12: SDRAMs D0 - D17 Serial PD SDA VDD, VDDQ VREF VSS D0 - D17 SCL D0 - D17 A0 A1 A2 SA0 SA1 SA2 Clock Input SDRAMs *CK0/CK0 *CK1/CK1 *CK2/CK2 6 SDRAMs 6 SDRAMs 6 SDRAMs * Wire per Clock Loading Table/Wiring Diagrams D0 - D17 VDDID CKE1 CKE: SDRAMs D9 - D17 RAS RAS: SDRAMs D0 - D17 CAS CAS: SDRAMs D0 - D17 CKE0 CKE: SDRAMs D0 - D8 WE WE: SDRAMs D0 - D17 Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/S relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms. 4. VDDID strap connections (for memory device VDD, VDDQ): STRAP OUT (OPEN): VDD = VDDQ Block Diagram: Two Bank 128M x 72 DDR-I SDRAM DIMM Modules HYS72D128020GU using x8 Organized SDRAMs INFINEON Technologies 8 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Clock Net Wiring 4 DRAM Loads 6 DRAM Loads DR AM 1 DR AM 1 DRAM2 CK DRAM2 R = 120 R =120 DRAM3 DIMM Connector Cap. DIMM Connector CK DR AM4 Cap. DR AM5 DR AM5 DR AM6 DRAM6 DR AM 1 3 DRAM Loads 2 DRAM Loads DR AM 1 Cap. Cap. R =120 R =120 Cap. DIMM Connector DR AM3 DIMM Connector Cap. Cap. DR AM5 DR AM5 Cap. Cap. Absolute Maximum Ratings Parameter Symbol Limit Values min. max. Unit Input / Output voltage relative to VSS VIN, VOUT – 0.5 3.6 V Power supply voltage on VDD/VDDQ to VSS VDD, VDDQ – 0.5 3.6 V Storage temperature range TSTG -55 +150 o Power dissipation (per SDRAM component) PD – 1 W Data out current (short circuit) IOS – 50 mA C Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded. Functional operation should be restricted to recommended operation conditions. Exposure to higher than recommended voltage for extended periods of time affect device reliability INFINEON Technologies 9 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules Supply Voltage Levels Parameter Symbol Limit Values min. nom. max. Unit Notes Device Supply Voltage VDD 2.3 2.5 2.7 V – Output Supply Voltage VDDQ 2.3 2.5 2.7 V 1) Input Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 2) Termination Voltage VTT VREF – 0.04 VREF VREF + 0.04 V 3) EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V 1) 2) 3) Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. VTT of the transmitting device must track VREF of the receiving device. DC Operating Conditions (SSTL_2 Inputs) (VDDQ = 2.5 V, TA = 70 °C, Voltage Referenced to VSS ) Parameter Symbol Limit Values min. Unit Notes max. DC Input Logic High VIH (DC) VREF + 0.15 VDDQ + 0.3 V 1) DC Input Logic Low VIL (DC) – 0.30 VREF – 0.15 V – Input Leakage Current IIL –5 5 µA 2) Output Leakage Current IOL –5 5 µA 2) 1) 2) The relationship between the VDDQ of the driving device and the VREF of the receiving device is what determines noise margins. However, in the case of VIH (max) (input overdrive), it is the VDDQ of the receiving device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but has no SSTL_2 outputs (such as a translator), and therefore no VDDQ supply voltage connection, inputs must tolerate input overdrive to 3.0 V (High corner VDDQ + 300 mV). For any pin under test input of 0 V ≤ VIN ≤ VDDQ + 0.3 V. Values are shown per DDR-SDRAM component. INFINEON Technologies 10 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Operating, Standby and Refresh Currents (PC1600) 512MB x64 1bank -8 512MB x72 1bank -8 1GB x64 2bank -8 1GB x72 2bank -8 Unit Notes Symbol Parameter/Condition MAX MAX MAX MAX IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1280 1440 1680 1890 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 1360 1530 1760 1980 mA 1, 3 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN 96 108 192 216 mA 2 IDD2F Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. 320 360 640 720 mA 2 IDD2Q Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. 200 225 400 450 mA 2 IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. 128 144 256 288 mA 2 IDD3N Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 400 450 800 900 mA 2 IDD4R Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1320 1485 1720 1935 mA 1, 3 IDD4W Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN 1280 1440 1680 1890 mA 1 IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 2320 2610 2720 3060 mA 1 IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 40 45 80 90 mA IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 2800 3150 3200 3600 mA 4 1, 3 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 11 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules Operating, Standby and Refresh Currents (PC2100 and PC2700) 512MB 512MB 1GB x64 x64 x72 1bank 1bank 2bank -6 -7 -7 1GB 1GB 1GB x72 x64 x72 2bank 2bank 2bank -6 -7 -7 Unit Notes Symbol Parameter/Condition MAX MAX MAX MAX MAX MAX IDD0 Operating Current: one bank; active / precharge; tRC = tRC MIN; tCK = tCK MIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles 1360 1530 2200 2475 1920 2160 mA 1 IDD1 Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. 1440 1620 2320 2610 2000 2250 mA 1, 3 IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE <= VIL MAX; tCK = tCK MIN 112 126 288 324 224 252 mA 2 IDD2F Precharge Floating Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. 400 450 960 1080 800 900 mA 2 IDD2Q Precharge Quiet Standby Current: /CS >= VIH MIN, all banks idle; CKE >= VIH MIN; tCK = tCK MIN ,address and other control inputs stable at >= VIH MIN or <= VIL MAX; VIN = VREF for DQ, DQS and DM. 224 252 640 720 448 504 mA 2 IDD3P Active Power-Down Standby Current: one bank active; power-down mode; CKE <= VIL MAX; tCK = tCK MIN;VIN = VREF for DQ, DQS and DM. 144 162 368 414 288 324 mA 2 IDD3N Active Standby Current: one bank active; active / precharge;CS >= VIH MIN; CKE >= VIH MIN; tRC = tRAS MAX; tCK = tCK MIN; DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 560 630 1200 1350 1120 1260 mA 2 IDD4R Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN; IOUT = 0mA 1600 1800 2560 2880 2160 2430 mA 1, 3 IDD4W Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200, and DDR266A, CL=3 for DDR333; tCK = tCK MIN 1560 1755 2480 2790 2120 2385 mA 1 IDD5 Auto-Refresh Current: tRC = tRFC MIN, distributed refresh 2480 2790 3280 3690 3040 3420 mA 1 IDD6 Self-Refresh Current: CKE <= 0.2V; external clock on; tCK = tCK MIN 40 45 80 90 80 90 mA IDD7 Operating Current: four bank; four bank interleaving with BL=4; Refer to the following page for detailed test conditions. 3040 3420 3840 4320 3600 4050 mA 4 1, 3 1. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 2. The module IDD values are calculated from the component IDD datasheet values as: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for two bank modules (n: number of components per module bank) 3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 4. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C INFINEON Technologies 12 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol DDR333 -6 Parameter DDR266A -7 DDR200 -8 Unit Notes + 0.8 ns 1-4 + 0.8 ns 1-4 0.45 0.55 tCK 1-4 0.45 0.55 Min Max Min Max Min Max DQ output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 DQS output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 tCH CK high-level width 0.45 0.55 0.45 0.55 tCL CK low-level width 0.45 0.55 0.45 0.55 tHP Clock Half Period tAC tDQSCK tCK tCK 1-4 min (tCL, tCH) min (tCL, tCH) min (t CL, tCH) ns 1-4 CL = 2.5 6 12 7 12 8 12 ns 1-4 CL = 2.0 7.5 12 7.5 12 10 12 ns 1-4 Clock cycle time tCK tDH DQ and DM input hold time 0.45 – 0.5 0.6 ns 1-4 tDS DQ and DM input setup time 0.45 – 0.5 0.6 ns 1-4 tIPW Control and Addr. input pulse width (each input) 2.2 2.2 2.5 ns 1, 10 tDIPW DQ and DM input pulse width (each input) 1.75 1.75 2 ns 1-4, 11 tHZ Data-out high-impedence time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 tLZ Data-out low-impedence time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 − 0.8 + 0.8 ns 1-4, 5 tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 0.75 1.25 tCK 1-4 tDQSQ DQS-DQ skew (for DQS & associated DQ signals) tQHS Data hold skew factor + 0.55 tQH Data Output hold time from DQS + 0.4 – + 0.5 + 0.6 ns 1-4 + 0.75 + 1.0 ns 1-4 tHP-t QHS tHP-tQHS tHP-tQHS ns 1-4 DQS input low (high) pulse width (write cycle) 0.35 0.35 0.35 tCK 1-4 tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 0.2 tCK 1-4 tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 0.2 tCK 1-4 tMRD tDQSL,H Mode register set command cycle time 12 14 16 ns 1-4 tWPRES Write preamble setup time 0 0 0 ns 1-4, 7 tWPST Write postamble 0.40 tCK 1-4, 6 tWPRE Write preamble 0.25 0.25 0.25 tCK 1-4 0.75 0.9 1.1 ns 1.0 1.1 ns 0.75 0.9 1.1 ns tIS Address and control input setup time tIH Address and control input hold time fast slew rate slow slew rate fast slew rate slow slew rate 0.60 0.40 0.60 1.0 0.40 0.60 1.1 2-4, 10,11 ns tRPRE Read preamble 0.9 0.9 1.1 0.9 1.1 tCK 1-4 tRPST Read postamble 0.40 0.40 0.60 0.40 0.60 tCK 1-4 tRAS Active to Precharge command 42 45 120,000 50 120,000 ns 1-4 tRC Active to Active/Auto-refresh command period 60 65 ns 1-4 INFINEON Technologies 13 70 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Electrical Characteristics & AC Timing for DDR-I components (for reference only) (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V) Symbol Parameter DDR333 -6 Min Max DDR266A -7 Min Max DDR200 -8 Min Unit Notes Max tRFC Auto-refresh to Active/Auto-refresh command period 72 75 80 ns 1-4 tRCD Active to Read or Write delay 18 20 20 ns 1-4 tRP Precharge command period 18 20 20 ns 1-4 tRRD Active bank A to Active bank B command 12 15 15 ns 1-4 tWR Write recovery time 15 15 15 ns 1-4 tDAL Auto precharge write recovery + precharge time (twr/tck) + (trp/ tck) (twr/tck) + (trp/ tck) tCK 1-4,9 1-4 tWTR Internal write to read command delay 1 1 1 tCK tXSNR Exit self-refresh to non-read command 75 75 80 ns 1-4 tXSRD Exit self-refresh to read command 200 200 200 tCK 1-4 tREFI Average Periodic Refresh Interval 7.8 µs 1-4, 8 512 Mbit based 7.8 7.8 1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200. 2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are >= 1.0 V/ns. 3. Inputs are not recognized as valid until VREF stabilizes. 4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT. 5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 10. These parameters guarantee device timing, but they are not necessarily tested on each device 11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/ ns, measured between VOH(ac) and VOL(ac) INFINEON Technologies 14 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules SPD Codes for PC1600 Modules “-8” Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 128 256 DDR-SDRAM 13 11 1 /2 x64 / x72 0 SSTL_2.5 8 ns 0.8 ns non-ECC / ECC Self-Refresh, 7.8 ms x8 na / x8 512MB x64 1bank -8 HEX 80 08 07 0D 0B 01 40 00 04 80 80 00 82 08 00 512MB x72 1bank -8 HEX 80 08 07 0D 0B 01 48 00 04 80 80 02 82 08 08 1GB x64 2bank -8 HEX 80 08 07 0D 0B 02 40 00 04 80 80 00 82 08 00 1GB x72 2bank -8 HEX 80 08 07 0D 0B 02 48 00 04 80 80 02 82 08 08 Description tccd = 1 CLK 01 01 01 01 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64 65-71 72 73-90 91-92 93-94 95-98 99-127 Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code Manufacturer Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number – 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered – 10.0 ns 0.8 ns not supported not supported 20 ns 15 ns 20 ns 50 ns 512MByte 1.1 ns 1.1 ns 0.6 ns 0.6 ns – 70 ns 80 ns 12 ns 0.6 ns 1.0 ns Revision 0.0 – – – – – – – – – 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 E8 C1 INFINEON 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 FA C1 INFINEON 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 E9 C1 INFINEON 0E 04 0C 01 02 20 C0 A0 80 00 00 50 3C 50 32 80 B0 B0 60 60 00 46 50 30 3C A0 00 00 FB C1 INFINEON 128-255 open for Customer use – 15 INFINEON Technologies 15 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules SPD Codes for PC2100 & PC2700 Modules “-7” & “-6” Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36-40 41 42 43 44 45 46-61 62 63 64 Description Number of SPD Bytes Total Bytes in Serial PD Memory Type Number of Row Addresses Number of Column Addresses Number of DIMM Banks Module Data Width Module Data Width (cont’d) Module Interface Levels SDRAM Cycle Time at CL = 2.5 Access Time from Clock at CL = 2.5 DIMM Config Refresh Rate/Type SDRAM Width, Primary Error Checking SDRAM Data Width Minimum Clock Delay for Back-to-Back Random Column Address Burst Length Supported Number of SDRAM Banks Supported CAS Latencies CS Latencies WE Latencies SDRAM DIMM Module Attributes SDRAM Device Attributes: General Min. Clock Cycle Time at CAS Latency = 2 Access Time from Clock for CL = 2 Minimum Clock Cycle Time at CL = 1.5 Access Time from Clock at CL = 1.5 Minimum Row Precharge Time Minimum Row Act. to Row Act. Delay tRRD Minimum RAS to CAS Delay tRCD Minimum RAS Pulse Width tRAS Module Bank Density (per bank) Addr. and Command Setup Time Addr. and Command Hold Time Data Input Setup Time Data Input Hold Time Superset Information Minimum Core Cycle Time tRC Min. Auto Refresh Cmd Cycle Time tRFC Maximum Clock Cycle Time tck Max. DQS-DQ Skew tDQSQ X-Factor tQHS Superset Information SPD Revision Checksum for Bytes 0 - 62 Manufacturers JEDEC ID Code 128 256 DDR-SDRAM 13 11 1 /2 x64 / x72 0 SSTL_2.5 7 ns 0.75 ns non-ECC / ECC Self-Refresh, 7.8 ms x8 na / x8 512MB x72 1bank -7 HEX 80 08 07 0D 0B 01 48 00 04 70 75 02 82 08 08 1GB x64 2bank -7 HEX 80 08 07 0D 0B 02 40 00 04 70 75 00 82 08 00 1GB x72 2bank -7 HEX 80 08 07 0D 0B 02 48 00 04 70 75 02 82 08 08 1GB x64 2bank -6 HEX 80 08 07 0D 0B 02 40 00 04 60 70 00 82 08 00 1GB x72 2bank -6 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 08 08 tccd = 1 CLK 01 01 01 01 01 01 2, 4 & 8 4 CAS latency = 2 & 2.5 CS latency = 0 Write latency = 1 unbuffered – 7.5 ns 0.75 ns not supported not supported 20 ns 15 ns 20 ns 45 ns 512MByte 0.9 ns 0.9 ns 0.5 ns 0.5 ns – 65 ns 75 ns 12 ns 0.5 ns 0.75 ns – Revision 0.0 – – 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 F3 C1 INFINEON 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 05 C1 INFINEON 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 F4 C1 INFINEON 0E 04 0C 01 02 20 C0 75 75 00 00 50 3C 50 2D 80 90 90 50 50 00 41 4B 30 32 75 00 00 06 C1 INFINEON 0E 04 0C 01 02 20 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 42 C1 INFINEON 0E 04 0C 01 02 20 C0 75 70 00 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 2D 55 00 00 54 C1 INFINEON 65-71 Manufacturer – 72 73-90 91-92 93-94 95-98 99-127 Module Assembly Location Module Part Number Module Revision Code Module Manufacturing Date Module Serial Number – – – – – – – 128-255 open for Customer use – INFINEON Technologies 512MB x64 1bank -7 HEX 80 08 07 0D 0B 01 40 00 04 70 75 00 82 08 00 16 2002-09-10 (rev.0.81) HYS64/72D64000/128020GU-7/8-A Unbuffered DDR-I SDRAM-Modules Package Outlines -Raw Card A1 (One Bank Modules) DDR-SDRAM DIMM Module Package 133.35 -+ 0.15 4.0 max. 4.0 31.75 + - 0.13 Front View 2.3 typ. *) 52 pin 1 92 53 64.77 1.27 +- 0.1 49.53 2.3 typ. 6.62 Backside View 144 145 184 2.5D 10.0 17.80 pin 93 3 3 *) on ECC modules only Detail of Contacts B 6.35 2.5 -+ 0.20 0.20 +- 0.15 Detail of Contacts A 3.8 typ. 0.9R 1+- 0.05 1.27 1.8 2.175 L-DIM-18429 INFINEON Technologies 17 2002-09-10 (rev.0.81) HYS64/72D64000/128x20GU-7/8-A Unbuffered DDR-I SDRAM-Modules Package Outlines - Raw Card B1 (Two Bank Modules) DDR-SDRAM DIMM Module Package two bank modules 133.35 -+ 0.15 4.0 max. 4.0 31.75 -+ 0.13 Front View 2.3 typ. *) 52 pin 1 92 53 64.77 1.27 -+ 0.1 49.53 2.3 typ. 6.62 Backside View 144 145 184 2.5D 10.0 17.80 pin 93 *) 3 3 *) on ECC modules only Detail of Contacts B 6.35 2.5 +- 0.20 0.20 -+ 0.15 Detail of Contacts A 3.8 typ. 0.9R 1 +- 0.05 1.27 1.8 2.175 L-DIM-1849d INFINEON Technologies 18 2002-09-10 (rev.0.81)