INFINEON HYS72V16200GU-8

3.3 V 16M × 64/72-Bit SDRAM Modules
3.3 V 32M × 64/72-Bit SDRAM Modules
3.3 V 64M × 64/72-Bit SDRAM Modules
HYS 64/72V16200GU
HYS 64/72V32220GU
HYS 64/72V32200GU
HYS 64/72V64220GU
PC100-168 pin unbuffered DIMM Modules
Preliminary Information
• 168 Pin unbuffered 8 Byte Dual-In-Line SDRAM Modules for PC main memory applications
• One bank 16M × 64, 16M × 72, 32M × 64 and 32M × 72 organization
• Two bank 32M × 64, 32M × 72, 64M × 64 and 64M × 72 organization
• Optimized for byte-write non-parity or ECC applications
• Fully PC board layout compatible to INTEL’s Rev. 1.0 module specification
• JEDEC standard Synchronous DRAMs (SDRAM)
• SDRAM Performance:
fCK
Clock frequency (max.)
tAC
Clock access time
-8
-8B
Units
100
100
MHz
6
6
ns
• Programmed Latencies:
Product Speed
CL
tRCD
tRP
-8
PC100
2
2
2
-8B
PC100
3
2
3
• Single + 3.3 V (± 0.3 V) power supply
• Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• Decoupling capacitors mounted on substrate
• All inputs, outputs are LVTTL compatible
• Serial Presence Detect with E2PROM
• Utilizes 32M × 8 SDRAMs in TSOPII-54 packages
• Uses SIEMENS 128Mbit and 256Mbit SDRAM components
• Gold contact pad
• Card Size: 133.35 mm × 31.75 mm × 4.00 mm
Semiconductor Group
1
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
The HYS 64/72V1600, HYS 64/72V32220, HYS 64/72V32200 and HYS 64/72V64220 are industry
standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) which are organized as 16M × 64,
16M × 72, 32M × 64 and 32M × 72 in 1 bank and 32M × 64, 32M × 72, 64M × 64 and 64M × 72 in
two banks high speed memory arrays designed with 128M and 256M Synchronous DRAMs
(SDRAMs) for non-parity and ECC applications. The DIMMs use -8 and -8B speed sort for 16M × 8
and 32M × 8 SDRAM devices in TSOP-54 packages to meet the PC100 requirement. Decoupling
capacitors are mounted on the PC board. The PC board design is according to INTEL’s PC 100
module specification.
The DIMMs have a serial presence detect, implemented with a serial E2PROM using the two pin I2C
protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128 bytes are
available to the end user.
All SIEMENS 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm
long footprint, with 1.25“ (31.75 mm) height.
Ordering Information
Type
Ordering Code
Package
Descriptions
Module
Height
HYS 64V16200GU-8
PC100-222-620
L-DIM-168-30
PC100 16M × 64 1 bank
SDRAM module
1.25“
HYS 72V16200GU-8
PC100-222-620
L-DIM-168-30
PC100 16M × 72 1 bank
SDRAM module
1.25“
HYS 64V32220GU-8
PC100-222-620
L-DIM-168-30
PC100 32M × 64 2 bank
SDRAM module
1.25“
HYS 72V32220GU-8
PC100-222-620
L-DIM-168-30
PC100 32M × 72 2 bank
SDRAM module
1.25“
HYS 64V16200GU-8B
PC100-323-620
L-DIM-168-30
PC100 16M × 64 1 bank
SDRAM module
1.25“
HYS 72V16200GU-8B
PC100-323-620
L-DIM-168-30
PC100 16M × 72 1 bank
SDRAM module
1.25“
HYS 64V32220GU-8B
PC100-323-620
L-DIM-168-30
PC100 32M × 64 2 bank
SDRAM module
1.25“
HYS 72V32220GU-8B
PC100-323-620
L-DIM-168-30
PC100 32M × 72 2 bank
SDRAM module
1.25“
HYS 64V32200GU-8
PC100-222-620
L-DIM-168-30
PC100 32M × 64 1 bank
SDRAM module
1.25“
HYS 72V32200GU-8
PC100-222-620
L-DIM-168-30
PC100 32M × 72 1 bank
SDRAM module
1.25“
HYS 64V64220GU-8
PC100-222-620
L-DIM-168-30
PC100 64M × 64 2 bank
SDRAM module
1.25“
HYS 72V64220GU-8
PC100-222-620
L-DIM-168-30
PC100 64M × 72 2 bank
SDRAM module
1.25“
Semiconductor Group
2
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Ordering Information (cont’d)
Type
Ordering Code
Package
Descriptions
Module
Height
HYS 64V32200GU-8B
PC100-323-620
L-DIM-168-30
PC100 32M × 64 1 bank
SDRAM module
1.25“
HYS 72V32200GU-8B
PC100-323-620
L-DIM-168-30
PC100 32M × 72 1 bank
SDRAM module
1.25“
HYS 64V64220GU-8B
PC100-323-620
L-DIM-168-30
PC100 64M × 64 2 bank
SDRAM module
1.25“
HYS 72V64220GU-8B
PC100-323-620
L-DIM-168-30
PC100 64M × 72 2 bank
SDRAM module
1.25“
Pin Names
A0-A12
Address Inputs
CLK0 - CLK3
(RA0 ~ RA10/CA0 ~ CA9)
Clock Input
BA0, BA1
Bank Selects
DQMB0 - DQMB7
Data Mask
DQ0 - DQ63
Data Input/Output
CS0 - CS3
Chip Select
CB0-CB7
Check Bits
(× 72 organization only)
VCC
Power (+ 3.3 Volt)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
SCL
Clock for Presence Detect
WE
Read/Write Input
SDA
Serial Data Out for Presence
Detect
CKE0, CKE1
Clock Enable
N.C. / DU
No Connection
Address Format
Part Number
Rows Columns Bank
Select
Refresh Period
Interval
16M × 64/72 HYS 64/72V16200GU 12
10
2
4k
64ms
15.6 µ
32M × 64/72 HYS 64/72V32220GU 12
10
2
4k
64ms
15.6 µ
32M × 64/72 HYS 64/72V32220GU 13
10
2
8k
64ms
7.8 µ
64M × 64/72 HYS 64/72V64220GU 13
10
2
8k
64ms
7.8 µ
Semiconductor Group
3
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Pin Configuration
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
PIN #
Symbol
1
2
3
4
5
6
VSS
VSS
DQ32
DQ33
DQ34
DQ35
VCC
127
128
129
130
131
132
VSS
DU
CS2
DQMB2
DQMB3
DU
85
86
87
88
89
90
VSS
VCC
43
44
45
46
47
48
CKE0
CS3
DQMB6
DQMB7
NC
7
DQ4
49
VCC
91
DQ36
133
VCC
8
9
10
11
12
DQ5
DQ6
DQ7
DQ8
NC
NC
NC (CB2)
NC (CB3)
92
93
94
95
96
DQ37
DQ38
DQ39
DQ40
VSS
134
135
136
137
138
NC
NC
CB6
CB7
VSS
50
51
52
53
54
13
14
15
16
17
DQ9
DQ10
DQ11
DQ12
DQ13
55
56
57
58
59
VCC
97
98
99
100
101
DQ41
DQ42
DQ43
DQ44
DQ45
139
140
141
142
143
VCC
18
VCC
60
DQ20
102
VCC
144
DQ52
19
20
21
22
DQ14
DQ15
NC (CB0)
NC (CB1)
61
62
63
64
NC
DU
CKE1
DQ46
DQ47
NC (CB4)
NC (CB5)
145
146
147
148
NC
DU
NC
VSS
103
104
105
106
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
25
26
NC
NC
DQ22
DQ23
108
109
110
NC
NC
VCC
150
151
152
DQ54
DQ55
VCC
66
67
68
27
28
29
30
31
WE
DQMB0
DQMB1
CS0
DU
69
70
71
72
73
CAS
DQMB4
DQMB5
CS1
RAS
153
154
155
156
157
DQ56
DQ57
DQ58
DQ59
VCC
111
112
113
114
115
32
VSS
74
DQ28
116
VSS
158
DQ60
33
34
35
36
A0
A2
A4
A6
75
76
77
78
DQ29
DQ30
DQ31
A1
A3
A5
A7
159
160
161
162
DQ61
DQ62
DQ63
VSS
117
118
119
120
VSS
37
38
39
40
A8
A10
BA1
79
80
81
82
CLK2
NC
WP
SDA
121
122
123
124
A9
BA0
A11
VCC
163
164
165
166
CLK3
NC
SA0
SA1
83
SCL
125
CLK1
167
SA2
84
VCC
126
A12
168
VCC
DQ0
DQ1
DQ2
DQ3
41
VCC
VCC
42
CLK0
VSS
DQ16
DQ17
DQ18
DQ19
VSS
DQ24
DQ25
DQ26
DQ27
VSS
DQ48
DQ49
DQ50
DQ51
VSS
VCC
Note: Pinnames in brackets are for the x72 ECC versions
Semiconductor Group
4
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
WE
CS0
DQMB0
DQ(7:0)
CS
WE
DQM
DQ0-DQ7
D0
DQMB4
DQ(39:32)
CS
WE
DQM
DQ0-DQ7
D4
DQMB1
DQ(15:8)
CS
WE
DQM
DQ0-DQ7
D1
DQMB5
DQ(47:40)
CS
WE
DQM
DQ0-DQ7
D5
CS
WE
DQM
DQ0-DQ7
D8
CB(7:0)
CS2
DQMB2
DQ(23:16)
CS
WE
DQM
DQ0-DQ7
D2
DQMB6
DQ(55:48)
CS
WE
DQM
DQ0-DQ7
D6
DQMB3
DQ(31:24)
CS
WE
DQM
DQ0-DQ7
D3
DQMB7
DQ(63:56)
CS
WE
DQM
DQ0-DQ7
D7
A0-A11, (A12), BA0, BA1
VCC
E 2 PROM (256 word x 8 Bit)
D0-D7, (D8)
SA0
SA1
SA2
SCL
D0-D7, (D8)
C
VSS
D0-D7, (D8)
RAS
D0-D7, (D8)
CAS
D0-D7, (D8)
CKE0
SA0
SA1
SA2
SCL
SDA
WP
47 k Ω
Clock Wiring
D0-D7, (D8)
CLK0
CLK1
CLK2
CLK3
Note: D8 is only used in the x72 ECC version.
32 M x 64
32 M x 72
4 SDRAM + 3.3 pF
Termination
4 SDRAM + 3.3 pF
Termination
5 SDRAM
Termination
4 SDRAM + 3.3 pF
Termination
SPB03970
Block Diagram for 16M × 64/72 & 32M × 64/72 one bank SDRAM DIMM Modules
(HYS 64/72V16200GU & HYS 64/72V32200GU)
Semiconductor Group
5
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
CS1
CS0
CS
DQM
DQ0-DQ7
DQMB0
DQ(7:0)
CS
DQM
DQ0-DQ7
CS
DQM
DQ0-DQ7
CS
DQM
DQ0-DQ7
D1
CS
DQM
DQ0-DQ7
CB(7:0)
CS
DQM
DQ0-DQ7
D4
D8
D0
DQMB1
DQ(15:8)
CS
DQM
DQ0-DQ7
DQMB4
DQ(39:32)
CS
DQM
DQ0-DQ7
DQMB5
DQ(47:40)
D9
D12
CS
DQM
DQ0-DQ7
D5
D13
CS
D16
DQM
DQ0-DQ7
D17
CS3
CS2
CS
DQM
DQ0-DQ7
DQMB2
DQ(23:16)
CS
DQM
DQ0-DQ7
D2
CS
DQM
DQ0-DQ7
DQMB3
DQ(31:24)
CS
DQM
DQ0-DQ7
A0-A12, BA0, BA1
D0-D15, (D16, D17)
VDD
D0-D15, (D16, D17)
D0-D7, (D8)
RAS, CAS, WE
D0-D15, (D16, D17)
CKE0
D0-D7, (D16)
CS
DQM
DQ0-DQ7
DQMB7
DQ(63:56)
D14
CS
DQM
DQ0-DQ7
D7
D11
D15
E 2 PROM (256 word x 8 Bit)
SA0
SA1
SA2
SCL
C0-C31, (C32...C35)
VSS
CS
DQM
DQ0-DQ7
D6
D10
D3
SA0
SA1
SA2
SCL
SDA
WP
47 k Ω
Clock Wiring
VDD
10 k Ω
CKE1
CS
DQM
DQ0-DQ7
DQMB6
DQ(55:48)
CLK0
CLK1
CLK2
CLK3
D9-D15, (D17)
64 M x 64
64 M x 72
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
5 SDRAM
5 SDRAM
4 SDRAM + 3.3 pF
4 SDRAM + 3.3 pF
Note: D16 & D17 is only used in the x72 ECC version and all resistor values are 10 Ω except otherwise noted.
SPB03971
Block Diagram for 32M × 64/72 & 64M × 64/72 two bank SDRAM DIMM Modules
Semiconductor Group
6
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
DC Characteristics
TA = 0 to 70 °C; VSS = 0 V; VDD, VDDQ = 3.3 V ± 0.3 V
Parameter
Symbol
Limit Values
min.
max.
Unit
Input high voltage
VIH
2.0
VCC + 0.3
V
Input low voltage
VIL
– 0.5
0.8
V
Output high voltage (IOUT = – 2.0 mA)
VOH
2.4
–
V
Output low voltage (IOUT = 2.0 mA)
VOL
–
0.4
V
Input leakage current, any input
(0 V < VIN < 3.6 V, all other inputs = 0 V)
II(L)
– 40
40
µA
Output leakage current
(DQ is disabled, 0 V < VOUT < VCC)
IO(L)
– 40
40
µA
Capacitance
TA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
Parameter
Symbol
Limit Values
Unit
max.
max.
max.
max.
32M×64 32M×72 32M×64 32M×72
Input capacitance
(A0 to A11, BA0, BA1, RAS, CAS, WE)
CI1
45
55
80
90
pF
Input capacitance (CS0 - CS3)
CI2
20
25
30
35
pF
Input capacitance (CLK0 - CLK3)
CICL
22
38
22
38
pF
Input capacitance (CKE0, CKE1)
CI3
22
38
50
55
pF
Input capacitance (DQMB0 - DQMB7)
CI4
13
13
20
20
pF
Input/Output capacitance
(DQ0 - DQ63, CB0 - CB7)
CIO
13
12
20
20
pF
Input Capacitance (SCL, SA0 - 2)
CSC
8
8
8
8
pF
Input/Output Capacitance
CSD
10
10
10
10
pF
Semiconductor Group
7
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Operating Currents
TA = 0 to 70 °C, VCC = 3.3 V ± 0.3 V 1
Recommended Operating Conditions unless otherwise noted
Parameter & Test Condition
Symb.
-8/-8B
-10
Unit Note
max.
Operating current
tRC ≥ tRC(MIN.), tCK ≥ tCK(MIN.)
Outputs open, Burst Length = 4, CL = 3
All banks operated in random access,
all banks operated in ping-pong manner to maximize
gapless data access
ICC1
×4
×8
× 16
210
210
210
165
165
165
mA
mA
mA
2
tCK = min.
ICC2P
2
2
mA
2
Precharged Standby Current in Non- tCK = min.
power Down Mode
CS = VIH(MIN.), CKE ≥ VIH(MIN.)
ICC2N
19
16
mA
2
VIH(MIN.)
ICC3N
45
40
mA
2
10
10
mA
2
×4
×8
× 16
210
210
210
165
165
165
mA
mA
mA
2, 3
Precharged Standby Current in
Power Down Mode
CS = VIH(MIN.), CKE ≤ VIL(MAX.)
No operating current
tCK = min., CS = VIH(MIN.),
active state (max. 4 banks)
CKE ≥
CKE ≤ VIL(MAX.)
ICC3P
Burst operating current
tCK = min.,
Read command cycling
–
ICC4
Auto refresh current
tCK = min.,
Auto Refresh command cycling
–
ICC5
240
195
mA
2
Self refresh current
Self Refresh Mode, CKE = 0.2 V
standard version ICC6
2.5
2.5
mA
2
Notes
1.
2.
3.
All values are shown per one SDRAM component.
These parameters depend on the cycle rate. These values are measured at 100 MHz for -8
and at 66 MHz for -10 parts. Input signals are changed once during tCK, excepts for ICC6 and for
standby currents when tCK = infinity.
These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 is assumed and the VDDQ current is excluded.
Semiconductor Group
8
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
AC Characteristics 1, 2
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-8
PC100-222
min.
Unit
Note
-8B
PC100-323
max.
min.
max.
Clock and Clock Enable
Clock Cycle Time
tCK
CAS Latency = 3
CAS Latency = 2
10
10
–
–
10
12
–
–
ns
ns
System Frequency
fCK
CAS Latency = 3
CAS Latency = 2
–
–
100
100
–
–
100
83
MHz
MHz
Clock Access Time
tAC
CAS Latency = 3
CAS Latency = 2
–
–
6
6
–
–
6
7
ns
ns
3, 4
Clock High Pulse Width
tCH
3
–
3
–
ns
4
Clock Low Pulse Width
tCL
3
–
3
–
ns
4
Input Setup Time
tCS
2
–
2
–
ns
5
Input Hold Time
tCH
1
–
1
–
ns
5
CKE Setup Time
(Power down mode)
tCKSP
2
–
2
–
ns
6
CKE Setup Time
(Self Refresh Exit)
tCKSR
10
–
–
–
ns
7
Transition Time (rise and fall)
tT
1
–
–
–
ns
RAS to CAS Delay
tRCD
20
–
20
–
ns
Cycle Time
tRC
70
–
70
–
ns
Active Command Period
tRAS
48
–
48
–
ns
Precharge Time
tRP
20
–
30
–
ns
Bank to Bank Delay Time
tRRD
16
–
20
–
ns
CAS to CAS Delay Time
(same bank)
tCCD
1
–
1
–
CLK
Common Parameters
Semiconductor Group
9
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
AC Characteristics (cont’d) 1, 2
TA = 0 to 70 °C; VSS = 0 V; VCC = 3.3 V ± 0.3 V, tT = 1 ns
Parameter
Symbol
Limit Values
-8
PC100-222
min.
Unit
Note
-8B
PC100-323
max.
min.
max.
Refresh Cycle
Self Refresh Exit Time
tSREX
10
–
10
–
ns
9
Refresh Period
tREF
64
–
64
–
ms
6
–
–
15.6
7.8
–
–
15.6
7.8
µs
µs
tOH
3
–
3
–
ns
Data Out to Low Impedance Time tLZ
0
–
0
–
ns
Data Out to High Impedance
Time
tHZ
3
8
3
10
ns
DQM Data Out Disable Latency
tDQZ
–
2
–
2
CLK
Data Input to Precharge
(write recovery)
tWR
2
–
2
–
CLK
Data In to Active/Refresh
tDAL
5
–
5
–
CLK
DQM Write Mask Latency
tDQW
0
–
0
–
CLK
Refresh Interval
128Mbit SDRAM based modules
256Mbit SDRAM based modules
Read Cycle
Data Out Hold Time
2
8
Write Cycle
Semiconductor Group
10
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Notes
1.
2.
An initial pause of 100 µs is required after power-up, then a Precharge All Banks command
must be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set
Operation can begin.
AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V
crossover point. The transition time is measured between VIH and VIL. All AC measurements
assume tT = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are
measured with a 50 pF only, without any resisitve termination and with a input signal of 1 V/ns
edge rate between 0.8 V and 2.0 V.
t CH
2.4 V
0.4 V
CLOCK
t CL
t SETUP
tT
t HOLD
INPUT
1.4 V
t AC
t LZ
t AC
I/O
t OH
50 pF
OUTPUT
1.4 V
Measurement conditions for
tAC and tOH
t HZ
SPT03404
3.
4.
5.
6.
7.
8.
If clock rising time is longer than 1 ns, a time (tT/2 – 0.5) ns has to be added to this parameter.
Rated at 1.5 V
If tT is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up” the device.
Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
Referenced to the time which the output achieves the open circuit condition, not to output
voltage levels.
Semiconductor Group
11
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
A serial presence detect storage device - E2PROM - is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E2PROM device during module
production using a serial presence detect protocol (I2C synchronous 2-wire bus).
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte#
Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
0
Number of SPD bytes
128
80
80
80
80
1
Total bytes in Serial PD
256
08
08
08
08
2
Memory Type
SDRAM
04
04
04
04
3
Number of Row
Addresses
(without BS bits)
13
0D
0D
0D
0D
4
Number of Column
Addresses (for 32M×8
SDRAMs)
10
0A
0A
0A
0A
5
Number of DIMM Banks
1
01
01
01
01
6
Module Data Width
64/72
40
40
48
48
7
Module Data Width
(cont’d)
0
00
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
01
9
SDRAM Cycle Time at
CL = 3
10.0 ns
A0
A0
A0
A0
10
SDRAM Access time
from Clock at CL = 3
6.0 ns
60
60
60
60
11
Dimm Configuration
none / ECC
00
00
02
02
12
Refresh Rate/Type
Self-Refresh,
7.8 µs
82
82
82
82
13
SDRAM width, Primary
x8
08
08
08
08
14
Error Checking SDRAM
data width
n/a/x8
00
00
08
08
15
Minimum clock delay for
back-to-back random
column address
tCCD = 1 CLK
01
01
01
01
16
Burst Length supported
1, 2, 4, 8 & full
page
8F
8F
8F
8F
17
Number of SDRAM
banks
4
04
04
04
04
Semiconductor Group
12
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte#
Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
18
Supported CAS
Latencies
CAS latency = 2
&3
06
06
06
06
19
CS Latencies
CS latency = 0
01
01
01
01
20
WE Latencies
Write latency = 0 01
01
01
01
21
SDRAM DIMM module
attributes
non buffered/
non re.
00
00
00
00
22
SDRAM Device
Attributes: General
VCC tol ± 10%
06
06
06
06
23
Min. Clock Cycle Time at
CAS Latency = 2
10.0 / 12.0 ns
A0
C0
A0
C0
24
Max. data access time
from Clock for CL = 2
6.0 / 7.0 ns
60
70
60
70
25
Minimum Clock Cycle
Time at CL = 1
not supported
FF
FF
FF
FF
26
Maximum Data Access
Time from Clock at
CL = 1
not supported
FF
FF
FF
FF
27
Minimum Row Precharge 20 / 30 ns
Time
14
1E
14
1E
28
Minimum Row Active to
Row Active delay tRRD
16 / 20 ns
10
14
10
14
29
Minimum RAS to CAS
delay tRCD
20 ns
14
14
14
14
30
Minimum RAS pulse
width tRAS
50 / 60 ns
32
3C
32
3C
31
Module Bank Density
(per bank)
256 MByte
40
40
40
40
32
SDRAM input setup time
2 ns
20
20
20
20
33
SDRAM input hold time
1 ns
10
10
10
10
34
SDRAM data input hold
time
2 ns
20
20
20
20
35
SDRAM data input setup
time
1 ns
10
10
10
10
Semiconductor Group
13
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte#
Description
SPD Entry
Value
Hex
32M×64 32M×64 32M×72 32M×72
one bank one bank one bank one bank
-8
-8B
-8
-8B
62-61
Superset information
(may be used in future)
–
FF
FF
FF
FF
62
SPD Revision
Revision 1.2
12
12
12
12
63
Checksum for bytes
0 - 62
–
–
–
–
–
64125
Manufacturers
information (optional)
(FFH if not used)
–
XX
XX
XX
XX
126
Frequency Specification
100 MHz
64
64
64
64
127
100 MHz support details
–
AF
AD
AF
AD
128+
Unused storage locations –
FF
FF
FF
FF
SPD-Table for 256MBit SDRAM based PC100 Modules
Byte#
Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
0
Number of SPD bytes
128
80
80
80
80
1
Total bytes in Serial PD
256
08
08
08
08
2
Memory Type
SDRAM
04
04
04
04
3
Number of Row
Addresses
(without BS bits)
13
0D
0D
0D
0D
4
Number of Column
Addresses
(for 32M × 8 SDRAMs)
10
0A
0A
0A
0A
5
Number of DIMM Banks
2
02
02
02
02
6
Module Data Width
64/72
40
40
48
48
7
Module Data Width
(cont’d)
0
00
00
00
00
8
Module Interface Levels
LVTTL
01
01
01
01
9
SDRAM Cycle Time at
CL = 3
10.0 ns
A0
A0
A0
A0
Semiconductor Group
14
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte#
Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
10
SDRAM Access time
from Clock at CL = 3
6.0 ns
60
60
60
60
11
Dimm Configuration
none/ECC
00
00
02
02
12
Refresh Rate/Type
Self Refresh,
7.8 µs
82
82
82
82
13
SDRAM width, Primary
×8
08
08
08
08
14
Error Checking SDRAM
data width
n/a/× 8
00
00
08
08
15
Minimum clock delay for
back-to-back random
column address
tCCD = 1 CLK
01
01
01
01
16
Burst Length supported
1, 2, 4, 8 & full
page
8F
8F
8F
8F
17
Number of SDRAM
banks
4
04
04
04
04
18
Supported CAS
Latencies
CAS latency = 2
&3
06
06
06
06
19
CS Latencies
CS latency = 0
01
01
01
01
20
WE Latencies
Write latency = 0 01
01
01
01
21
SDRAM DIMM module
attributes
non buffered/
non re.
00
00
00
00
22
SDRAM Device
Attributes: General
VCC tol ± 10%
06
06
06
06
23
Min. Clock Cycle Time at
CAS Latency = 2
10.0/12.0 ns
A0
C0
A0
C0
24
Max. data access time
from Clock for CL = 2
6.0/7.0 ns
60
70
60
70
25
Minimum Clock Cycle
Time at CL = 1
not supported
FF
FF
FF
FF
26
Maximum Data Access
Time from Clock at
CL = 1
not supported
FF
FF
FF
FF
27
Minimum Row Precharge 20/30 ns
Time
14
1E
14
1E
Semiconductor Group
15
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
SPD-Table for 256MBit SDRAM based PC100 Modules (cont’d)
Byte#
Description
SPD Entry
Value
Hex
64M×64 64M×64 64M×72 64M×72
two bank two bank two bank two bank
-8
-8B
-8
-8B
28
Minimum Row Active to
Row Active delay tRRD
16/20 ns
10
14
10
14
29
Minimum RAS to CAS
delay tRCD
20 ns
14
14
14
14
30
Minimum RAS pulse
width tRAS
50/60 ns
32
3C
32
3C
31
Module Bank Density
(per bank)
256 MByte
40
40
40
40
32
SDRAM input setup time
2 ns
20
20
20
20
33
SDRAM input hold time
1 ns
10
10
10
10
34
SDRAM data input hold
time
2 ns
20
20
20
20
35
SDRAM data input setup
time
1 ns
10
10
10
10
62-61
Superset information
(may be used in future)
FF
FF
FF
FF
62
SPD Revision
12
12
12
12
63
Checksum for bytes
0 - 62
10
65
22
77
64125
Manufacturers
information (optional)
(FFH if not used)
XX
XX
XX
XX
126
Frequency Specification
64
64
64
64
127
100 MHz support details
FF
FD
FF
FD
128+
Unused storage locations
FF
FF
FF
FF
Semiconductor Group
Revision 1.2
100 MHz
16
1998-08-01
HYS 64(72)V16200/3222(0)0/64220GU
SDRAM Modules
Package Outlines
L-DIM-168-30
SDRAM DIMM Module Package
133.35
127.35
31.75
4 ± 0.1
4
3
*)
1
10
3
11
6.35
1.27
40
41
6.35
84
1.27± 0.1
42.18
3.125
91 x 1.27 = 115.57
94
2
95
124
125
168
4.45
8.25
17.78
85
*)
R1.27
+0.1
3 min.
2.26
*) on ECC modules only
2.54 min.
0.2 ± 0.15
Detail of Contacts
1 ± 0.05
1.27
GLD09159
Sorts of Packing
Package outlines for tubes, trays etc. are contained in our
Data Book “Package Information”.
SMD = Surface Mounted Device
Semiconductor Group
17
Dimensions in mm
1998-08-01