. IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Features • High Performance: -75A -260, -360, -10, Units CL=3 CL=2 CL=3 CL=3 fCK Clock Frequency 133 100 100 100 MHz tCK Clock Cycle 7.5 10 10 10 ns tAC Clock Access Time1 — — — 7 ns tAC Clock Access Time2 5.4 6 6 9 ns Note: 1Terminated load, 2Unterminated load. See AC Characteristics (page 39). • Single-pulsed RAS interface • Fully Synchronous to Positive Clock Edge • Four Banks controlled by BS0, BS1 (Bank Selects) • Programmable CAS Latency: 2, 3 • • • • • • • • • • • • • Programmable Burst Length: 1, 2, 4, or 8 Programmable Wrap: Sequential or Interleave Multiple Burst Read with Single Write Option Automatic and Controlled Precharge command Data Mask for Read/Write control (x4, x8) and Dual Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Suspend mode and Power Down mode Standard Power operation 8192 Refresh cycles/64ms Random Column Address every CLK (1-N Rule) Single 3.3V ± 0.3V Power Supply LVTTL compatible Packages: - 54-pin 400 mil TSOP-Type II - 66-pin 400 mil 2-High Stack TSOJ Description The IBM0325404, IBM0325804, and IBM0325164 are four bank Synchronous DRAMs organized as 16Mbit x 4 I/O x 4 Bank, 8Mbit x 8 I/O x 4 Bank, and 4Mbit x 16 I/O x 4 Bank, respectively. IBM03254B4, a stacked version of the x4 component, is also offered. These synchronous devices achieve highspeed data-transfer rates of up to 133 MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is fabricated with IBM’s advanced 256Mbit single transistor CMOS DRAM process technology. The device is designed to comply with all JEDEC standards set for Synchronous DRAM products, both electrically and mechanically. All the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CLK). Internal chip operating modes are defined by combinations of these signals, and a command decoder initiates the necessary timings for each operation. A fifteen-bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Thirteen row addresses (A0-A12) and two bank select addresses (BS0, BS1) are strobed with RAS. Eleven column addresses (A0-A9, A11) plus bank select addresses and A10 are strobed 29L0000.E36980A 7/99 with CAS. Column address A11 is dropped on the x8 device and column addresses A9 and A11 are dropped on the x16 device. Access to the lower or upper DRAM in a stacked device is controlled by CS0 and CS1. Prior to any access, the CAS latency, burst length, and sequence must be programmed into the device by address inputs A0-A12, BS0, BS1 during a Mode Register Set cycle. It is also possible to program a Multiple Burst sequence with single write cycle for write-through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 133 MHz is possible depending on burst length, CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR), and Self Refresh operation are supported. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Pin Assignments for Planar Components (Top View) VDD VDD VDD 1 54 VSS VSS VSS DQ0 VDDQ DQ1 DQ2 DQ0 VDDQ NC DQ1 NC VDDQ NC DQ0 2 3 4 5 53 52 51 50 NC VSSQ NC DQ3 DQ7 VSSQ NC DQ6 DQ15 VSSQ DQ14 DQ13 VSSQ DQ3 DQ4 VDDQ DQ5 VSSQ NC NC VDDQ NC 6 7 8 9 10 49 48 47 46 45 VDDQ NC NC VSSQ NC VDDQ NC DQ5 VSSQ NC VDDQ DQ12 DQ11 VSSQ DQ10 DQ6 VSSQ NC DQ2 VDDQ NC DQ3 DQ1 11 44 DQ2 DQ4 DQ9 VSSQ VSSQ VSSQ 12 43 VDDQ VDDQ VDDQ DQ7 VDD NC VDD NC VDD LDQM WE CAS RAS CS BS0 NC WE CAS RAS CS BS0 NC WE CAS RAS CS BS0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 NC VSS NC DQM CLK CKE A12 A11 NC VSS NC DQM CLK CKE A12 A11 DQ8 VSS NC UDQM CLK CKE A12 A11 BS1 A10/AP A0 BS1 A10/AP A0 BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A9 A8 A7 A9 A8 A7 A1 A2 A1 A2 A1 A2 31 30 A6 A5 A6 A5 A6 A5 A3 VDD A3 VDD A3 VDD 24 25 26 27 29 28 A4 VSS A4 VSS A4 VSS 54-pin Plastic TSOP(II) 400mil 16Mbit x 4 I/O x 4 Bank IBM0325404 8Mbit x 8 I/O x 4 Bank IBM0325804 4Mbit x 16 I/O x 4 Bank IBM0325164 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Pin Assignments for 2 High Stack Package (Dual CS Pin) VDD 1 NC 2 3 4 5 VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC WE CAS RAS CS01 CS12 BS0 BS1 A10/AP A0 A1 A2 A3 VDD 66 65 64 63 62 61 60 59 58 57 VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC 11 12 56 DQ2 55 VDDQ 13 14 15 16 17 18 19 20 54 53 52 51 50 49 48 47 NC NC VSSQ NC NC NC VSS DQM 21 22 23 46 45 44 NC CK CKE03 24 25 26 27 28 43 42 CKE14 A12 41 40 39 38 37 36 35 34 A11 A9 A8 A7 A6 A5 A4 VSS 6 7 8 9 10 29 30 31 32 33 (Top View) 66-pin Plastic TSOJ 400mil 32Mbit x 4 I/O x 4 Bank (2 High Stack) IBM03254B4 Notes 1. CS0 selects the lower SDRAM in the stack. 2. CS1 selects the upper SDRAM in the stack. 3. CKE0 controls the clock for the lower SDRAM. 4. CKE1 controls the clock for the upper SDRAM. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Pin Description CLK Clock Input DQ0-DQ15 Data Input/Output CKE (CKE0, CKE1) Clock Enable DQM, LDQM, UDQM Data Mask CS (CS0, CS1) Chip Select VDD Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQs (+3.3V) WE Write Enable VSSQ Ground for DQs BS1, BS0 Bank Selects NC No Connection A0 - A12 Address Inputs — — Input/Output Functional Description Symbol Type Polarity Function CLK Input Positive Edge CKE, CKE0, CKE1 Input Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the Active High clock, CKE (CKE0, CKE1 for stacked devices) low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS, CS0, CS1 Input CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the Active Low command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Active Low BS0, BS1 Input — The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which bank is to be active. During a Bank Activate Command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write Command cycle, A0-A9, A11 defines the column address (CA0-CA9, CA11) when sampled at the rising clock edge. A0 - A12 Input — A10 is used to invoke Auto Precharge operation at the end of the Burst Read or Write cycle. If A10 is high, Auto Precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, Auto Precharge is disabled. During a Precharge Command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0 - DQ15 InputOutput — Data Input/Output pins operate in the same manner as on conventional DRAMs. The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In x16 products, LDQM and UDQM control the lower and upper byte I/O buffers, respectively. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output Active High enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. DQM LDQM UDQM Input VDD, VSS Supply — Power and ground for the input buffers and the core logic. VDDQ, VSSQ Supply — Isolated power supply and ground for the output buffers to provide improved noise immunity. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Ordering Information - Planar Devices (Single CS Pin) Part Number CAS Latencies Power Supply Clock Cycle Package Org. IBM0325404CT3A-75A 3 3.3V 7.5ns 400mil Type II TSOP-54 x4 IBM0325404CT3A-260 2, 3 3.3V 10ns 400mil Type II TSOP-54 x4 IBM0325404CT3A-360 2, 3 3.3V 10ns 400mil Type II TSOP-54 x4 IBM0325404CT3A-10 2, 3 3.3V 10ns 400mil Type II TSOP-54 x4 IBM0325804CT3A-75A 3 3.3V 7.5ns 400mil Type II TSOP-54 x8 IBM0325804CT3A-260 2, 3 3.3V 10ns 400mil Type II TSOP-54 x8 IBM0325804CT3A-360 2, 3 3.3V 10ns 400mil Type II TSOP-54 x8 IBM0325804CT3A-10 2, 3 3.3V 10ns 400mil Type II TSOP-54 x8 IBM0325164CT3A-360 2, 3 3.3V 10ns 400mil Type II TSOP-54 x16 Ordering Information - 2 High Stacked Devices (Dual CS Pin) Part Number CAS Latencies Power Supply Clock Cycle Package Org. IBM03254B4CT3A-75A 3 3.3V 7.5ns 400mil Type II TSOJ-66 x4 IBM03254B4CT3A-260 2, 3 3.3V 10ns 400mil Type II TSOJ-66 x4 IBM03254B4CT3A-360 2, 3 3.3V 10ns 400mil Type II TSOJ-66 x4 IBM03254B4CT3A-10 2, 3 3.3V 10ns 400mil Type II TSOJ-66 x4 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Block Diagram - Planar Devices Column Decoder CKE Buffer Row Decoder Row Decoder CLK Cell Array Memory Bank A Column Decoder Cell Array Memory Bank B CLK Buffer Sense Amplifiers Data Control Circuitry Control Signal Generator Sense Amplifiers Mode Register Column Address Counter Refresh Counter Address Buffers (15) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A11 A12 BS0 BS1 A10 DQX Command Decoder Cell Array Memory Bank C Sense Amplifiers Column Decoder Row Decoder WE Row Decoder CAS DQ0 DQM Column Decoder CS RAS Data Input/Output Buffers CKE Cell Array Memory Bank D Sense Amplifiers Cell Array, per Bank, for 16Mb x 4 DQ: 8192 Row x 2048 Col x 4 DQ (DQ0-DQ3). Cell Array, per Bank, for 8Mb x 8 DQ: 8192 Row x 1024 Col x 8 DQ (DQ0-DQ7). Cell Array, per Bank, for 4Mb x 16 DQ: 8192 Row x 512 Col x 16 DQ (DQ0-DQ15). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Block Diagram - 32Mbit x 4 I/O x 4 Bank (2-High) CS0 CKE0 CS1 CKE1 CLK A12-A0 BS0, BS1 RAS CAS WE DQM 29L0000.E36980A 7/99 16Mb x 4 I/O x 4 Bank DQ0 DQ1 DQ2 DQ3 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Power On and Initialization The default power-on state of the mode register is supplier specific and may be undefined. The following power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During Power On, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power-on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must be started at the same time. After Power On, an initial pause of 200 µs is required followed by a precharge of all banks using the Precharge command. To prevent data contention on the DQ bus during Power On, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set command must be issued to initialize the Mode Register. A minimum of two Auto Refresh cycles (CBR) are also required. These may be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes. Programming the Mode Register For application flexibility, CAS latency, burst length, burst sequence, and operation type are user-defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set command. Any content of the Mode Register can be altered by re-executing the Mode Register Set command. If the user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined when the Mode Register Set command is issued. After initial Power Up, the Mode Register Set command must be issued before read or write cycles may begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set command can be issued. The Mode Register Set command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the Mode Register Set command once a delay equal to tRSC has elapsed. CAS Latency The CAS latency is a parameter that is used to define the delay from when a Read command is registered on a rising clock edge to when the data from that Read command becomes available at the outputs. The CAS latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS latency is determined by the speed grade of the device and the clock frequency that is used in the application. A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it must be programmed into the mode register after Power Up; for an explanation of this procedure see Programming the Mode Register in the previous section. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Mode Register Operation (Address Input For Mode Set) BS1 BS0 A12 A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 CAS Latency A3 A2 BT A1 A0 Burst Length Address Bus (Ax) Mode Register (Mx) Burst Type M3 Type 0 Sequential 1 Interleave Operation Mode MBS1 MBS0 M12 M11 M10 M9 M8 M7 0 0 0 0 0 0 0 0 Burst Length Mode Normal Length M2 0 0 0 0 0 1 0 0 M0 Multiple Burst with Single Write Sequential Interleave CAS Latency 29L0000.E36980A 7/99 M1 M6 M5 M4 Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Mode Operation Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from memory locations (read cycle). There are three parameters that define how the burst mode will operate. These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A12, BS0, and BS1. The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM. Two types of burst sequences are supported: sequential and interleaved. See the table below. The burst length controls the number of bits that will be output after a Read command, or the number of bits to be input after a Write command. The burst length can be programmed to have values of 1, 2, 4, or 8. Burst operation mode can be normal operation or Multiple Burst with single write operation. Normal operation implies that the device will perform burst operations on both read and write cycles until the desired burst length is satisfied. Multiple Burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected. Burst Length and Sequence Burst Length Starting Address (A2 A1 A0) Sequential Addressing (decimal) Interleave Addressing (decimal) xx0 0, 1 0, 1 xx1 1, 0 1, 0 x00 0, 1, 2, 3 0, 1, 2, 3 x01 1, 2, 3, 0 1, 0, 3, 2 x10 2, 3, 0, 1 2, 3, 0, 1 x11 3, 0, 1, 2 3, 2, 1, 0 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 2 4 8 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Bank Activate Command In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the rising edge of the clock. The bank select address BS0, BS1 is used to select the desired bank. The row address A0 - A12 is used to determine which row to activate in the selected bank. Activation of banks within both decks of a 2-High stacked device is allowed. The Bank Activate command must be applied before any Read or Write operation can be executed. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active is specified as tRAS(max). Bank Activate Command Cycle (CAS Latency = 3, tRCD= 3) T0 T1 T2 T3 Tn Tn+1 Tn+2 Tn+3 CLK .......... Bank A Col. Addr. Bank A Row Addr. ADDRESS .......... RAS-CAS delay (tRCD) Bank A Activate COMMAND NOP Bank B Row Addr. Bank A Row Addr. RAS - RAS delay time (tRRD) NOP : “H” or “L” Write A with Auto Precharge .......... Bank B Activate NOP Bank A Activate NOP RAS Cycle time (tRC) Bank Select The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge, Read, or Write operation. Bank Selection Bits BS0 BS1 Bank 0 0 Bank 0 1 0 Bank 1 0 1 Bank 2 1 1 Bank 3 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Read and Write Access Modes After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be defined at this time to determine whether the access cycle is a read operation (WE high) or a write operation (WE low). The address inputs determine the starting column address. The SDRAM provides a wide variety of fast access modes. A single Read or Write command will initiate a serial read or write operation on successive clock cycles up to 133 MHz. The number of serial data bits for each access is equal to the burst length, which is programmed into the Mode Register. Similar to Page mode of conventional DRAMs, a read or write cycle cannot begin until the sense amplifiers latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends. The ability to interrupt a Burst operation at every clock cycle is supported; this is referred to as the 1-N rule. When the previous burst is interrupted by another Read or Write command, the remaining addresses are overridden by the new address. Precharging an active bank after each read or write operation is not necessary providing the same row is to be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must be precharged and a new Bank Activate command must be issued. When more than one bank is activated, interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, fast and seamless data access operation among many different pages can be realized. When multiple banks are activated, column-to-column interleave operation can be done between different pages. Finally, Read or Write commands can be issued to the same bank or between active banks on every clock cycle. Burst Read Command The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency that is set in the Mode Register. Burst Read Operation (Burst Length = 4, CAS Latency = 2, 3) CLK COMMAND T0 READ A CAS latency = 2 tCK2, DQs T1 NOP T2 T3 T5 NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 DOUT A0 DOUT A1 DOUT A2 CAS latency = 3 tCK3, DQs ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 68 T4 T6 NOP T7 NOP T8 NOP DOUT A3 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Read Interrupted by a Read A Burst Read may be interrupted before completion of the burst by another Read command, with the only restriction being that the interval that separates the commands must be at least one clock cycle. When the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. The data from the first Read command continues to appear on the outputs until the CAS latency from the interrupting Read command is satisfied; at this point the data from the interrupting Read command appears. Read Interrupted by a Read (Burst Length = 4, CAS Latency = 2, 3) T0 T1 READ A READ B T2 T3 T4 T5 T6 T7 T8 CLK COMMAND CAS latency = 2 tCK2, DQs CAS latency = 3 tCK3, DQs 29L0000.E36980A 7/99 NOP NOP NOP NOP NOP DOUT A0 DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT A0 DOUT B0 DOUT B1 DOUT B2 NOP NOP DOUT B3 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Read Interrupted by a Write To interrupt a Burst Read with a Write command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read command will issue data on the first or second clocks cycles of the write operation, DQM is needed to ensure the DQs are tri-stated. After that point the Write command will have control of the DQ bus. Minimum Read to Write Interval (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM high for CAS latency = 2 only. Required to mask first bit of READ data. DQM WRITE A NOP NOP NOP CAS latency = 2 tCK2, DQs DIN A0 DIN A1 DIN A2 DIN A3 CAS latency = 3 tCK3, DQs DIN A0 DIN A1 DIN A2 DIN A3 COMMAND NOP READ A NOP NOP NOP : “H” or “L” ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Non-Minimum Read to Write Interval (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND READ A NOP WRITE A NOP NOP NOP NOP NOP NOP CL=2: DQM needed to mask first, second bit of READ data. CAS latency = 2 tCK2 , DQs DIN A0 DIN A1 DIN A2 DIN A3 CL=3: DQM needed to mask first bit of READ data. CAS latency = 3 tCK3 , DQs DIN A0 DIN A1 DIN A2 DIN A3 : DQM high for CAS latency = 2 : DQM high for CAS latency = 3 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Write Command The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. There is no CAS latency required for Burst Write cycles. Data for the first Burst Write cycle must be applied on the DQ pins on the same clock cycle that the Write command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data supplied to the DQ pins will be ignored. Burst Write Operation (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP DQs WRITE A DIN A0 NOP NOP NOP DIN A1 DIN A2 DIN A3 The first data element and the Write are registered on the same clock edge. NOP NOP NOP NOP don’t care Extra data is masked. Write Interrupted by a Write A Burst Write may be interrupted before completion of the burst by another Write command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied. Write Interrupted by a Write (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 WRITE A WRITE B T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP NOP NOP DIN B1 DIN B2 DIN B3 NOP NOP NOP 1 Clk Interval DQs DIN A0 DIN B0 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Write Interrupted by a Read A Read command will interrupt a Burst Write operation on the same clock cycle that the Read command is registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data appears on the outputs to avoid data contention. When the Read command is registered, any residual data from the Burst Write cycle will be ignored. Data that is presented on the DQ pins before the Read command is initiated will actually be written to the memory. Minimum Write to Read Interval (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK WRITE A READ B CAS latency = 2 tCK2 DQs DIN A0 don’t care CAS latency = 3 tCK2, DQs DIN A0 don’t care COMMAND NOP NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 don’t care NOP NOP DOUT B3 Input data for the Write is masked. Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Non-Minimum Write to Read Interval (Burst Length = 4, CAS Latency = 2, 3) CLK T0 T1 T2 WRITE A NOP CAS latency=2 tCK2, DQs DIN A0 DIN A1 don’t care CAS latency=3 tCK3, DQs DIN A0 DIN A1 don’t care COMMAND T3 READ B NOP don’t care Input data for the Write is masked. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 68 T4 T5 T6 NOP T7 T8 NOP NOP NOP NOP DOUT B0 DOUT B1 DOUT B2 DOUT B3 DOUT B0 DOUT B1 DOUT B2 DOUT B3 Input data must be removed from the DQs at least one clock cycle before the Read data appears on the outputs to avoid data contention. 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Auto Precharge Operation Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge command or the Auto Precharge function. When a Read or a Write command is given to the SDRAM, the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically begin precharge at the earliest possible moment during the Burst Read or Write cycle. If A10 is low when the Read or Write command is issued, then normal Read or Write Burst operation is executed and the bank remains active at the completion of the burst sequence. If A10 is high when the Read or Write command is issued, then the Auto Precharge function is engaged. During Auto Precharge, a Read command will execute as normal with the exception that the active bank will begin to precharge before all Burst Read cycles have been completed. Regardless of burst length, the precharge will begin (CAS latency -1) clock prior to the last data output. Auto Precharge can also be implemented during Write commands. A Read or Write command without Auto Precharge can be terminated in the midst of a Burst operation. However, a Read or Write command with Auto Precharge cannot be interrupted by a command to the same bank. Therefore use of a Read, Write, or Precharge command to the same bank is prohibited during a read or write cycle with Auto Precharge until the entire Burst operation is completed. Once the Precharge operation has started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. When using the Auto Precharge command, the interval between the Bank Activate command and the beginning of the internal Precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then tRCD must be extended. Burst Read with Auto Precharge (Burst Length = 1, CAS Latency = 2, 3) T0 CLK COMMAND READ A Auto Precharge T1 NOP T2 T3 NOP Begin Auto Precharge 29L0000.E36980A 7/99 NOP T6 NOP T7 NOP T8 NOP DOUT A0 ♣ tRP♦ CAS latency = 3 tCK3, DQs NOP T5 ♣ tRP CAS latency = 2 tCK2, DQs NOP T4 DOUT A0 ♣ Bank can be reactivated at completion of tRP. ♦ tRP is a function of the clock cycle time and speed sort (see Clock Frequency and Latency). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Read with Auto Precharge (Burst Length = 2, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto Precharge NOP NOP NOP DOUT A0 NOP NOP NOP DOUT A1 tRP♦ CAS latency = 3 tCK3, DQs NOP ♣ tRP CAS latency = 2 tCK2, DQs NOP DOUT A0 ♣ DOUT A1 ♣ Bank can be reactivated at completion of tRP. ♦ tRP is a function of the clock cycle time and speed sort (see Clock Frequency and Latency). Begin Auto Precharge Burst Read with Auto Precharge (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto Precharge NOP NOP NOP NOP NOP NOP DOUT A0 DOUT A1 DOUT A2 DOUT A3 ♣ tRP♦ CAS latency = 3 tCK3, DQs DOUT A0 DOUT A1 NOP ♣ tRP CAS latency = 2 tCK2, DQs NOP DOUT A2 DOUT A3 ♣ Bank can be reactivated at completion of tRP. Begin Auto Precharge ♦ tRP is a function of the clock cycle time and speed sort (see Clock Frequency and Latency). Although a Read command with Auto Precharge cannot be interrupted by a command to the same bank, it can be interrupted by a Read or Write command to a different bank. If the interrupting command is issued before Auto Precharge begins then the Precharge function will begin with the new command. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Read with Auto Precharge Interrupted by Read (Burst Length = 4, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto Precharge NOP READ B NOP DOUT A0 DOUT A1 DOUT B0 tRP♦ CAS latency = 3 tCK3, DQs NOP NOP NOP DOUT B1 DOUT B2 DOUT B3 DOUT B1 DOUT B2 NOP ♣ tRP CAS latency = 2 tCK2, DQs NOP DOUT A0 ♣ DOUT A1 DOUT B0 DOUT B3 ♣ Bank can be reactivated at completion of tRP. ♦ tRP is a function of the clock cycle time and speed sort (see Clock Frequency and Latency). Begin Auto Precharge A * If interrupting a Read command with Auto Precharge with a Write command, DQM must be used to avoid DQ contention. Burst Read with Auto Precharge Interrupted by Write (Burst Length = 8, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ A Auto Precharge CAS latency = 2 tCK2, DQs NOP NOP NOP WRITE B NOP tRP DOUT A0 DIN B0 DIN B1 NOP NOP NOP ♣ DIN B2 DIN B3 DOUT B4 DQM Begin Auto Precharge A 29L0000.E36980A 7/99 ♣ Bank A can be reactivated at completion of tRP. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) If A10 is high when a Write command is issued, the Write with Auto Precharge function is initiated. The bank undergoing Auto Precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied. Burst Write with Auto Precharge T0 T1 T2 T3 (Burst Length = 2, CAS Latency = 2, 3) T5 T6 T7 T8 T4 CLK COMMAND WRITE A Auto Precharge NOP NOP NOP NOP DIN A0 DIN A0 NOP NOP DIN A1 ♣ tDAL ♦ CAS latency = 3 tCK3, DQs NOP ♣ tDAL ♦ CAS latency = 2 tCK2, DQs NOP DIN A1 ♣ Bank can be reactivated at completion of tDAL. ♦ Number of clocks required depends on clock frequency. See Clock Frequency and Latency Table. Begin Auto Precharge Similar to the Read command, a Write command with Auto Precharge cannot be interrupted by a command to the same bank. It can be interrupted by a Read or Write command to a different bank, however. The interrupting command will terminate the write. The bank undergoing Auto Precharge cannot be reactivated until tDAL is satisfied. Burst Write with Auto Precharge Interrupted by Write T0 T1 T2 T3 T4 (Burst Length = 4, CAS Latency = 3) T5 T6 T7 CLK COMMAND WRITE A Auto Precharge NOP WRITE B NOP NOP NOP DIN A0 DIN A1 DIN B0 DIN B1 NOP ♣ tDAL♦ CAS latency = 3 tCK3, DQs NOP DIN B2 DIN B3 ♣ Bank can be reactivated at completion of tDAL. ♦ Number of clocks required depends on clock frequency. See Clock Frequency and Latency Table. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 22 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Write with Auto Precharge Interrupted by Read T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 3) T6 T7 T8 CLK COMMAND WRITE A Auto Precharge CAS latency=3 DIN A0 tCK3, DQs NOP NOP READ B NOP NOP NOP DIN A2 NOP ♣ tDAL♦ DIN A1 NOP DOUT B0 DOUT B1 DOUT B2 ♣ Bank can be reactivated at completion of tDAL. ♦ Number of clocks required depends on clock frequency. See Clock Frequency and Latency Table. Precharge Command The Precharge command is used to precharge or close a bank that has been activated. The Precharge command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge command can be used to precharge each bank separately or all banks simultaneously. Three address bits—A10, BS0, and BS1—are used to define which bank(s) is to be precharged when the command is issued. Bank Selection for Precharge by Address Bits A10 Bank Select Precharged Bank(s) LOW BS0, BS1 Single bank defined by BS0, BS1 HIGH DON’T CARE All Banks For read cycles, the Precharge command may be applied (CAS latency - 1) prior to the last data output. For write cycles, a delay must be satisfied from the start of the last Burst Write cycle until the Precharge command can be issued. This delay is known as tDPL, Data-in to Precharge delay. After the Precharge command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge command and the Activate command must be greater than or equal to the Precharge time (tRP). 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 23 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Read followed by the Precharge Command (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP Precharge A NOP tRP CAS latency = 2 t , DQs DOUT Ax0 DOUT Ax1 DOUT Ax2 NOP NOP NOP ♣ DOUT Ax3 CK2 ♣ Bank A can be reactivated at completion of tRP. Burst Write followed by the Precharge Command T0 T1 T2 T3 T4 T5 (Burst Length = 2, CAS Latency = 2) T6 T7 T8 CLK COMMAND NOP Activate Bank Ax NOP WRITE Ax0 NOP NOP tDPL CAS latency = 2 tCK2, DQs DIN Ax0 Precharge A NOP tRP NOP ♣ DIN Ax1 ♣ Bank A can be reactivated at completion of tRP. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 24 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Precharge Termination The Precharge command may be used to terminate either a Burst Read or Write operation. When the Precharge command is issued, the Burst operation is terminated and bank precharge begins. For Burst Read operations, valid data will continue to appear on the data bus as a function of CAS Latency. Burst Read Interrupted by Precharge (Burst Length = 8, CAS Latency = 2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND READ Ax0 NOP NOP NOP Precharge A NOP NOP DOUT Ax0 DOUT Ax1 DOUT Ax2 DOUT Ax3 ♣ tRP♦ CAS latency = 3 tCK3, DQs DOUT Ax0 DOUT Ax1 NOP ♣ tRP CAS latency = 2 tCK2, DQs NOP DOUT Ax2 DOUT Ax3 ♣ Bank A can be reactivated at completion of tRP.c ♦ tRP is a function of the clock cycle time and speed sort (see Clock Frequency and Latency). 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 25 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Burst Write operations will be terminated by the Precharge command. The last write data that will be properly stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL. Precharge Termination of a Burst Write (Burst Length = 8, CAS Latency =2, 3) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK COMMAND NOP NOP WRITE Ax0 NOP NOP NOP Precharge A NOP NOP DQM tDPL CAS latency = 2 tCK2, DQs DIN Ax0 DIN Ax1 DIN Ax2 tDPL CAS latency = 3 tCK3, DQs DIN Ax0 DIN Ax1 DIN Ax2 Automatic Refresh Command (CAS Before RAS Refresh) When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of the Precharge time (tRP) before the Auto Refresh command (CBR) can be applied. For a stacked device, both decks may be refreshed at the same time using Automatic Refresh mode. An address counter internal to the device provides the address during the refresh cycle. No control of the external address pins is required once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay between the Auto Refresh command (CBR) and the next Activate command or subsequent Auto Refresh command must be greater than or equal to the RAS cycle time (tRC). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 26 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Self Refresh Command The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh command is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh operation to save power. The user may halt the external clock while the device is in Self Refresh mode; however, the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh operation and before the next command can be issued. This delay is equal to the RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a stacked device may be refreshed at the same time. Power Down Mode In order to reduce standby power consumption, two power down modes are available: Precharge and Active Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the Power Down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a Power Down Mode command when the device is performing a Read or Write operation causes the device to enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any refresh operations; therefore the device can’t remain in Power Down mode longer than the Refresh period (tREF) of the device. The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation command or Device Deselect command is required on the next rising clock edge. Power Down Mode Exit Timing Tm Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+ 8 COMMAND NOP NOP NOP NOP NOP CLK tCK CKE tCES(min) COMMAND NOP : “H” or “L” 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 27 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Data Mask The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately (zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and become high impedance after a two-clock delay, independent of CAS latency. Data Mask Activated During a Read Cycle (Burst Length = 4, CAS Latency = 2) T0 T1 T2 T3 T4 T5 T6 T7 T8 CLK DQM COMMAND NOP READ A DQs NOP NOP DOUT A0 NOP DOUT A1 NOP NOP NOP NOP A two-clock delay before the DQs become Hi-Z : “H” or “L” No Operation Command The No Operation command should be used in cases when the SDRAM is in an idle or a wait state. The purpose of the No Operation command is to prevent the SDRAM from registering any unwanted commands between operations. A No Operation command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation command will not terminate a previous operation that is still executing, such as a Burst Read or Write cycle. Deselect Command The Deselect command performs the same function as a No Operation command. Deselect command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 28 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Clock Suspend Mode During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a oneclock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock-cycle delay from when CKE returns high to when Clock Suspend mode is exited. When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited. Clock Suspend During a Read Cycle T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 2) T6 T7 T8 CLK CKE A one clock delay before Suspend operation starts COMMAND NOP READ A NOP A one clock delay to exit the Suspend command NOP DQs NOP DOUT A0 : “H” or “L” NOP DOUT A2 DOUT A1 DOUT element at the DQs when the Suspend operation starts is held valid If Clock Suspend mode is initiated during a Burst Write operation, then the input data is masked and ignored until the Clock Suspend mode is exited. Clock Suspend During a Write Cycle T0 T1 T2 T3 T4 T5 (Burst Length = 4, CAS Latency = 2) T6 T7 T8 CLK CKE A one clock delay before Suspend operation starts COMMAND DQs : “H” or “L” 29L0000.E36980A 7/99 NOP WRITE A DIN A0 A one clock delay to exit the Suspend Command NOP NOP NOP DIN A1 DIN A2 DIN A3 NOP DIN is masked during the Clock Suspend Period ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 29 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Command Truth Table EC Update (-10) (See note 1) CKE Function Previous Cycle Current Cycle CS Mode Register Set Idle H X L Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L L L L H X X X X Idle (SelfRefresh) H X X X L H X X X X L H H H Single Bank Precharge See Current State Table H X L L H L X BS L X Precharge all Banks See Current State Table H X L L H L X X H X Idle H X L L H H X BS Write Active H X L H L L X BS L Column 2 Write with Auto Precharge Active H X L H L L X BS H Column 2 Read Active H X L H L H X BS L Column 2 Read with Auto Precharge Active H X L H L H X BS H Column 2 Exit Self Refresh Bank Activate RAS CAS L L WE L DQM BS0, BS1 A12, A11, A9- Notes A0 Device State X A10 OP Code Row Address 2 2 No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X H X X X Idle/Active H L X X X X 5, 6 L H H H X X X X 5, 6 Power Down Mode Entry Power Down Mode Exit Any (Power Down) L H X X X L H H H H 3 4 1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock. Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the Current State Truth Table. 2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 1,0 selects bank 1; BS0, BS1 = 0,1 selects bank 2; BS0, BS1 = 1,1 selects bank 3. 3. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 4. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a Data Mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 5. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a Burst operation, the device state will be Clock Suspend mode.) The Power Down Mode does not perform any refresh operations; therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 6. A No Operation or Device Deselect command is required on the next clock edge following CKE going high. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 30 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Clock Enable (CKE) Truth Table CKE Current State Command Action Notes Previous Cycle Current Cycle CS RAS CAS WE H X X X X X X X INVALID 1 L H H X X X X X Exit Self Refresh with Device Deselect 2 L H L H H H X X Exit Self Refresh with No Operation 2 L H L H H L X X ILLEGAL 2 L H L H L X X X ILLEGAL 2 L H L L X X X X ILLEGAL 2 L L X X X X X X Maintain Self Refresh H X X X X X X X INVALID 1 L H H X X X X X Power Down mode exit, all banks idle 2 L H L X X X X X ILLEGAL 2 L L X X X X X X Maintain Power Down Mode H H H X X X Self Refresh BS0,BS1 A12 - A0 Power Down All Banks Idle Any State other than listed above H H L H X X H H L L H X H H L L L H H H L L L L H L H X X X 3 Refer to the Idle State section of the Current State Truth Table 3 3 X X OP Code CBR Refresh 4 Mode Register Set 3 Refer to the Idle State section of the Current State Truth Table H L L H X X H L L L H X H L L L L H H L L L L L L X X X X X X X Power Down H H X X X X X X Refer to operations in the Current State Truth Table H L X X X X X X Begin Clock Suspend next cycle L H X X X X X X Exit Clock Suspend next cycle L L X X X X X X Maintain Clock Suspend 3 3 X X OP Code 4 Entry Self Refresh Mode Register Set 4 5 1. For the given Current State CKE must be low in the previous cycle. 2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for CKE (tCES) must be satisfied before any command other than Exit is issued. When exiting Power Down mode, a NOP command (or Device Deselect command) is required on the first rising clock after CKE goes high (see page 27). 3. The address inputs (A12 - A0, BS0, BS1) depend on the command that is issued. See the Idle State section of the Current State Truth Table for more information. 4. The Power Down Mode, Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle state. 5. Must be a legal command as defined in the Current State Truth Table. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 31 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Current State Truth Table (Part 1 of 4) (See note 1) Current State Idle Row Active Read Command CS RAS CAS WE BS0,BS1 L L L L L L L H X L L H L H A12 - A0 OP Code Action Description Mode Register Set Notes 2 Set the Mode Register 2, 3 X Auto or Self Refresh Start Auto or Self Refresh BS X Precharge No Operation BS Row Address Bank Activate Activate the specified bank and row L L H L H L L BS Column Write w/o Precharge ILLEGAL 4 L H L H BS Column Read w/o Precharge ILLEGAL 4 L H H H X X H X X X X L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Precharge 6 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 7, 8 L H L H BS Column Read Start Read; Determine if Auto Precharge 7, 8 L H H H X X No Operation No Operation H X X X X L L L L L L L H X L L H L H X OP Code X OP Code No Operation No Operation Device Deselect No Operation or Power Down Mode Register Set ILLEGAL Device Deselect No Operation Mode Register Set ILLEGAL 5 X Auto or Self Refresh ILLEGAL BS X Precharge Terminate Burst; Start the Precharge BS Row Address Bank Activate ILLEGAL 4 L L H L H L L BS Column Write Terminate Burst; Start the Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start a new Read cycle 8, 9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation; if CKE is inactive (low) the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 32 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Current State Truth Table (Part 2 of 4) (See note 1) Current State Write Read with Auto Precharge Write with Auto Precharge Command CS RAS CAS WE BS0,BS1 A12 - A0 OP Code Action Description Mode Register Set Notes L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge Terminate Burst; Start the Precharge L L H H BS Row Address Bank Activate ILLEGAL L H L L BS Column Write Terminate Burst; Start a new Write cycle 8, 9 L H L H BS Column Read Terminate Burst; Start the Read cycle 8, 9 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 L H H H X X No Operation Continue the Burst H X X X X X Device Deselect Continue the Burst OP Code X OP Code ILLEGAL Device Deselect Continue the Burst Mode Register Set ILLEGAL 4 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation; if CKE is inactive (low) the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 33 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Current State Truth Table (Part 3 of 4) (See note 1) Current State Command CS RAS CAS WE BS0,BS1 OP Code Write Recovering Action Description Mode Register Set Notes L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge No Operation; Bank(s) idle after tRP L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 Precharging Row Activating A12 - A0 ILLEGAL L H H H X X No Operation No Operation; Bank(s) idle after tRP H X X X X X Device Deselect No Operation; Bank(s) idle after tRP L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4, 10 L H L L BS Column Write ILLEGAL 4 L H L H BS Column Read ILLEGAL 4 OP Code L H H H X X No Operation No Operation; Row Active after tRCD H X X X X X Device Deselect No Operation; Row Active after tRCD L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write Start Write; Determine if Auto Precharge 9 L H L H BS Column Read Start Read; Determine if Auto Precharge 9 OP Code L H H H X X No Operation No Operation; Row Active after tDPL H X X X X X Device Deselect No Operation; Row Active after tDPL 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation; if CKE is inactive (low) the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 34 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Current State Truth Table (Part 4 of 4) (See note 1) Current State Write Recovering with Auto Precharge Command CS RAS CAS WE BS0,BS1 OP Code Action Description Mode Register Set Notes L L L L L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL 4 L L H H BS Row Address Bank Activate ILLEGAL 4 L H L L BS Column Write ILLEGAL 4, 9 L H L H BS Column Read ILLEGAL 4, 9 L H H H X X No Operation No Operation; Precharge after tDPL H X X X X X Device Deselect No Operation; Precharge after tDPL L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL L L H H BS Row Address Bank Activate ILLEGAL L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after tRC H X X X X Device Deselect No Operation; Idle after tRC L L L L Mode Register Set ILLEGAL L L L H X X Auto or Self Refresh ILLEGAL L L H L BS X Precharge ILLEGAL Bank Activate ILLEGAL OP Code Refreshing Mode Register Accessing A12 - A0 X OP Code ILLEGAL L L H H BS Row Address L H L L BS Column Write ILLEGAL L H L H BS Column Read ILLEGAL L H H H X X No Operation No Operation; Idle after two clock cycles H X X X X X Device Deselect No Operation; Idle after two clock cycles 1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the command is being applied to. 2. All Banks must be idle; otherwise, it is an illegal action. 3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation; if CKE is inactive (low) the Self Refresh mode is entered. 4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being referenced by the Current State then the action may be legal depending on the state of that bank. 5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation. 6. The minimum and maximum Active time (tRAS) must be satisfied. 7. The RAS to CAS delay (tRCD) must occur before the command is given. 8. Column address A10 is used to determine if the Auto Precharge function is activated. 9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements. 10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 35 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Absolute Maximum Ratings Symbol VDD VDDQ VIN VOUT TA TSTG PD IOUT Parameter Rating Units Notes Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to VDD+0.3 V 1 Output Voltage -0.3 to VDD+0.3 V 1 0 to +70 °C 1 -55 to +125 °C 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 Operating Temperature (ambient) Storage Temperature 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0 to 70°C) Rating Symbol Parameter Units Notes 3.6 V 1 3.3 3.6 V 1 2.0 — VDD + 0.3 V 1, 2 -0.3 — 0.8 V 1, 3 Min. Typ. Max. Supply Voltage 3.0 3.3 Supply Voltage for Output 3.0 VIH Input High Voltage VIL Input Low Voltage VDD VDDQ 1. All voltages referenced to VSS and VSSQ. 2. VIH (max) = VDD/VDDQ + 1.2V for pulse width ≤ 5ns. 3. VIL (min) = VSS/VSSQ - 1.2V for pulse width ≤ 5ns. Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ± 0.3V) Symbol Parameter Min. Typ. Max. Units Notes Input Capacitance (A0-A12, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 3.4 3.8 pF 1 Input Capacitance (CLK) 2.5 3.2 3.5 pF 1 Output Capacitance (DQ0 - DQ15) 4.0 4.8 6.5 pF 1 CI CO 1. Multiply given planar values by 2 for 2-High stacked device (except CS and CKE). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 36 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) DC Electrical Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) Symbol Parameter Min. Max. Units Notes II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V -1 +1 µA 1 IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ) -1 +1 µA 1 VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 — V VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) — 0.4 V 1. Multiply given planar values by 2 for 2-High stacked device. DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 29L0000.E36980A 7/99 870Ω ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 37 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Operating, Standby and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) Speed Parameter Operating Current Symbol Units Notes 90 mA 1, 2, 3 -75A -260 -360 -10 120 115 115 ICC1 1 bank operation, tRC = tRC(min), tCK = min, Active Precharge Command cycling without Burst operation ICC2P CKE ≤ VIL(max), tCK = min, CS =VIH (min) 2 2 2 2 mA 1 ICC2PS CKE ≤ VIL(max), tCK = Infinity, CS =VIH (min) 2 2 2 2 mA 1 ICC2N CKE ≥ VIH(min), tCK = min, CS =VIH (min) 30 20 20 20 mA 1, 4 6 6 6 6 mA 1, 7 Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode Test Condition ICC2NS CKE ≥ VIH(min), tCK = Infinity ICC3N CKE ≥ VIH(min), tCK = min, CS = VIH (min) 60 45 45 55 mA 1, 5 ICC3P CKE ≤ VIL(max), tCK = min 6 6 6 6 mA 1, 6 Operating Current (Burst Mode) ICC4 tCK = min, Read/ Write Command cycling, Multiple banks active, gapless data, BL=4 155 115 115 115 mA 1, 3, 4 Auto (CBR) Refresh Current ICC5 tCK = min, tRC = tRC(min) CBR Command cycling 175 170 170 130 mA 1 Self Refresh Current ICC6 CKE ≤ 0.2V 3 3 3 3 mA 1 No Operating Current (Active state: 4 bank) 1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the other deck. 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ). 7. Input signals are stable. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 38 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200 µs, with DQM and CKE held high, is required after Power Up. A Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH). 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V crossover point 5. Load Circuit A: AC measurements assume tT=1.0 ns. 6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 7. Load Circuit B: AC measurements assume tT=1.2 ns. AC Diagrams tT tCKL Clock tSETUP Vtt=1.4V VIH 1.4V VIL tCKH 50Ω Output Zo = 50Ω 50pF AC Output Load Circuit (A) tHOLD Input 1.4V Output Zo = 50Ω tOH tAC 50pF tLZ AC Output Load Circuit (B) 1.4V Output Clock and Clock Enable Parameters -75A Symbol -260 -360 -10 Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. Notes tCK3 Clock Cycle Time, CAS Latency = 3 7.5 1000 10 1000 10 1000 10 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 — — 10 1000 15 1000 14 1000 ns tAC3 (A) Clock Access Time, CAS Latency = 3 — — — — — — — 7 ns 1 tAC2 (A) Clock Access Time, CAS Latency = 2 — — — — — — — 8 ns 1 tAC3 (B) Clock Access Time, CAS Latency = 3 — 5.4 — 6 — 6 — 9 ns 2 tAC2 (B) Clock Access Time, CAS Latency = 2 — — — 6 — 9 — 9 ns 2 tCKH Clock High Pulse Width 2.5 — 3 — 3 — 3 — ns tCKL Clock Low Pulse Width 2.5 — 3 — 3 — 3 — ns tCES Clock Enable Setup Time 1.5 — 2 — 2 — 3 — ns tCEH Clock Enable Hold Time 0.8 — 1 — 1 — 1 — ns tSB Power Down mode Entry Time 0 7.5 0 10 0 10 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 0.5 10 0.5 10 ns 1. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 4, 5 and load circuit A. 2. Access time is measured at 1.4V. See AC Characteristics: notes: 1, 2, 3, 6, 7 and load circuit B. 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 39 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Common Parameters -75A Symbol -260 -360 -10 Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. Notes tCS Command Setup Time 1.5 — 2 — 2 — 3 — ns tCH Command Hold Time 0.8 — 1 — 1 — 1 — ns tAS Address and Bank Select Setup Time 1.5 — 2 — 2 — 3 — ns tAH Address and Bank Select Hold Time 0.8 — 1 — 1 — 1 — ns tRCD RAS to CAS Delay 20 — 20 — 20 — 28 — ns 1 tRC Bank Cycle Time 67.5 — 70 — 70 — 84 — ns 1 tRAS Active Command Period 45 100000 50 100000 50 100000 56 100000 ns 1 tRP Precharge Time 20 — 20 — 20 — 14 — ns 1 tRRD Bank to Bank Delay Time 15 — 20 — 20 — 20 — ns 1 tCCD CAS to CAS Delay Time 1 — 1 — 1 — 1 — CLK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -75A Symbol tRSC -260 -360 -10 Parameter Mode Register Set Cycle Time Min. Max. Min. Max. Min. Max. Min. Max. 2 — 2 — 2 — 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Read Cycle -75A Symbol tOH -260 -360 -10 Parameter Units Notes — ns 1 3 — ns 2, 4 Min. Max. Min. Max. Min. Max. Min. Max. — — 2.5 — 2.5 — 3 2.7 — 3 — 3 — Data Out Hold Time tLZ Data Out to Low Impedance Time 0 — 0 — 0 — 0 — ns tHZ3 Data Out to High Impedance Time 3 5.4 3 6 3 6 3 7 ns 3 tHZ2 Data Out to High Impedance Time — — 3 6 3 8 3 8 ns 3 tDQZ DQM Data Out Disable Latency 2 — 2 — 2 — 2 — CLK 1. 2. 3. 4. AC Output Load Circuit A. AC Output Load Circuit B. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Data Out Hold Time with no load must meet 1.8ns (-75A). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 40 of 68 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Refresh Cycle -75A Symbol -260 -360 -10 Parameter Min. Max. Min. Max. Min. Max. Min. Max. Units Notes 1 tREF Refresh Period — 64 — 64 — 64 — 64 ms tSREX Self Refresh Exit Time 10 — 10 — 10 — 10 — ns 1. 8192 Auto Refresh cycles. Write Cycle -75A Symbol -260 -360 -10 Parameter Units Min. Max. Min. Max. Min. Max. Min. Max. tDS Data In Setup Time 1.5 — 2 — 2 — 3 — ns tDH Data In Hold Time 0.8 — 1 — 1 — 1 — ns tDPL Data Input to Precharge 15 — 20 — 20 — 20 — ns tDAL3 Data Input to Active, CL = 3 5 — 5 — 5 — 5 — CLK tDAL2 Data Input to Active, CL = 2 — — 5 — 5 — 3 — CLK tDQW DQM Write Mask Latency 0 — 0 — 0 — 0 — CLK Clock Frequency and Latency Symbol Parameter -75A -260 -360 -10 Units fCK Clock Frequency 133 100 100 100 66 100 71 MHz tCK Clock Cycle Time 7.5 10 10 10 15 10 14 ns tAA CAS Latency 3 3 2 3 2 3 2 CLK tRP Precharge Time 3 2 2 2 2 3 1 CLK tRCD RAS to CAS Delay 3 2 2 2 2 3 2 CLK tRC Bank Cycle Time 9 7 7 7 6 9 5 CLK tRAS Minimum Bank Active Time 6 5 5 5 4 6 4 CLK tDPL Data In to Precharge 2 2 2 2 2 2 2 CLK tDAL Data In to Active/Refresh 5 5 5 5 5 5 3 CLK tRRD Bank to Bank Delay Time 2 2 2 2 2 2 2 CLK tCCD CAS to CAS Delay Time 1 1 1 1 1 1 1 CLK tWL Write Latency 0 0 0 0 0 0 0 CLK tDQW DQM Write Mask Latency 0 0 0 0 0 0 0 CLK tDQZ DQM Data Disable Latency 2 2 2 2 2 2 2 CLK tCSL Clock Suspend Latency 1 1 1 1 1 1 1 CLK 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 41 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Timing Diagrams EC Update (-10) Page AC Parameters for Write Timing ............................................................................................................... 43 AC Parameters for Read Timing (3/3/3), BL=4......................................................................................... 44 AC Parameters for Read Timing (2/2/2), BL=2......................................................................................... 45 AC Parameters for Read Timing (3/2/2), BL=2......................................................................................... 46 AC Parameters for Read Timing (3/3/3), BL=2......................................................................................... 47 Mode Register Set .................................................................................................................................... 48 Power On Sequence and Auto Refresh (CBR)......................................................................................... 49 Clock Suspension / DQM During a Burst Read ....................................................................................... 50 Clock Suspension / DQM During a Burst Write ....................................................................................... 51 Power Down Mode and Clock Suspend ................................................................................................... 52 Auto Refresh (CBR) .................................................................................................................................. 53 Self Refresh (Entry and Exit) .................................................................................................................... 54 Random Row Read (Interleaving Banks) with Precharge, BL=8 .............................................................. 55 Random Row Read (Interleaving Banks) with Auto Precharge, BL=8...................................................... 56 Random Row Write (Interleaving Banks) with Auto Precharge, BL=8 ...................................................... 57 Random Row Write (Interleaving Banks) with Precharge, BL=8 .............................................................. 58 Read And Write Cycle............................................................................................................................... 59 Interleaved Column Read Cycle ............................................................................................................... 60 Auto Precharge after a Read Burst, BL=4 ................................................................................................ 61 Auto Precharge after a Write Burst, BL=4 ................................................................................................ 62 Burst Read and Single Write Operation.................................................................................................... 63 CS Function (Only CS signal needs to be asserted at minimum rate)...................................................... 64 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 42 of 68 29L0000.E36980A 7/99 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCKH tRCD tDPL tRC tCKL tRRD tRP tDAL tDAL tCK2 CLK tCES tCEH CKE tCS tCH CS EC Update (-10) T0 AC Parameters for Write Timing 29L0000.E36980A 7/99 (CAS Latency = 2; Burst Length = 4) RAS CAS WE BS1* RAx A0-9, A11, A12 RAx RBx RAy RAz RBy RAz RBy tAS CAx RBx CBx RAy RAy DQM tDH tDS DQ Ax0 Activate Command Bank A * BS0 = "L" Bank C, D = Idle Ax1 Ax2 Ax3 Activate Command Bank B Write with Auto Precharge Command Bank A Bx0 Bx1 Bx2 Bx3 Ay0 Ay1 Activate Command Bank A Write with Auto Precharge Command Bank B Write Command Bank A Ay2 Ay3 Precharge Command Bank A Activate Command Bank B Activate Command Bank A IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Page 43 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. tAH A10 Page 44 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. * BS0 = "L" Bank C, D = Idle DQ Activate Command Bank A RAx A0-9, A11, A12 DQM RAx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 tCK3 tRCD T2 CAx tRAS T4 T5 RBx RBx tRC T6 T8 Ax0 Ax2 Ax3 T10 Read with Auto Precharge Command Bank B Ax1 tOH CBx tRP T9 Begin Auto Precharge Bank A T7 tAC3 Activate Command Bank B Read with Auto Precharge Command Bank A tRRD T3 T13 Bx0 RAy RAy Bx1 Bx3 T14 Bx2 Begin Auto Precharge Bank B T12 Activate Command Bank A T11 (CAS Latency = 3; Burst Length = 4; tRCD, tRP = 3) IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) AC Parameters for Read Timing (3/3/3) 29L0000.E36980A 7/99 29L0000.E36980A 7/99 * BS0 = "L" Bank C, D = Idle DQ DQM tAS T3 tAH CAx tRRD T5 tRC T6 Ax0 tOH Activate Command Bank B tLZ tAC2 RBx RBx T7 tRP tHZ CBx T8 T9 T10 Bx0 Bx1 tHZ RAy RAy tCEH T12 Activate Command Bank A T11 tRP Begin Auto Precharge Bank B Read with Auto Precharge Command Bank B Ax1 tCH Begin Auto Precharge Bank A tCS tRAS (min)** T4 Read with Auto Precharge Command Bank A tRCD** Activate Command Bank A **Note: Must satisfy tRAS (min) For -260, extend tRCD 1 CLK RAx A0-9, A11, A12 tCES tCK2 T2 RAx tCKH tCKL T1 A10 BS1* WE CAS RAS CS CKE CLK T0 T13 (CAS Latency = 2; Burst Length = 2; tRCD, tRP = 2) EC Update (-10) IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A AC Parameters for Read Timing (2/2/2) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 45 of 68 Page 46 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. * BS0 = "L" Bank C, D = Idle DQ DQM tCS Bank A T6 RBx RBx tRP T7 tLZ Ax0 tAC3 Activate Command Bank B Read with Auto Precharge Command Bank A CAx T5 tCH Begin Auto Precharge tRC T4 tRAS (min)** T3 tRRD tRCD** T2 **Note: Must satisfy tRAS (min) Extended tRCD one clock Not required for BL ≥ 4 Activate Command Bank A RAx A0-9, A11, A12 tAH tAS tCES RAx tCKL tCK3 T1 A10 BS1* WE CAS RAS CS CKE CLK tCKH T0 tHZ3 CBx T9 T11 T12 tRP T13 Bx1 Activate Command Bank A Bx0 RAy RAy Begin Auto Precharge Bank B T10 Read with Auto Precharge Command Bank B Ax1 tOH T8 tHZ3 tCEH T14 (CAS Latency = 3; Burst Length = 2; tRCD, tRP = 2) IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) AC Parameters for Read Timing (3/2/2) 29L0000.E36980A 7/99 29L0000.E36980A 7/99 tRRD T4 tRAS (min)** *BS0 = "L" Bank C, D = Idle DQ DQM **Note: Must satisfy tRAS (min); extended tRCD 1 clock. Extended tRCD not required for BL ≥ 4. Activate Command Bank A Ax0 Read with Auto Precharge Command Bank A tRP T8 tAC3 Activate Command Bank B RBx CAx T7 Begin Auto Precharge Bank A T6 RAx tRC T5 A0-9, A11, A12 tCK3 tRCD** T3 RBx T2 RAx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 Ax1 tOH T9 CBx T11 T13 T15 Bx1 tCEH Activate Command Bank A Bx0 RAy tRP T14 RAy Begin Auto Precharge Bank B T12 Read with Auto Precharge Command Bank B T10 (CAS Latency = 3; Burst Length = 2; tRCD, tRP = 3) EC Update (-10) IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A AC Parameters for Read Timing (3/3/3) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 47 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Any Command T7 Address Key Mode Register Set Command tRSC Precharge Command All Banks tRP Page 48 of 68 Hi-Z DQ DQM A0-9, A11, A12 A10 BS0, BS1 Low ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. WE CAS RAS CS CKE CLK T0 High T1 tCK2 T2 T3 T4 T5 T6 (CAS Latency = 2) Mode Register Set 29L0000.E36980A 7/99 29L0000.E36980A 7/99 T2 tRP T3 T4 1st Auto Refresh Command Precharge Command All Banks Hi-Z High level is required tCK T1 Inputs must be stable for 200 µsec DQ DQM A0-9, A11, A12 A10 BS WE CAS RAS CS CKE CLK T0 T5 T6 tRC T7 T8 T10 T11 T12 2nd Auto Refresh Command A minimum of 2 refresh cycles is required T9 T13 tRC T14 T15 T18 2 clock min T17 T19 Any Command Mode Register Set Command Address key T16 T20 EC Update (-10) IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Power On Sequence and Auto Refresh (CBR) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 49 of 68 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T9 tCK3 CLK tCEH tCES CKE CS RAS CAS WE IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A T0 Clock Suspension, DQM during Burst Read ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 50 of 68 (CAS Latency = 3; Burst Length = 8; tRCD = 3) BS1* A10 RAx A0-9, A11, A12 RAx CAx DQM tHZ DQ Ax0 Ax1 Clock Suspend 1 Cycle * BS0 = "L" Bank C, D = Idle Clock Suspend 2 Cycles Ax3 Ax4 Ax7 Clock Suspend 3 Cycles Read Command Bank A DQM has no effect on data out since CLK cycle T8 is suspended and the Command bus is deactivated Ax6 DQM will gate off Ax5 since CLK cycle T16 is not a suspended clock cycle EC Update (-10) 29L0000.E36980A 7/99 Activate Command Bank A Ax2 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK3 CLK CKE CS RAS CAS WE EC Update (-10) T0 Clock Suspension, DQM during Burst Write 29L0000.E36980A 7/99 (CAS Latency = 3; Burst Length = 8; tRCD = 3) BS1* RAx A0-9, A11, A12 RAx CAx DQM DQ DAx0 Clock Suspend 1 Cycle Activate Command Bank A * BS0 = "L" Bank C, D = Idle Write Command Bank A DAx1 DAx2 Clock Suspend 2 Cycles DAx3 DAx5 DAx6 DAx7 Clock Suspend 3 Cycles DAx4 is gated off with DQM since T14 is not a suspended clock cycle DQM is ignored since T17 is a suspended clock cycle IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Page 51 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T6 tSB T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 tCK2 tSB CLK tCES tCES tCES CKE Valid CS RAS CAS WE IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A T0 Power Down Mode and Clock Suspend ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 52 of 68 (CAS Latency = 2; Burst Length = 4) BS1* A10 A0-9, A11, A12 RAx CAx RAx DQM tHZ DQ Ax0 Enter Active Standby * BS0 = "L" Bank C, D = Idle Read Command Bank A Exit Active Standby Ax2 Clock Suspension Start Ax3 Clock Suspension End Precharge Command Bank A Enter Precharge Standby NOP Any Command Exit Precharge Standby EC Update (-10) 29L0000.E36980A 7/99 Activate Command Bank A NOP Ax1 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) T16 T15 T14 DQ DQM A0-9, A11, A12 A10 BS WE CAS RAS CS Hi-Z High CKE CLK T0 29L0000.E36980A 7/99 Precharge Command All Banks Auto Refresh Command tCK2 tRP T1 T2 T3 T4 T5 T6 tRC T7 T8 T9 T10 Auto Refresh Command T11 T12 tRC T13 (CAS Latency = 2) T17 Auto Refresh (CBR) ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 53 of 68 Page 54 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. T2 tSB T3 T4 Tm Hi-Z low Power Down Entry Self Refresh Entry tCES CLK must be re-established prior to CKE returning High. T1 All Banks Must be Idle DQ DQM A0-9, A11, A12 A10 BS WE CAS RAS CS CKE CLK T0 Power Down Exit Self Refresh Exit tCES tSREX tRC Any Command Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 Tm+10Tm+11Tm+12Tm+13Tm+14 Tm+15 (Entry and Exit) IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Self Refresh 29L0000.E36980A 7/99 29L0000.E36980A 7/99 T6 tAC3 T7 T8 * BS0 = "L" Bank C, D = Idle Read Command Bank B Activate Command Bank B DQ DQM Bx1 Bx2 T9 Bx6 Ax0 Ax1 RBy Ax5 CBy Ax6 Ax7 By0 By1 Precharge Command Bank A Read Command Bank B Ax4 Activate Command Bank B Precharge Command Bank B Bx5 Read Command Bank A Bx4 CAx RBy T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 Bx3 Activate Command Bank A Bx0 RAx T5 RBx CBx T4 A0-9, A11, A12 tCK3 T3 RAx tRCD T2 RBx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 (CAS Latency = 3; BL = 8; tRCD, tRP = 3) EC Update (-10) IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Random Row Read (Interleaving Banks) with Precharge ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 55 of 68 Page 56 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. * BS0 = "L" Bank C, D = Idle DQ tRCD T2 tCK3 T3 CBx T4 T5 T6 Activate Command Bank B Read with Auto Precharge Command Bank B RBx A0-9, A11, A12 DQM RBx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 Bx0 tAC3 T7 Bx2 RAx RAx T9 Bx3 Bx4 Bx5 CAx Bx6 Start Auto Precharge Bank B Bx7 Ax0 Ax4 Ax5 CBy Ax6 Ax7 Activate Command Bank B Read with Auto Precharge Command Bank B Ax1 RBy RBy T21 Start Auto Precharge Bank A T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 Activate Command Bank A Read with Auto Precharge Command Bank A Bx1 T8 (CAS Latency= 3; BL= 8; tRCD, tRP = 3) IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Random Row Read (Interleaving Banks) with Auto Precharge 29L0000.E36980A 7/99 29L0000.E36980A 7/99 * BS0 = "L" Bank C, D = Idle DQ tRCD T2 CAx T4 DAx0 tCK3 T3 DAx1 T5 Write with Auto Precharge Command Bank A Activate Command Bank A RAx A0-9, A11, A12 DQM RAx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 T6 T7 DAx5 RBx RBx T9 DAx6 DBx0 DBx1 DBx2 DBx3 tDAL Write with Auto Precharge Command Bank B DAx7 CBx Activate Command Bank A DBx4 DBx5 RAy RAy DBx7 DAy0 DAy1 DAy2 tDAL Write with Auto Precharge Command Bank A DBx6 CAy T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 Activate Command Bank B DAx4 T8 (CAS Latency= 3; BL = 8; tRCD, tRP = 3) EC Update (-10) IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Random Row Write (Interleaving Banks) with Auto Precharge ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 57 of 68 Page 58 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. RAx A0-9, A11, A12 tRCD T2 * BS0 = "L" Bank C, D = Idle Activate Command Bank A DQ DQM RAx T1 A10 BS1* WE CAS RAS CS CKE CLK T0 T5 DAx0 DAx1 CAx T4 Write Command Bank A tCK3 T3 T6 T8 RBx RBx T9 CBx tRP RAy RAy Activate Command Bank B Activate Command Bank A Precharge Command Bank A Write Command Bank B Precharge Command Bank B Write Command Bank A DBx6 DBx7 DAy0 DAy1 DAy2 DAy3 tDPL CAy T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 DAx4 DAx5 DAx6 DAx7 DBx0 DBx1 DBx2 DBx3 DBx4 DBx5 T7 (CAS Latency = 3; BL = 8; tRCD, tRP = 3) IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Random Row Write (Interleaving Banks) with Precharge 29L0000.E36980A 7/99 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 tCK3 CLK EC Update (-10) T0 Read-Write Cycle 29L0000.E36980A 7/99 (CAS Latency = 3; Burst Length = 8; tRCD = 3) High CKE CS RAS CAS WE BS1* RAx A0-9, A11, A12 RAx CAx CAy DQM DQ Ax0 Read Command Bank A Activate Command Bank A * BS0 = "L" Bank C, D = Idle Ax1 Ax2 Ax3 DAy0 DAy1 DAy3 Write Command Bank A Read data masked Write data masked with with two clock latency zero clock latency DAy4 Precharge Command Bank A IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Page 59 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tRCD tAC3 tCK3 CLK High CKE Start Auto Precharge Bank A CS IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A T0 Interleaved Column Read Cycle ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 60 of 68 (CAS Latency = 3; Burst Length = 4; tRCD = 3) RAS CAS WE BS1* A10 RAx A0-9, A11, A12 RAx DQM RBx CAx RBx CBx CAy CBz CBy Low DQ Ax0 * BS0 = "L" Bank C, D = Idle Activate Command Bank B Read Command Bank A Ax2 Ax3 Bx0 Read Command Bank B Read Command Bank B Bx1 By0 By1 Bz0 Bz1 Ay0 Read with Auto Precharge Command Bank A Read Command Bank B Precharge Command Bank B Ay1 Ay2 Ay3 EC Update (-10) 29L0000.E36980A 7/99 Activate Command Bank A Ax1 T1 T2 T3 T4 T5 T6 T7 T8 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 T9 t CK3 CLK CKE Start Auto Precharge Bank B Start Auto Precharge Bank A Start Auto Precharge Bank B CS RAS EC Update (-10) T0 Auto Precharge after Read Burst 29L0000.E36980A 7/99 (CAS Latency = 3; Burst Length = 4; tRCD = 3) CAS WE A10 RAx A0-9, A11, A12 RAx RBx CAx RBy RBx CBx CAy RBy CBy Low DQM DQ Ax0 Activate Command Bank A * BS0 = "L" Bank C, D = Idle Ax1 Ax2 Ax3 Activate Command Bank B Read Command Bank A Read with Auto Precharge Command Bank B Bx0 Bx1 Bx2 Bx3 Read with Auto Precharge Command Bank A Ay0 Ay1 Ay2 Ay3 Read with Auto Precharge Command Bank B Activate Command Bank B By0 By1 By2 By3 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Page 61 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. BS1* T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 tCK2 CLK CKE high CS IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A T0 Auto Precharge after Write Burst ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 62 of 68 (CAS Latency = 2; Burst Length = 4) RAS CAS WE BS1* A10 RAx A0-9, A11, A12 RAx DQM RBx CBx CAy CBy RBy DAx0 DAx1 DAx2 DAx3 DBx0 DBx1 DBx2 DBx3 DAy0 DAy1 DAy2 DAy3 Activate Command Bank B Write Command Bank A Write with Auto Precharge Command Bank B CAz tDAL Write with Auto Precharge Command Bank A DBy0 DBy1 DBy2 Write with Auto Precharge Command Bank B Activate Command Bank B DBy3 DAz0 DAz1 DAz2 Write with Auto Precharge Command Bank A Activate Command Bank A tDAL DAz3 EC Update (-10) 29L0000.E36980A 7/99 Activate Command Bank A RAz tDAL tDAL Low DQ * BS0 = "L" Bank C, D = Idle RBx CAx RAz RBy T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 tCK2 CLK CKE high CS RAS CAS WE EC Update (-10) T0 Burst Read and Single Write Operation 29L0000.E36980A 7/99 (CAS Latency = 2; Burst Length = 4) BS1* RAv A0-9, A11, A12 RAv CAw CAv CAx CAy CAz LDQM UDQM Lower byte masked DQ0-7 Av0 Av1 Av2 Av3 DQ8-15 Av0 Av1 Av2 Av3 DAw0 Ay0 Ay1 Ay3 DAz0 Lower byte masked DAx0 Ay0 * BS0 = "L" Bank C, D = Idle Read Command Bank A Single Write Command Bank A Single Write Command Bank A Ay3 DAz0 Upper byte masked Upper byte masked Activate Command Bank A Ay2 Read Command Bank A Single Write Command Bank A IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Page 63 of 68 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. A10 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Write Command Bank A Ax2 Ax3 CAy DAy0 DAy1 DAy2 DAy3 tDPL Precharge Command Bank A T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 RAx A0 - A9 Activate Command Bank A RAx A10 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 64 of 68 Hi-Z DQ DQM A11(BS) WE CAS RAS CS CKE CLK Low T0 tCK3 T1 T2 tRCD T3 T4 Read Command Bank A T5 CAx T6 T7 Ax0 T8 Ax1 T9 (CAS Latency = 3; Burst Length = 4; tRCD/tRP = 3) CS Function (Only CS signal needs to be asserted at minimum rate) 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 22.22 ± 0.13 11.76 ± 0.20 10.16 ± 0.13 Detail A Lead #1 Seating Plane 0.10 0.80 Basic 0.35 + 0.10 - 0.05 0.71REF 1.20 Max Detail A 0.25 Basic Gage Plane 0.5 ± 0.1 0.05 Min 29L0000.E36980A 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 65 of 68 IBM0325804 IBM0325404 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A Package Dimensions EC Update (-10) (400mil; 66 lead; 2 High Stack; Thin Small Outline J Lead Package) 3.20 Max 22.25 ± 0.3 9.90 ± 0.40 11.4 ± 0.25 10.15 ± 0.15 0.75 Min Lead #1 0.10 0.65 Basic ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 66 of 68 + 0.10 0.3 - 0.04 Seating Plane 29L0000.E36980A 7/99 IBM0325404 IBM0325804 IBM0325164 IBM03254B4 256Mb Synchronous DRAM - Die Revision A EC Update (-10) Revision Log Revision Location 8/24/98 -- Initial Release page 1 Change -260 to 135 MHz maximum, -360 to 100MHz maximum. Also page 39 and page 41. Remove -68, low power. page 5 Update clock cycle for -260, -360. Remove -68, low power. page 6 Correct cell array information. page 9 Update Mode Register Figure. page 22-23 1/7/99 Contents of Modification Correct Burst Write with Auto Precharge / Interrupt. page 24 Correct Burst Read followed by a Precharge Command timing diagram. page 30 Update bank designation for consistency. page 32 Remove Burst Termination from Current State Truth Table. page 38 Update currents. page 39 Correct number of CBRs required (note 1). page 39-page 41 Update timings: -260 (tCK3, tSETUP, tHOLD, tRC, tRAS, tRRD, tSB, tRSC, tDPL, tDAL); -360 (tCK3, tRAS, tRRD, tSB, tRSC, tDPL, tDAL); -10 (tCK2, tRC, tRAS, tRCD, tRP, tRSC, tDPL, tDAL) . Remove -68. page 44-page 47, page 49, page 50, page 52, page 54, page 55, page 56, page 61, Correct timing diagrams. page 62 page 65, 66 2/11/99 page 1 Add -75A. Change -260 to 100 MHz maximum. page 5 Add -75A. Update clock cycle for -260. page 36 Update capacitance table. page 38 Update currents. page 39 - page 41 3/19/99 Add -75A timings. Update -260 timings: tCK3, tSETUP, tHOLD, tRC, tRAS, tRRD, tDPL. page 11 Update Bank Selection Bits. page 40 Update tRP, tRCD for -75A (22.5 to 20ns) page 41 Update tDPL from 15 to 20ns (-260, -360), tDAL2 from 4 to 5 clk (-360) 6/30/99 -- 7/27/99 page 40, 41 29L0000.E36980A 7/99 Correct package dimensions. Correct drawing of 2 high stack package. Removed preliminary. Update tRP (28ns to14ns), tDPL (14ns to 20ns), tDAL2 (4clk to 3clk), for -10 sort ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 67 of 68 International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. 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