Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Features • Programmable Wrap: Sequential or Interleave • High Performance: -75A, CL=3 Units • Multiple Burst Read with Single Write Option • Automatic and Controlled Precharge Command fCK Clock Frequency 133 MHz tCK Clock Cycle 7.5 ns tAC Clock Access Time 5.4 ns tRP Precharge Time 20 ns • Suspend Mode and Power Down Mode tRCD RAS to CAS Delay 20 ns • Standard Power operation tRC Bank Cycle Time 67.5 ns • 4096 refresh cycles/64ms • Data Mask for Read/Write control • Auto Refresh (CBR) and Self Refresh • Single Pulsed RAS Interface • Random Column Address every CLK (1-N Rule) • Fully Synchronous to Positive Clock Edge • Single 3.3V ± 0.3V Power Supply • Four Banks controlled by Bank Selects • LVTTL compatible • Programmable Burst Length: 1, 2, 4, 8, full-page; • Package: 54-pin 400 mil TSOP-Type II 54-pin 2 High Stack TSOJ • Programmable CAS Latency: 3 Description The IBM0364404CT3 is a four-bank 64Mb Synchronous DRAM organized as 4Mbit x 4 I/O x 4 Bank. IBM03644B4CT3 is a stacked version of the 64Mb, x 4 component. 46L8543.F46205 7/99 This datasheet provides timing information for the 133 MHz performance sort for this synchronous device. For the complete functional description and timing diagrams refer to the datasheet 19L3264. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Pin Assignments for Planar Components (Top View) VDD 1 54 VSS NC VDDQ NC DQ0 2 3 4 5 53 52 51 50 NC VSSQ NC DQ3 VSSQ NC NC VDDQ NC 6 7 8 9 10 49 48 47 46 45 VDDQ NC NC VSSQ NC DQ1 11 44 DQ2 VSSQ 12 43 VDDQ NC VDD NC WE CAS RAS CS A13/BS0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 NC VSS NC DQM CLK CKE NC A11 A12/BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A1 A2 24 25 26 27 31 30 A6 A5 29 28 A4 VSS A3 VDD 54-pin Plastic TSOP(II) 400 mil 4Mbit x 4 I/O x 4 Bank IBM0364404CT3 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Pin Assignments for 2 High Stack Package (Dual CS Pin) (Top View) VDD 1 54 VSS NC VDDQ NC DQ0 2 3 4 5 53 52 51 50 NC VSSQ NC DQ3 VSSQ NC NC VDDQ NC 6 7 8 9 10 49 48 47 46 45 VDDQ NC NC VSSQ NC DQ1 11 44 DQ2 VSSQ 12 43 VDDQ NC VDD NC WE CAS RAS CS0/NC A13/BS0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 NC VSS NC DQM CLK CKE NC/CS1 A11 A12/BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A1 A2 24 25 26 27 31 30 A6 A5 29 28 A4 VSS A3 VDD 54-pin Plastic TSOJ(II) 400 mil (4Mbit x 4 I/O x 4 Bank) x 2High IBM03644B4CT3 * CS0 selects the lower DRAM in the stack. * CS1 selects the upper DRAM in the stack. 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Pin Description CLK Clock Input DQ0-DQ3 Data Input/Output CKE Clock Enable DQM Data Mask CS (2High Stack: CS0, CS1) Chip Select VDD Power (+3.3V) RAS Row Address Strobe VSS Ground CAS Column Address Strobe VDDQ Power for DQs (+3.3V) WE Write Enable VSSQ Ground for DQs BS1, BS0 Bank Select NC No Connection A0-A11 Address Inputs — — Input/Output Functional Description Symbol Type Polarity Function CLK Input Positive The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Edge CKE Input Active High CKE activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS, CS0, CS1 Input Active Low CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS, WE Input Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BS1, BS0 Input — Selects which bank is to be active. A0 - A11 Input — During a Bank Activate command cycle, A0-A11 defines the row address when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 defines the column address when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If A10 is low, then BS0 and BS1 are used to define which bank to precharge. DQ0-DQ3 InputOutput — Data Input/Output pins operate in the same manner as on conventional DRAMs. DQM Input Active High VDD, VSS Supply VDDQ, VSSQ Supply The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode, DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the input buffers and the core logic. — Isolated power supply and ground for the output buffers to provide improved noise immunity. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Ordering Information - Planar Devices (Single CS Pin) Part Number CAS Latencies Power Supply Clock Cycle Package Org. IBM0364404CT3B-75A 3 3.3V 7.5ns 400mil Type II TSOP-54 x4 Ordering Information - 2 High Stacked Devices (Dual CS Pin) Part Number CAS Latencies Power Supply Clock Cycle Package Org. IBM03644B4CT3B-75A 3 3.3V 7.5ns 400mil Type II TSOJ-54 x4 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Command Truth Table (See note 1) Function CKE Device State Previous Current Cycle Cycle CS RAS CAS WE DQM L L L L X Bank Selects A10 Address Notes Mode Register Set Idle H X OP Code Auto (CBR) Refresh Idle H H L L L H X X X X Entry Self Refresh Idle H L L L L H X X X X Exit Self Refresh Idle (SelfRefresh) L H X X X X Single Bank Precharge See Current State Table H Precharge all Banks See Current State Table Bank Activate Write H X X X L H H H X L L H L X BS L X H X L L H L X X H X Idle H X L L H H X BS Active H X L H L L X BS L Column 2 Row Address 2 2 Write with Auto-Precharge Active H X L H L L X BS H Column 2 Read H X L H L H X BS L Column 2 Read with Auto-Precharge Active H X L H L H X BS H Column 2 Burst Termination Active H X L H H L X X X X 3, 8 No Operation Any H X L H H H X X X X Device Deselect Any H X H X X X X X X X Clock Suspend Mode Entry Active H L X X X X X X X X Clock Suspend Mode Exit Active L H X X X X X X X X Data Write/Output Enable Active 4 Active H X X X X X L X X X Data Mask/Output Disable Active H X X X X X H X X X Power Down Mode Entry Idle/Active H L H X X X L H H H X X X X 6, 7 Power Down Mode Exit Any (Power Down) L H X X X X 6, 7 H X X X L H H H 5 1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other deck. Refer to the Current State Truth Table. 2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 0,1 selects bank 1; BS0, BS1 = 1,0 selects bank 2; BS0, BS1 = 1,1 selects bank 3. 3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency. 4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data Read and Write operations. One clock delay is required for mode entry and exit. 5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two clock delay. DQM also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency). 6. All banks must be precharged before entering the Power Down Mode.(If this command is issued during a burst operation, the device state will be Clock Suspend Mode.)The Power Down Mode does not perform any refresh operations, therefore the device can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit. 7. A No Operation or Device Deselect command is required on the next clock edge following CKE going high. 8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Absolute Maximum Ratings Symbol VDD VDDQ VIN VOUT TA Parameter Rating Units Notes Power Supply Voltage -0.3 to +4.6 V 1 Power Supply Voltage for Output -0.3 to +4.6 V 1 Input Voltage -0.3 to VDD+0.3 V 1 Output Voltage -0.3 to VDD+0.3 V 1 0 to +70 °C 1 -55 to +125 °C 1 Power Dissipation 1.0 W 1 Short Circuit Output Current 50 mA 1 Operating Temperature (ambient) TSTG Storage Temperature PD IOUT 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended DC Operating Conditions (TA = 0 to 70°C) Rating Symbol Parameter Units Notes 3.6 V 1 3.3 3.6 V 1 2.0 — VDD + 0.3 V 1, 2 -0.3 — 0.8 V 1, 3 Min. Typ. Max. Supply Voltage 3.0 3.3 Supply Voltage for Output 3.0 VIH Input High Voltage VIL Input Low Voltage VDD VDDQ 1. All voltages referenced to VSS and VSSQ. 2. VIH (max) = VDD/VDDQ + 1.2V for pulse width ≤ 5ns. 3. VIL (min) = VSS/VSSQ - 1.2V for pulse width ≤ 5ns. Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V) Symbol CI CO Parameter Min. Typ. Max. Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM) 2.5 2.9 3.8 Input Capacitance (CLK) 2.5 3.2 3.5 Output Capacitance (DQ0 - DQ3) 4.0 5.4 6.5 Units Notes pF 1 1. Multiply given planar values by 2 for 2-High stacked device except CS. 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V) Symbol Parameter Min. Max. Units Notes II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V -1 +1 µA 1 IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ) -1 +1 µA 1 VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 — V VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) — 0.4 V 1. Multiply given planar values by 2 for 2-High stacked device. Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ± 0.3V) Symbol Test Condition Speed -75A Units Notes ICC1 1 bank operation tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 75 mA 1, 2, 3 ICC2P CKE ≤ VIL(max), tCK = min, CS =VIH(min) 1 mA 1 ICC2PS CKE ≤ VIL(max), tCK = Infinity, CS =VIH(min) 1 mA 1 ICC2N CKE ≥ VIH(min), tCK = min, CS =VIH (min) 35 mA 1, 5 ICC2NS CKE ≥ VIH(min), tCK = Infinity, 5 mA 1, 7 ICC3N CKE ≥ VIH(min), tCK = min, CS =VIH (min) 40 mA 1, 5 ICC3P CKE ≤ VIL(max), tCK = min 7 mA 1, 6 Operating Current (Burst Mode) ICC4 tCK = min, Read/ Write command cycling, Multiple banks active, gapless data,BL=4 120 mA 1, 3, 4 Auto (CBR) Refresh Current ICC5 tCK = min, tRC = tRC(min) CBR command cycling 145 mA 1 Self Refresh Current ICC6 CKE ≤ 0.2V 1 mA 1 Parameter Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode No Operating Current (Active state: 4 bank) 1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the other deck. 2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed up to three times during tRC(min). 3. The specified values are obtained with the output open. 4. Input signals are changed once during tCK(min). 5. Input signals are changed once during three clock cycles. 6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ). 7. Input signals are stable. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V) 1. See full specification (19L3264) for power-up requirements. 2. The Transition time is measured between VIH and VIL (or between VIL and VIH). 3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 4. AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V crossover point 5. AC measurements assume tT = 1.2ns. AC Characteristics Diagram tT tCKL Clock tSETUP tCKH VIH 1.4V VIL tHOLD Output Zo = 50Ω Input 1.4V AC Output Load Circuit tOH tAC Output 50pF tLZ 1.4V Clock and Clock Enable Parameters -75A Symbol Parameter Units Min. Max. Notes tCK3 Clock Cycle Time, CAS Latency = 3 7.5 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 — — ns tAC3 Clock Access Time, CAS Latency = 3 — 5.4 ns 1 tAC2 Clock Access Time, CAS Latency = 2 — — ns 1 tCKH Clock High Pulse Width 2.5 — ns tCKL Clock Low Pulse Width 2.5 — ns tCES Clock Enable Set-up Time 1.5 — ns tCEH Clock Enable Hold Time 0.8 — ns tSB Power down mode Entry Time 0 7.5 ns tT Transition Time (Rise and Fall) 0.5 10 ns 1. Access time is measured at 1.4V. 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Common Parameters -75A Symbol Parameter Units Min. Max. Notes tCS Command Setup Time 1.5 — ns tCH Command Hold Time 0.8 — ns tAS Address and Bank Select Set-up Time 1.5 — ns tAH Address and Bank Select Hold Time 0.8 — ns tRCD RAS to CAS Delay 20 — ns 1 tRC Bank Cycle Time 67.5 — ns 1 tRAS Active Command Period 45 100K ns 1 tRP Precharge Time 20 — ns 1 tRRD Bank to Bank Delay Time 15 — ns 1 tCCD CAS to CAS Delay Time 1 — CLK 1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Mode Register Set Cycle -75A Symbol tRSC Parameter Mode Register Set Cycle Time Min. Max. 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Read Cycle -75A Symbol Parameter Units Notes — ns 1 Min. Max. 2.7 tOH Data Out Hold Time tLZ Data Out to Low Impedance Time 0 — ns tHZ Data Out to High Impedance Time 3 5.4 ns DQM Data Out Disable Latency 2 — CLK tDQZ 2 1. Data Out Hold Time with no load must meet 1.8ns. 2. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Refresh Cycle -75A Symbol Parameter Units Min. Max. tREF Refresh Period — 64 ms tRFC Row Refresh Cycle Time 75 — ns Self Refresh Exit Time 10 — ns tSREX Write Cycle -75A Symbol Parameter Units Min. Max. tDS Data In Set-up Time 1.5 — ns tDH Data In Hold Time 0.8 — ns tDPL Data input to Precharge 2 — CLK tDAL Data input to Activate 5 — CLK tDQW DQM Write Mask Latency 0 — CLK 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Clock Frequency and Latency Symbol Parameter -75A Units fCK Clock Frequency 133 MHz tCK Clock Cycle Time 7.5 ns tAA CAS Latency 3 CLK tRP Precharge Time 3 CLK tRCD RAS to CAS Delay 3 CLK tRC Bank Cycle Time 9 CLK tRAS Minimum Bank Active Time 6 CLK tDPL Data In to Precharge 2 CLK tDAL Data In to Active 5 CLK tRRD Bank to Bank Delay Time 2 CLK tCCD CAS to CAS Delay Time 1 CLK tWL Write Latency 0 CLK tDQW DQM Write Mask Latency 0 CLK tDQZ DQM Data Disable Latency 2 CLK tCSL Clock Suspend Latency 1 CLK ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Package Dimensions (400mil; 54 lead; Thin Small Outline Package) 22.22 ± 0.13 11.76 ± 0.20 10.16 ± 0.13 Detail A Lead #1 Seating Plane 0.10 0.80 Basic + 0.10 0.35 - 0.05 0.805REF 1.20 Max Detail A 0.25 Basic Gage Plane 0.5 ± 0.1 0.05 Min 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Stack Package Dimensions (400mil; 54 lead; 2 High Stack; Thin Small Outline J Lead Package) 3.20 Max 22.22 ± 0.28 9.90 ± 0.40 11.4 ± 0.25 10.15 ± 0.05 0.75 Min Lead #1 0.10 0.80 Basic 0.30 + 0.10 - 0.04 0.50 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 + 0.13 - 0.04 Seating Plane 46L8543.F46205 7/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM0364404 IBM03644B4 PC133 Synchronous DRAM - 64Mb Revision B Revision Log Revision Contents of Modification 1/14/99 Initial release. 3/1/99 Remove - 75D, 64Mb Rev C, and 256Mb Rev A. 3/21/99 Change tRP, tRCD for -75A (22.5 to 20ns). 7/99 Removed Preliminary. 46L8543.F46205 7/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 16 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Discontinued (8/99 - last order; 12/99 - last ship) International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant. Powered by ICminer.com Electronic-Library Service CopyRight 2003