ETC IBM0364804CT3C-360

.
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Features
• High Performance:
-68 -75A, -260, -360, -10,
Units
CL=3 CL=3 CL=2 CL=3 CL=3
fCK Clock Frequency
150
133
100
100
100
MHz
tCK Clock Cycle
6.67
7.5
10
10
10
ns
tAC Clock Access Time1
6
—
—
—
7
ns
tAC Clock Access Time2
—
5.4
6
6
9
ns
1. Terminated load. See AC Characteristics on page 41.
2. Unterminated load. See AC Characteristics on page 41.
•
•
•
•
•
Single Pulsed RAS Interface
Fully Synchronous to Positive Clock Edge
Four Banks controlled by A12/A13 (Bank Select)
Programmable CAS Latency: 2, 3
Programmable Burst Length: 1, 2, 4, 8, full-page
•
•
•
•
•
•
•
•
•
•
•
•
•
Programmable Wrap: Sequential or Interleave
Multiple Burst Read with Single Write Option
Automatic and Controlled Precharge Command
Data Mask for Read/Write control (x4, x8)
Dual Data Mask for byte control (x16)
Auto Refresh (CBR) and Self Refresh
Suspend Mode and Power Down Mode
Standard or Low Power operation
4096 refresh cycles/64ms
Random Column Address every CLK (1-N Rule)
Single 3.3V ± 0.3V Power Supply
LVTTL compatible
Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
Description
The IBM0364404, IBM0364804, and IBM0364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. IBM03644B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve highspeed data transfer rates of up to 150MHz by
employing a pipeline chip architecture that synchronizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 64Mbit single transistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an externally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
19L3265.E35856B
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and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device. Access to the lower or
upper DRAM in a stacked device is controlled by
CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be programmed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 150MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed,
depending on the operation being done. Auto
Refresh (CBR), Self Refresh, and Low Power operation are supported.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Assignments for Planar Components (Top View)
VDD
VDD
VDD
1
54
VSS
VSS
VSS
DQ0
VDDQ
DQ1
DQ2
DQ0
VDDQ
NC
DQ1
NC
VDDQ
NC
DQ0
2
3
4
5
53
52
51
50
NC
VSSQ
NC
DQ3
DQ7
VSSQ
NC
DQ6
DQ15
VSSQ
DQ14
DQ13
VSSQ
DQ3
DQ4
VDDQ
DQ5
VSSQ
NC
NC
VDDQ
NC
6
7
8
9
10
49
48
47
46
45
VDDQ
NC
NC
VSSQ
NC
VDDQ
NC
DQ5
VSSQ
NC
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ6
VSSQ
NC
DQ2
VDDQ
NC
DQ3
DQ1
11
44
DQ2
DQ4
DQ9
VSSQ
VSSQ
VSSQ
12
43
VDDQ
VDDQ
VDDQ
DQ7
VDD
NC
VDD
NC
VDD
NC
LDQM
NC
WE
WE
WE
CAS
CAS
CAS
RAS
RAS
RAS
CS
CS
CS
A13/BS0 A13/BS0 A13/BS0
13
14
15
16
17
18
19
20
42
41
40
39
38
37
36
35
NC
VSS
NC
DQM
CLK
CKE
NC
A11
NC
VSS
NC
DQM
CLK
CKE
NC
A11
DQ8
VSS
NC
UDQM
CLK
CKE
NC
A11
A12/BS1 A12/BS1 A12/BS1
A10/AP A10/AP
A10/AP
A0
A0
A0
21
22
23
34
33
32
A9
A8
A7
A9
A8
A7
A9
A8
A7
A1
A2
A1
A2
A1
A2
24
25
31
30
A6
A5
A6
A5
A6
A5
A3
VDD
A3
VDD
A3
VDD
26
27
29
28
A4
VSS
A4
VSS
A4
VSS
54-pin Plastic TSOP(II) 400 mil
4Mbit x 4 I/O x 4 Bank
IBM0364404
2Mbit x 8 I/O x 4 Bank
IBM0364804
1Mbit x 16 I/O x 4 Bank
IBM0364164
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 2 of 73
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.
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Assignments for 2 High Stack Package (Dual CS Pin) (Top View)
VDD
1
54
VSS
NC
VDDQ
NC
DQ0
2
3
4
5
53
52
51
50
NC
VSSQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
6
7
8
9
10
49
48
47
46
45
VDDQ
NC
NC
VSSQ
NC
DQ1
11
44
DQ2
VSSQ
12
43
VDDQ
NC
VDD
NC
WE
CAS
RAS
CS0/NC
A13/BS0
13
14
15
16
17
18
19
20
42
41
40
39
38
37
36
35
NC
VSS
NC
DQM
CLK
CKE
NC/CS1
A11
A12/BS1
A10/AP
A0
21
22
23
34
33
32
A9
A8
A7
A1
A2
24
25
31
30
A6
A5
A3
VDD
26
27
29
28
A4
VSS
54-pin Plastic TSOJ(II) 400 mil
(4Mbit x 4 I/O x 4 Bank) x 2High
IBM03644B4
* CS0 selects the lower DRAM in the stack.
* CS1 selects the upper DRAM in the stack.
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 3 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Pin Description
CLK
Clock Input
DQ0-DQ15
Data Input/Output
CKE
Clock Enable
DQM, LDQM, UDQM
Data Mask
CS (CS0, CS1)
Chip Select
VDD
Power (+3.3V)
RAS
Row Address Strobe
VSS
Ground
CAS
Column Address Strobe
VDDQ
Power for DQs (+3.3V)
WE
Write Enable
VSSQ
Ground for DQs
BS1, BS0 (A12, A13)
Bank Select
NC
No Connection
A0 - A11
Address Inputs
—
—
Input/Output Functional Description
Symbol
Type
Polarity
Function
CLK
Input
Positive
Edge
CKE
Input
Active
High
CS, CS0,
CS1
Input
CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables the
Active Low command decoder when high. When the command decoder is disabled, new commands are
ignored but previous operations continue.
RAS, CAS,
WE
Input
Active Low
BS1, BS0
(A12, A13)
Input
—
Selects which bank is to be active.
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the
clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode.
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to
be executed by the SDRAM.
A0 - A11
Input
—
During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9) when
sampled at the rising clock edge.
A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is
high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low,
autoprecharge is disabled.
During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control which
bank(s) to precharge. If A10 is high, all banks will be precharged regardless of the state of BS. If
A10 is low, then BS0 and BS1 are used to define which bank to precharge.
DQ0 - DQ15
InputOutput
—
Data Input/Output pins operate in the same manner as on conventional DRAMs.
The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high.
In x16 products, the LDQM and UDQM control the lower and upper byte I/O buffers, respectively.
In Read mode, DQM has a latency of two clock cycles and controls the output buffers like an output enable. DQM low turns the output buffers on and DQM high turns them off. In Write mode,
DQM has a latency of zero and operates as a word mask by allowing input data to be written if it is
low but blocks the write operation if DQM is high.
DQM
LDQM
UDQM
Input
Active
High
VDD, VSS
Supply
—
Power and ground for the input buffers and the core logic.
VDDQ VSSQ
Supply
—
Isolated power supply and ground for the output buffers to provide improved noise immunity.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 4 of 73
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Ordering Information - Planar Devices (Single CS Pin)
Part Number
CAS Latencies
IBM
IBM0364404CT3C-75A
Power SupClock Cycle
ply
3
Power2
Org.
400mil
Type II TSOP-54
SP
x4
400mil
Type II TSOP-54
SP
x8
400mil
Type II TSOP-54
SP
x16
7.5ns
IBM0364404CT3C-260
3.3V
IBM0364404CT3C-360
Package
2, 3
10ns
3
7.5ns
IBM0364404CT3C-10
IBM0364804CT3C-75A
IBM0364804CT3C-260
3.3V
IBM0364804CT3C-360
2, 3
10ns
3
6.67ns
IBM0364804CT3C-10
IBM0364164CT3C-68
IBM0364164CT3C-260
3.3V
2, 3
IBM0364164CT3C-360
10ns
IBM0364164CT3C-10
IBM0364804PT3C-260
IBM0364804PT3C-360
2, 3
3.3V
10ns
400mil
Type II TSOP-54
LP
x8
2, 3
3.3V
10ns
400mil
Type II TSOP-54
LP
x16
Package
Power1
Org.
400mil Type II TSOJ-54
SP
x4
IBM0364804PT3C-10
IBM0364164PT3C-260
IBM0364164PT3C-360
IBM0364164PT3C-10
1. Part numbers manufactured by an IBM licensee and functionally equivalent to IBM parts.
2. SP: Standard Power; LP: Low Power.
Ordering Information - 2 High Stacked Devices (Dual CS Pin)
Part Number
CAS Latencies
IBM03644B4CT3C-75A
3
IBM03644B4CT3C-260
Power Supply
Clock Cycle
7.5ns
3.3V
2, 3
10ns
IBM03644B4CT3C-360
1. SP: Standard Power.
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 5 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Planar Block Diagram
Column Decoder
CKE Buffer
Row Decoder
Row Decoder
CLK
Cell Array
Memory Bank 0
Column Decoder
Cell Array
Memory Bank 1
CLK Buffer
Sense Amplifiers
Sense Amplifiers
Column
Address
Counter
Refresh
Counter
Mode Register
Data Control Circuitry
Control Signal
Generator
Address Buffers (14)
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12 (BS1)
A13 (BS0)
A10
Command Decoder
WE
DQX
Cell Array
Memory Bank 2
Sense Amplifiers
Column Decoder
Row Decoder
CAS
Row Decoder
CS
DQ0
DQM
Column Decoder
RAS
Data Input/Output Buffers
CKE
Cell Array
Memory Bank 3
Sense Amplifiers
Cell Array, per bank, for 4Mb x 4 DQ: 4096 Row x 1024 Col x 4 DQ (DQ0-DQ3).
Cell Array, per bank, for 2Mb x 8 DQ: 4096 Row x 512 Col x 8 DQ (DQ0-DQ7).
Cell Array, per bank, for 1Mb x 16 DQ: 4096 Row x 256 Col x 16 DQ (DQ0-DQ15).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 6 of 73
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Block Diagram (4Mbit x 4 I/O x 4 Bank) x 2-High
CS0
CS1
CKE
CLK
A11-A0
BS0,BS1
RAS
CAS
WE
DQM
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4Mb x 4 I/O x 4 Bank
DQ0
DQ1
DQ2
DQ3
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Power On and Initialization
The default power on state of the mode register is supplier specific and may be undefined. The following
power on and initialization sequence guarantees the device is preconditioned to each users specific needs.
Like a conventional DRAM, the Synchronous DRAM must be powered up and initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when
the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the
input pins or VDD supplies. The CLK signal must be started at the same time. After power on, an initial pause
of 200µs is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the
initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued
to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required. These may
be done before or after programming the Mode Register. Failure to follow these steps may lead to unpredictable start-up modes.
Programming the Mode Register
For application flexibility, CAS latency, burst length, burst sequence, and operation type are user defined variables and must be programmed into the SDRAM Mode Register with a single Mode Register Set Command.
Any content of the Mode Register can be altered by re-executing the Mode Register Set Command. If the
user chooses to modify only a subset of the Mode Register variables, all four variables must be redefined
when the Mode Register Set Command is issued.
After initial power up, the Mode Register Set Command must be issued before read or write cycles may
begin. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of
RAS, CAS, CS, and WE at the positive edge of the clock. The address input data during this cycle defines the
parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to tRSC has elapsed.
CAS Latency
The CAS latency is a parameter that is used to define the delay from when a Read Command is registered on
a rising clock edge to when the data from that Read Command becomes available at the outputs. The CAS
latency is expressed in terms of clock cycles and can have a value of 2 or 3 cycles. The value of the CAS
latency is determined by the speed grade of the device and the clock frequency that is used in the application.
A table showing the relationship between the CAS latency, speed grade, and clock frequency appears in the
Electrical Characteristics section of this document. Once the appropriate CAS latency has been selected it
must be programmed into the mode register after power up, for an explanation of this procedure see Programming the Mode Register in the previous section.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 73
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Mode Register Operation (Address Input For Mode Set)
A13
A12 A11
A10
A9
A8
A7
A6
Operation Mode
A5
A4
CAS Latency
A3
A2
BT
A1
A0
Address
Bus (Ax)
Mode
Register(Mx)
Burst Length
Burst Type
M3
Type
0
Sequential
1
Interleave
Operation Mode
M13 M12 M11 M10 M9 M8 M7
Burst Length
Mode
Length
0
0
0
0
0
0
0
Normal
M2
M1
M0
0
0
0
0
1
0
0
Multiple Burst with
Single Write
0
0
0
1
1
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
Sequential Interleave
CAS Latency
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M6
M5
M4
Latency
1
0
0
Reserved Reserved
0
0
0
Reserved
1
0
1
Reserved Reserved
1
0
Reserved Reserved
1
1
Full Page Reserved
0
0
1
Reserved
1
0
1
0
2
1
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Burst Mode Operation
Burst mode operation is used to provide a constant flow of data to memory locations (write cycle), or from
memory locations (read cycle). There are three parameters that define how the burst mode will operate.
These parameters include burst sequence, burst length, and operation mode. The burst sequence and burst
length are programmable, and are determined by address bits A0 - A3 during the Mode Register Set command. Operation mode is also programmable and is set by address bits A7 - A13.
The burst type is used to define the order in which the burst data will be delivered or stored to the SDRAM.
Two types of burst sequences are supported, sequential and interleaved. See the table below.
The burst length controls the number of bits that will be output after a Read Command, or the number of bits
to be input after a Write Command. The burst length can be programmed to have values of 1, 2, 4, 8 or full
page (actual page length is dependent on organization: x4, x8, or x16). Full page burst operation is only possible using the sequential burst type.
Burst operation mode can be normal operation or multiple burst with single write operation. Normal operation
implies that the device will perform burst operations on both read and write cycles until the desired burst
length is satisfied. Multiple burst with single write operation was added to support Write Through Cache operation. Here, the programmed burst length only applies to read cycles. All write cycles are single write operations when this mode is selected.
Burst Length and Sequence
Burst Length
2
4
8
Full Page (Note)
Starting Address (A2 A1 A0)
Sequential Addressing (decimal)
Interleave Addressing (decimal)
xx0
0, 1
0, 1
xx1
1, 0
1, 0
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 4, 5, 6, 7, 0
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 4, 5, 6, 7, 0, 1
2, 3, 0, 1, 6, 7, 4, 5
011
3, 4, 5, 6, 7, 0, 1, 2
3, 2, 1, 0, 7, 6, 5, 4
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 0, 1, 2, 3, 4
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 0, 1, 2, 3, 4, 5
6, 7, 4, 5, 2, 3, 0, 1
111
7, 0, 1, 2, 3, 4, 5, 6
7, 6, 5, 4, 3, 2, 1, 0
nnn
Cn, Cn+1, Cn+2, ......
Not Supported
Note: Page length is a function of I/O organization and column addressing.
x4 organization (CA0-CA9); Page Length = 1024 bits
x8 organization (CA0-CA8); Page Length = 512 bits
x16 organization (CA0-CA7); Page Length = 256 bits
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 10 of 73
19L3265.E35856B
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Bank Activate Command
In relation to the operation of a fast page mode DRAM, the Bank Activate command corresponds to a falling
RAS signal. The Bank Activate command is issued by holding CAS and WE high with CS and RAS low at the
rising edge of the clock. The bank select address A12 - A13 is used to select the desired bank. The row
address A0 - A11 is used to determine which row to activate in the selected bank. Activation of banks within
both decks of a 2-High stacked device is allowed.
The Bank Activate command must be applied before any Read or Write operation can be executed. The
delay from when the Bank Activate command is applied to when the first read or write operation can begin
must meet or exceed the RAS to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank Activate command can be applied to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of
the device (tRC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B
and vice versa) is the Bank to Bank delay time (tRRD). The maximum time that each bank can be held active
is specified as tRAS(max).
Bank Activate Command Cycle
(CAS Latency = 3, tRCD = 3)
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
..........
Bank A
Col. Addr.
Bank A
Row Addr.
ADDRESS
..........
RAS-CAS delay (tRCD)
Bank A
Activate
COMMAND
NOP
Bank B
Row Addr.
Bank A
Row Addr.
RAS - RAS delay time (tRRD)
Write A
with Auto
Precharge
NOP
..........
Bank B
Activate
NOP
Bank A
Activate
NOP
: “H” or “L”
RAS Cycle time (tRC)
Bank Select
The Bank Select inputs, BS0 and BS1, determine the bank to be used during a Bank Activate, Precharge,
Read, or Write operation.
Bank Selection Bits
BS0
BS1
Bank
0
0
Bank 0
0
1
Bank 1
1
0
Bank 2
1
1
Bank 3
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Use is further subject to the provisions at the end of this document.
Page 11 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low). The address inputs determine the starting column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles up to 150 MHz. The number of serial data bits for
each access is equal to the burst length, which is programmed into the Mode Register. If the burst length is
full page, data is repeatedly read out or written until a Burst Stop or Precharge Command is issued.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (tREF) is what limits the number of random column accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address.
Precharging an active bank after each read or write operation is not necessary providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When more than one bank is activated,
interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length
and alternating the access and precharge operations between multiple banks, fast and seamless data access
operation among many different pages can be realized. When multiple banks are activated, column to column
interleave operation can be done between different pages. Finally, Read or Write Commands can be issued
to the same bank or between active banks on every clock cycle.
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Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst, the Mode Register
sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from the
start of the command to when the data from the first cell appears on the outputs is equal to the value of the
CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
NOP
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
NOP
NOP
NOP
NOP
DOUT A0
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
NOP
NOP
NOP
DOUT A3
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read Command continues to appear on the outputs until the CAS latency from
the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command
appears.
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Read Interrupted by a Read
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
READ A
READ B
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
tCK2, DQs
NOP
NOP
NOP
NOP
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT A0
DOUT B0
DOUT B1
DOUT B2
CAS latency = 3
tCK3, DQs
NOP
NOP
NOP
CAS latency = 4
tCK4, DQs
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DOUT B3
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Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a
high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first
or second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that
point the Write Command will have control of the DQ bus.
Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM high for CAS latency = 2 only.
Required to mask first bit of READ data.
DQM
COMMAND
CAS latency = 2
tCK2, DQs
NOP
READ A
WRITE A
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
DIN A0
DIN A1
DIN A2
DIN A3
NOP
NOP
NOP
CAS latency = 3
tCK3, DQs
: “H” or “L”
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Non-Minimum Read to Write Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
READ A
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
CL = 2: DQM needed to mask
first, second bit of READ data.
CAS latency = 2
tCK2, DQs
DIN A0
DIN A1
DIN A2
DIN A3
CL = 3: DQM needed to
mask first bit of READ data.
CAS latency = 3
tCK3, DQs
DIN A0
DIN A1
DIN A2
DIN A3
: DQM high for CAS latency = 2
: DQM high for CAS latency = 3
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Page 16 of 73
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Burst Write Command
The Burst Write command is initiated by having CS, CAS, and WE low while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. There is no CAS latency
required for burst write cycles. Data for the first burst write cycle must be applied on the DQ pins on the same
clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. When the burst has finished, any additional data
supplied to the DQ pins will be ignored.
Burst Write Operation
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
NOP
COMMAND
WRITE A
DIN A0
DQs
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
The first data element and the Write
are registered on the same clock edge.
NOP
NOP
NOP
Extra data is masked.
NOP
: “H” or “L”
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written
into the device until the programmed burst length is satisfied.
Write Interrupted by a Write
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
WRITE A
WRITE B
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
NOP
NOP
NOP
DIN B1
DIN B2
DIN B3
NOP
NOP
NOP
1 Clk Interval
DQs
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DIN A0
DIN B0
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Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is
registered. The DQs must be in the high impedance state at least one cycle before the interrupting read data
appears on the outputs to avoid data contention. When the Read Command is registered, any residual data
from the burst write cycle will be ignored. Data that is presented on the DQ pins before the Read Command is
initiated will actually be written to the memory.
Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
WRITE A
READ B
NOP
DIN A0
NOP
NOP
NOP
DOUT B0
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
DIN A0
Input data for the Write is masked.
: “H” or “L”
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Page 18 of 73
NOP
NOP
NOP
DOUT B3
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
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Non-Minimum Write to Read Interval
(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
WRITE A
NOP
DIN A0
DIN A1
DIN A0
DIN A1
READ B
NOP
Input data for the Write is masked.
NOP
NOP
DOUT B0
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B0
DOUT B1
DOUT B2
NOP
DOUT B3
Input data must be removed from the DQs at least one clock
cycle before the Read data appears on the outputs to avoid
data contention.
: “H” or “L”
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Burst Stop Command
Once a burst read or write operation has been initiated, there exist several methods in which to terminate the
burst operation prematurely. These methods include using another Read or Write Command to interrupt an
existing burst operation or using a Precharge Command to interrupt a burst cycle and close the active bank.
When interrupting a burst with another Read or Write Command care must be taken to avoid DQ contention.
If the burst length is full page, the Burst Stop Command may also be used to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the active bank.
Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is
defined by having RAS and CAS high with CS and WE low at the rising edge of the clock.
When using the Burst Stop Command during a burst read cycle, the data DQs go to a high impedance state
after a delay which is equal to the CAS Latency set in the Mode Register.
Termination of a Burst Read Operation
(Burst Length = Full Page, CAS Latency = 2, 3)
CLK
COMMAND
T0
READ A
T1
NOP
T2
T3
NOP
NOP
T4
T5
Burst
Stop
NOP
T6
NOP
T7
NOP
T8
NOP
The burst ends after a delay equal to the CAS latency.
CAS latency = 2
DOUT A0
tCK2, DQs
CAS latency = 3
tCK3, DQs
DOUT A1
DOUT A2
DOUT A3
DOUT A0
DOUT A1
DOUT A2
DOUT A3
If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the
burst write cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Termination of a Burst Write Operation
T0
T1
T2
T3
T4
(Burst Length = Full Page, CAS latency = 2, 3)
T5
T6
T7
T8
CLK
COMMAND
CAS latency = 2,3
DQs
NOP
WRITE A
DIN A0
NOP
NOP
DIN A1
DIN A2
Burst
Stop
NOP
NOP
NOP
NOP
: “H” or “L”
Input data for the Write is masked.
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Auto-Precharge Operation
Before a new row in an active bank can be opened, the active bank must be precharged using either the Precharge Command or the auto-precharge function. When a Read or a Write Command is given to the SDRAM,
the CAS timing accepts one extra address, column address A10, to allow the active bank to automatically
begin precharge at the earliest possible moment during the burst read or write cycle. If A10 is low when the
Read or Write Command is issued, then normal Read or Write burst operation is executed and the bank
remains active at the completion of the burst sequence. If A10 is high when the Read or Write Command is
issued, then the auto-precharge function is engaged. During auto-precharge, a Read Command will execute
as normal with the exception that the active bank will begin to precharge before all burst read cycles have
been completed. Regardless of burst length, the precharge will begin (CAS latency - 1) clocks prior to the last
data output. Auto-precharge can also be implemented during Write commands.
A Read or Write Command without auto-precharge can be terminated in the midst of a burst operation. However, a Read or Write Command with auto-precharge cannot be interrupted by a command to the same bank.
Therefore use of a Read, Write, or Precharge Command to the same bank is prohibited during a read or write
cycle with auto-precharge until the entire burst operation is completed. Once the precharge operation has
started the bank cannot be reactivated until the Precharge time (tRP) has been satisfied. It should be noted
that the device will not respond to the Auto-Precharge command if the device is programmed for full page
burst read or write cycles, or full page burst read cycles with single write operation.
When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy tRAS(min). If this interval does not satisfy tRAS(min) then
tRCD must be extended.
Burst Read with Auto-Precharge
(Burst Length = 1, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
Auto-Precharge
CAS latency = 2
tCK2, DQs
CAS latency = 3
tCK3, DQs
Begin Auto-precharge
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
*
tRP‡
DOUT A0
*
tRP‡
DOUT A0
*‡
Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
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Burst Read with Auto-Precharge
(Burst Length = 2, CAS Latency = 2, 3)
CLK
COMMAND
T0
T1
READ A
Auto-Precharge
NOP
T2
T3
NOP
T4
NOP
tCK2, DQs
DOUT A0
NOP
NOP
NOP
T7
T8
NOP
NOP
DOUT A1
*
tRP‡
CAS latency = 3
tCK3, DQs
T6
*
tRP‡
CAS latency = 2
T5
DOUT A0
DOUT A1
Begin Auto-precharge
*‡
Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Burst Read with Auto-Precharge
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ A
Auto-Precharge
NOP
NOP
NOP
NOP
DOUT A0
DOUT A1
DOUT A2
*
*
tRP‡
DOUT A0
Begin Auto-precharge
NOP
NOP
DOUT A3
CAS latency = 3
tCK3, DQs
NOP
tRP‡
CAS latency = 2
tCK2, DQs
NOP
DOUT A1
DOUT A2
*‡
DOUT A3
Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
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Although a Read Command with auto-precharge can not be interrupted by a command to the same bank, it
can be interrupted by a Read or Write Command to a different bank. If the command is issued before autoprecharge begins then the precharge function will begin with the new command. The bank being auto-precharged may be reactivated after the delay tRP.
Burst Read with Auto-Precharge Interrupted by Read
(Burst Length = 4, CAS Latency = 2, 3)
CLK
COMMAND
T0
READ A
Auto-Precharge
T1
NOP
T2
READ B
T3
T4
NOP
NOP
tCK2, DQs
DOUT A0
DOUT A1
DOUT B0
tCK3, DQs
T7
NOP
NOP
NOP
DOUT B1
DOUT B2
DOUT B3
DOUT B1
DOUT B2
T8
NOP
*
tRP‡
CAS latency = 3
T6
*
tRP‡
CAS latency = 2
T5
DOUT A0
DOUT A1
*‡
DOUT B0
DOUT B3
Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
If interrupting a Read Command with auto-precharge with a Write Command, DQM must be used to avoid DQ
contention.
Burst Read with Auto-Precharge Interrupted by Write
(Burst Length = 8, CAS Latency = 2)
CLK
COMMAND
T0
READ A
Auto-Precharge
T1
NOP
T2
NOP
T3
NOP
T4
T5
WRITE B
tRP‡
CAS latency = 2
tCK2, DQs
NOP
DOUT A0
DOUT B0
DOUT B1
T6
NOP
T7
NOP
T8
NOP
*
DOUT B2
DOUT B3
DOUT B4
DQM
*‡
Bank can be reactivated at completion of tRP.
tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
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If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The bank
undergoing auto-precharge cannot be reactivated until tDAL, Data-in to Active delay, is satisfied.
Burst Write with Auto-Precharge
T0
T1
T2
T3
(Burst Length = 2, CAS Latency = 2, 3)
T5
T6
T7
T8
T4
CLK
COMMAND
WRITE A
Auto-Precharge
NOP
NOP
DIN A0
*
tDAL‡
DIN A0
NOP
NOP
DIN A1
CAS latency = 3
tCK3, DQs
NOP
NOP
NOP
*
tDAL‡
CAS latency = 2
tCK2, DQs
NOP
DIN A1
*‡
Bank can be reactivated at completion of tDAL.
Number of clocks required depends on clock cycle
time and speed sort.
See the Clock Frequency and Latency table.
Similar to the Read Command, a Write Command with auto-precharge can not be interrupted by a command
to the same bank. It can be interrupted by a Read or Write Command to a different bank, however. The precharge function will be initiated by the new command. After the Data-in to Active, delay, tDAL, is satisfied the
bank may be reactivated.
Burst Write with Auto-Precharge Interrupted by Write
T0
T1
T2
T3
T4
T5
(Burst Length = 4, CAS Latency = 3)
T6
T7
T8
CLK
COMMAND
WRITE A
Auto-Precharge
NOP
WRITE B
DIN A0
DIN A1
DIN B0
DIN B1
NOP
NOP
NOP
NOP
NOP
*
tDAL‡
CAS latency = 3
tCK3, DQs
NOP
DIN B2
DIN B3
*‡
Bank can be reactivated at completion of tDAL.
Number of clocks required depends on clock cycle
time and speed sort.
See the Clock Frequency and Latency table.
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Page 24 of 73
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Burst Write with Auto-Precharge Interrupted by Read
T0
CLK
COMMAND
WRITE A
Auto-Precharge
T1
NOP
T2
T3
NOP
READ B
T5
NOP
NOP
DIN A0
DIN A1
(Burst Length = 4, CAS Latency = 3)
T6
T7
T8
NOP
NOP
NOP
*
tDAL‡
CAS latency = 3
tCK3, DQs
T4
DIN A2
DOUT B0
*‡
DOUT B1
DOUT B2
Bank A can be reactivated at completion of tDAL.
Number of clocks required depends on clock cycle
time and speed sort.
See the Clock Frequency and Latency table.
Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is triggered when CS, RAS, and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three
address bits, A10, A12, and A13, are used to define which bank(s) is to be precharged when the command is
issued.
Bank Selection for Precharge by Address Bits
A10
Bank Select
Precharged Bank(s)
LOW
BS0, BS1
Single bank defined by BS0, BS1
HIGH
DON’T CARE
All Banks
For read cycles, the Precharge Command may be applied (CAS latency - 1) prior to the last data output. For
write cycles, a delay must be satisfied from the start of the last burst write cycle until the Precharge Command
can be issued. This delay is known as tDPL, Data-in to Precharge delay.
After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write
access can be executed. The delay between the Precharge Command and the Activate Command must be
greater than or equal to the Precharge time (tRP).
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Burst Read Followed by the Precharge Command
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ Ax0
NOP
NOP
NOP
NOP
Precharge A
NOP
tRP
CAS latency = 2
DOUT Ax0
tCK2, DQs
DOUT Ax1
DOUT Ax2
*
NOP
NOP
*
DOUT Ax3
Bank A can be reactivated at completion of tRP.
Burst Write Followed by the Precharge Command
(Burst Length = 2, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
Activate
Bank Ax
NOP
WRITE Ax0
NOP
NOP
tDPL‡
Precharge A
NOP
NOP
tRP‡
*
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax1
*‡
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Page 26 of 73
Bank can be reactivated at completion of tRP.
tDPL and tRP are functions of clock cycle and speed sort.
See the Clock Frequency and Latency table.
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Precharge Termination
The Precharge Command may be used to terminate either a burst read or burst write operation. When the
Precharge command is issued, the burst operation is terminated and bank precharge begins. For burst read
operations, valid data will continue to appear on the data bus as a function of CAS Latency.
Burst Read Interrupted by Precharge
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
READ Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
tCK2, DQs
DOUT Ax0
DOUT Ax1
DOUT Ax2
DOUT Ax3
*
tRP‡
CAS latency = 3
tCK3, DQs
DOUT Ax0
DOUT Ax1
NOP
*
tRP‡
CAS latency = 2
NOP
DOUT Ax2
DOUT Ax3
*
Bank A can be reactivated at completion of tRP.
‡ tRP is a function of clock cycle time and speed sort.
See the Clock Frequency and Latency table.
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64Mb Synchronous DRAM - Die Revision C
Burst write operations will be terminated by the Precharge command. The last write data that will be properly
stored in the device is that write data that is presented to the device a number of clock cycles prior to the Precharge command equal to the Data-in to Precharge delay, tDPL.
Precharge Termination of a Burst Write
(Burst Length = 8, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
COMMAND
NOP
NOP
WRITE Ax0
NOP
NOP
NOP
Precharge A
NOP
NOP
DQM
tDPL‡
CAS latency = 2
tCK2, DQs
DIN Ax0
DIN Ax1
DIN Ax2
tDPL‡
CAS latency = 3
tCK3, DQs
DIN Ax0
DIN Ax1
DIN Ax2
‡ tDPL is an asynchronous timing and may be completed in one or two clock cycles
depending on clock cycle time.
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Page 28 of 73
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Automatic Refresh Command (CAS before RAS Refresh)
When CS, RAS, and CAS are held low with CKE and WE high at the rising edge of the clock, the chip enters
the Automatic Refresh mode (CBR). All banks of the SDRAM must be precharged and idle for a minimum of
the Precharge time (tRP) before the Auto Refresh Command (CBR) can be applied. For a stacked device,
both decks may be refreshed at the same time using Automatic Refresh Mode. An address counter, internal
to the device provides the address during the refresh cycle. No control of the external address pins is
required once this cycle has started.
When the refresh cycle has completed, all banks of the SDRAM will be in the precharged (idle) state. A delay
between the Auto Refresh Command (CBR) and the next Activate Command or subsequent Auto Refresh
Command must be greater than or equal to the RAS cycle time (tRC).
Self Refresh Command
The SDRAM device has a built-in timer to accommodate Self Refresh operation. The Self Refresh Command
is defined by having CS, RAS, CAS, and CKE held low with WE high at the rising edge of the clock. All banks
must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held
low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the
external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The user may halt the external clock while the device is in Self Refresh mode, however,
the clock must be restarted before the device can exit Self Refresh operation. Once the clock is cycling, the
device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the
device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the
RAS cycle time (tRC) plus the Self Refresh exit time (tSREX). When using Self Refresh, both decks of a
stacked device may be refreshed at the same time.
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64Mb Synchronous DRAM - Die Revision C
Power Down Mode
In order to reduce standby power consumption, two power down modes are available: Precharge and Active
Power Down mode. To enter Precharge Power Down mode, all banks must be precharged and the necessary precharge delay (tRP) must occur before the SDRAM can enter the power down mode. If a bank is activated but not performing a Read or Write operation, Active Power Down mode will be entered. (Issuing a
Power Down Mode Command when the device is performing a Read or Write operation causes the device to
enter Clock Suspend mode. See the following section.) Once the Power Down mode is initiated by holding
CKE low, all of the receiver circuits except CKE are gated off. The Power Down mode does not perform any
refresh operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(tREF) of the device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command (or
Device Deselect Command) is required on the next rising clock edge.
Power Down Mode Exit Timing
Tm
Tm+1
Tm+2
Tm+3
Tm+4
Tm+5
Tm+6
Tm+7
Tm+ 8
COMMAND
NOP
NOP
NOP
NOP
NOP
CLK
tCK
CKE
tCES(min)
COMMAND
NOP
: “H” or “L”
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Page 30 of 73
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Data Mask
The SDRAM has a Data Mask function that can be used in conjunction with data read and write cycles. When
the Data Mask is activated (DQM high) during a write cycle, the write operation is prohibited immediately
(zero clock latency). If the Data Mask is activated during a read cycle, the data outputs are disabled and
become high impedance after a two-clock delay, independent of CAS latency.
Data Mask Activated during a Read Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
NOP
READ A
DQs
NOP
NOP
DOUT A0
NOP
NOP
DOUT A1
NOP
NOP
NOP
A two-clock delay before
the DQs become Hi-Z
: “H” or “L”
No Operation Command
The No Operation Command should be used in cases when the SDRAM is in a idle or a wait state. The purpose of the No Operation Command is to prevent the SDRAM from registering any unwanted commands
between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held
high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is
still executing, such as a burst read or write cycle.
Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect Command
occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.
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64Mb Synchronous DRAM - Die Revision C
Clock Suspend Mode
During normal access mode, CKE is held high, enabling the clock. When CKE is registered low while at least
one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends or “freezes” any clocked operation that was currently being executed. There is a oneclock delay between the registration of CKE low and the time at which the SDRAM’s operation suspends.
While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend
mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when
Clock Suspend mode is exited.
When the operation of the SDRAM is suspended during the execution of a Burst Read operation, the last
valid data output onto the DQ pins will be actively held valid until Clock Suspend mode is exited.
Clock Suspend during a Read Cycle
T0
T1
T2
T3
T4
T5
(Burst Length = 4, CAS Latency = 2)
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
NOP
COMMAND
READ A
NOP
NOP
DQs
NOP
DOUT A0
DOUT A2
DOUT A1
: “H” or “L”
NOP
DOUT element at the DQs when the
suspend operation starts is held valid
If Clock Suspend mode is initiated during a burst write operation, the input data is masked and is ignored until
the Clock Suspend mode is exited.
Clock Suspend during a Write Cycle
(Burst Length = 4, CAS Latency = 2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
CKE
A one clock delay to exit
the Suspend command
A one clock delay before
suspend operation starts
COMMAND
DQs
NOP
WRITE A
DIN A0
NOP
NOP
NOP
DIN A1
DIN A2
DIN A3
: “H” or “L”
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NOP
DIN is masked during the Clock Suspend Period
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64Mb Synchronous DRAM - Die Revision C
Command Truth Table (See note 1)
CKE
Function
Device State
Previous
Cycle
Current
Cycle
CS
RAS
CAS
WE
DQM
A12,
A13
A10
A11, A9Notes
A0
Mode Register Set
Idle
H
X
L
L
L
L
X
Auto (CBR) Refresh
Idle
H
H
L
L
L
H
X
X
X
X
Entry Self Refresh
Idle
H
L
X
X
X
X
X
X
X
X
L
L
L
H
H
X
X
X
L
H
H
H
OP Code
Exit Self Refresh
Idle (SelfRefresh)
L
H
Single Bank Precharge
See Current
State Table
H
X
L
L
H
L
X
BS
L
X
Precharge all Banks
See Current
State Table
H
X
L
L
H
L
X
X
H
X
Bank Activate
Idle
H
X
L
L
H
H
X
BS
Write
Active
H
X
L
H
L
L
X
BS
L
Column
2
Write with Auto-Precharge Active
H
X
L
H
L
L
X
BS
H
Column
2
Read
Row Address
2
2
Active
H
X
L
H
L
H
X
BS
L
Column
2
Read with Auto-Precharge Active
H
X
L
H
L
H
X
BS
H
Column
2
Burst Termination
H
X
L
H
H
L
X
X
X
X
3, 8
Active
No Operation
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect
Any
H
X
H
X
X
X
X
X
X
X
Clock Suspend Mode
Entry
Active
H
L
X
X
X
X
X
X
X
X
Clock Suspend Mode Exit
Active
L
H
X
X
X
X
X
X
X
X
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Mask/Output Disable Active
H
X
X
X
X
X
H
X
X
X
Power Down Mode Entry
Idle/Active
H
L
X
X
X
X
6, 7
Power Down Mode Exit
Any (Power
Down)
L
H
X
X
X
X
6, 7
H
X
X
X
L
H
H
H
H
X
X
X
L
H
H
H
4
5
1. All of the SDRAM operations are defined by states of CS, WE, RAS, CAS, and DQM at the positive rising edge of the clock.Operation of both decks of a stacked device at the same time is allowed, depending on the operation being performed on the other
deck. Refer to the Current State Truth Table.
2. Bank Select (BS0, BS1): BS0, BS1 = 0,0 selects bank 0; BS0, BS1 = 0,1 selects bank 1; BS0, BS1 = 1,0 selects bank 2; BS0, BS1
= 1,1 selects bank 3.
3. During a Burst Write cycle there is a zero clock delay; for a Burst Read cycle the delay is equal to the CAS latency.
4. During normal access mode, CKE is held high and CLK is enabled. When it is low, it freezes the internal clock and extends data
Read and Write operations. One clock delay is required for mode entry and exit.
5. The DQM has two functions for the data DQ Read and Write operations. During a Read cycle, when DQM goes high at a clock timing the data outputs are disabled and become high impedance after a two-clock delay. DQM also provides a data mask function for
Write cycles. When it activates, the Write operation at the clock is prohibited (zero clock latency).
6. All banks must be precharged before entering the Power Down Mode. (If this command is issued during a burst operation, the
device state will be Clock Suspend Mode.) The Power Down Mode does not perform any refresh operations; therefore the device
can’t remain in this mode longer than the Refresh period (tREF) of the device. One clock delay is required for mode entry and exit.
7. A No Operation or Device Deselect Command is required on the next clock edge following CKE going high.
8. Device state is full page burst operation. Use of this command to terminate other burst length operations is illegal.
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Clock Enable (CKE) Truth Table
CKE
Current State
Self Refresh
Power Down
All Banks Idle
Any State
other than
listed above
Previous
Cycle
Command
Current
Cycle
CS
RAS
CAS
WE
Action
A12,A13 A11 - A0
Notes
H
X
X
X
X
X
X
X
INVALID
1
L
H
H
X
X
X
X
X
Exit Self Refresh with Device Deselect
2
L
H
L
H
H
H
X
X
Exit Self Refresh with No Operation
2
L
H
L
H
H
L
X
X
ILLEGAL
2
L
H
L
H
L
X
X
X
ILLEGAL
2
L
H
L
L
X
X
X
X
ILLEGAL
2
L
L
X
X
X
X
X
X
Maintain Self Refresh
H
X
X
X
X
X
X
X
INVALID
L
H
H
X
X
X
X
X
Power Down mode exit, all banks idle
2
L
H
L
X
X
X
X
X
ILLEGAL
2
X
X
Maintain Power Down Mode
L
L
X
X
X
X
H
H
H
X
X
X
H
H
L
H
X
H
H
L
L
H
X
H
H
L
L
L
H
H
H
L
L
L
L
H
L
H
X
X
X
H
L
L
H
X
X
H
L
L
L
H
X
H
L
L
L
L
H
1
3
Refer to the Idle State section of the
Current State Truth Table
X
3
3
X
X
OP Code
CBR Refresh
Mode Register Set
4
3
Refer to the Idle State section of the
Current State Truth Table
3
3
X
X
OP Code
Entry Self Refresh
4
H
L
L
L
L
L
L
X
X
X
X
X
X
X
Power Down
Mode Register Set
H
H
X
X
X
X
X
X
Refer to operations in the Current
State Truth Table
4
H
L
X
X
X
X
X
X
Begin Clock Suspend next cycle
L
H
X
X
X
X
X
X
Exit Clock Suspend next cycle
L
L
X
X
X
X
X
X
Maintain Clock Suspend
5
1. For the given Current State CKE must be low in the previous cycle.
2. When CKE has a low to high transition, the clock and other inputs are re-enabled asynchronously. The minimum setup time for
CKE (tCES) must be satisfied. When exiting power down mode, a NOP command (or Device Deselect Command) is required on
the first rising clock after CKE goes high (see page 30).
3. The address inputs (A13 - A0) depend on the command that is issued. See the Idle State section of the Current State Truth Table
for more information.
4. The Precharge Power Down Mode, the Self Refresh Mode, and the Mode Register Set can only be entered from the all banks idle
state.
5. Must be a legal command as defined in the Current State Truth Table.
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64Mb Synchronous DRAM - Die Revision C
Current State Truth Table
Current State
Idle
Row Active
Read
Write
(Part 1 of 3)(See note 1)
Command
CS RAS CAS WE A12,A13
A11 - A0
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
Description
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write w/o Precharge
Read w/o Precharge
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Action
Notes
Set the Mode Register
Start Auto or Self Refresh
No Operation
Activate the specified bank and row
ILLEGAL
ILLEGAL
No Operation
No Operation
No Operation or Power Down
ILLEGAL
ILLEGAL
Precharge
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation
No Operation
No Operation
ILLEGAL
ILLEGAL
Terminate Burst; Start the Precharge
ILLEGAL
Terminate Burst; Start the Write cycle
Terminate Burst; Start a new Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
Terminate Burst; Start the Precharge
ILLEGAL
Terminate Burst; Start a new Write cycle
Terminate Burst; Start the Read cycle
Terminate the Burst
Continue the Burst
Continue the Burst
2
2, 3
4
4
5
6
4
7, 8
7, 8
4
8, 9
8, 9
4
8, 9
8, 9
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode
is entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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Current State Truth Table
Current State
Read with
Auto Precharge
Write with
Auto Precharge
Precharging
Row
Activating
(Part 2 of 3)(See note 1)
Command
CS RAS CAS WE A12,A13
A11 - A0
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
L
H
H
L
X
X
L
H
H
H
X
X
H
X
X
X
X
X
L
L
L
L
OP Code
L
L
L
H
X
X
X
Description
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
Mode Register Set
Auto or Self Refresh
Precharge
Action
Notes
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Continue the Burst
Continue the Burst
ILLEGAL
ILLEGAL
No Operation; Bank(s) idle after tRP
L
L
H
L
BS
L
L
L
L
H
H
H
L
L
H
L
H
BS
BS
BS
L
H
H
L
X
X
Burst Termination
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Bank(s) idle after tRP
L
H
H
H
X
X
No Operation
No Operation; Bank(s) idle after tRP
H
X
X
X
X
Device Deselect
No Operation; Bank(s) idle after tRP
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
X
BS
BS
BS
BS
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
L
H
H
L
X
X
Burst Termination
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Row Active after tRCD
L
H
H
H
X
X
No Operation
No Operation; Row Active after tRCD
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tRCD
Row Address Bank Activate
Column
Write
Column
Read
X
OP Code
X
X
Row Address
Column
Column
4
4
4
4
4
4
4
4
4
4
4
4
4, 10
4
4
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode
is entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
©IBM Corporation. All rights reserved.
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Page 36 of 73
19L3265.E35856B
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Current State Truth Table
Current State
Write
Recovering
Write
Recovering
with
Auto Precharge
Refreshing
Mode
Register
Accessing
(Part 3 of 3)(See note 1)
Command
CS RAS CAS WE A12,A13
A11 - A0
L
L
L
L
OP Code
L
L
L
H
X
X
L
L
H
L
BS
X
L
L
H
H
BS
Row Address
L
H
L
L
BS
Column
L
H
L
H
BS
Column
Description
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Action
Notes
L
H
H
L
X
X
Burst Termination
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
Start Write; Determine if Auto Precharge
Start Read; Determine if Auto Precharge
No Operation; Row Active after tDPL
L
H
H
H
X
X
No Operation
No Operation; Row Active after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Row Active after tDPL
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
L
H
H
L
X
X
Burst Termination
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Precharge after tDPL
L
H
H
H
X
X
No Operation
No Operation; Precharge after tDPL
H
X
X
X
X
X
Device Deselect
No Operation; Precharge after tDPL
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
X
BS
BS
BS
BS
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
L
H
H
L
X
X
Burst Termination
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after tRC
X
BS
BS
BS
BS
OP Code
X
X
Row Address
Column
Column
OP Code
X
X
Row Address
Column
Column
L
H
H
H
X
X
No Operation
No Operation; Idle after tRC
H
X
X
X
X
X
Device Deselect
No Operation; Idle after tRC
L
L
L
L
L
L
L
L
H
L
L
L
L
H
H
H
H
X
L
L
H
H
L
L
H
H
X
L
H
L
H
L
H
L
H
X
Mode Register Set
Auto or Self Refresh
Precharge
Bank Activate
Write
Read
Burst Termination
No Operation
Device Deselect
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
No Operation; Idle after two clock cycles
No Operation; Idle after two clock cycles
X
BS
BS
BS
BS
X
X
X
OP Code
X
X
Row Address
Column
Column
X
X
X
4
4
9
9
4
4
4, 9
4, 9
1. CKE is assumed to be active (high) in the previous cycle for all entries. The Current State is the state of the bank that the Command is being applied to.
2. All Banks must be idle; otherwise, it is an illegal action.
3. If CKE is active (high) the SDRAM will start the Auto (CBR) Refresh operation, if CKE is inactive (low) than the Self Refresh mode
is entered.
4. The Current State refers to only one of the banks. If BS selects this bank then the action is illegal. If BS selects the bank not being
referenced by the Current State then the action may be legal depending on the state of that bank.
5. If CKE is inactive (low) then the Power Down mode is entered; otherwise there is a No Operation.
6. The minimum and maximum Active time (tRAS) must be satisfied.
7. The RAS to CAS Delay (tRCD) must occur before the command is given.
8. Column address A10 is used to determine if the Auto Precharge function is activated.
9. The command must satisfy any bus contention, bus turn around, and/or write recovery requirements.
10. The command is illegal if the minimum bank to bank delay time (tRRD) is not satisfied.
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©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 37 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VIN
VOUT
TA
TSTG
PD
IOUT
Parameter
Rating
Units
Notes
Power Supply Voltage
-0.3 to +4.6
V
1
Power Supply Voltage for Output
-0.3 to +4.6
V
1
Input Voltage
-0.3 to VDD+0.3
V
1
Output Voltage
-0.3 to VDD+0.3
V
1
0 to +70
°C
1
-55 to +125
°C
1
Power Dissipation
1.0
W
1
Short Circuit Output Current
50
mA
1
Operating Temperature (ambient)
Storage Temperature
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Recommended DC Operating Conditions (TA = 0 to 70°C)
Rating
Symbol
Parameter
Units
Notes
3.6
V
1
3.3
3.6
V
1
2.0
—
VDD + 0.3
V
1, 2
-0.3
—
0.8
V
1, 3
Min.
Typ.
Max.
Supply Voltage
3.0
3.3
Supply Voltage for Output
3.0
VIH
Input High Voltage
VIL
Input Low Voltage
VDD
VDDQ
1. All voltages referenced to VSS and VSSQ.
2. VIH (max) = VDD/VDDQ + 1.2V for pulse width ≤ 5ns.
3. VIL (min) = VSS/VSSQ - 1.2V for pulse width ≤ 5ns.
Capacitance (TA = 25°C, f = 1MHz, VDD = 3.3V ±0.3V)
Symbol
CI
CO
Parameter
Min.
Typ
Max.
Units
Notes
Input Capacitance (A0-A11, BS0, BS1, CS, RAS, CAS, WE, CKE, DQM)
2.5
3.0
3.8
pF
1
Input Capacitance (CLK)
2.5
2.8
3.5
pF
1
Output Capacitance (DQ0 - DQ15)
4.0
4.5
6.5
pF
1
1. Multiply given planar values by 2 for 2-High stacked device except CS.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 38 of 73
19L3265.E35856B
01/00
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
DC Electrical Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
Symbol
Parameter
Min.
Max.
Units
Notes
II(L)
Input Leakage Current, any input
(0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V
-1
+1
µA
1
IO(L)
Output Leakage Current
(DOUT is disabled, 0.0V ≤ VOUT ≤ VDDQ)
-1
+1
µA
1
VOH
Output Level (LVTTL)
Output “H” Level Voltage (IOUT = -2.0mA)
2.4
—
V
VOL
Output Level (LVTTL)
Output “L” Level Voltage (IOUT = +2.0mA)
—
0.4
V
1. Multiply given planar values by 2 for 2-High stacked device.
DC Output Load Circuit
3.3 V
1200Ω
VOH (DC) = 2.4V, IOH = -2mA
Output
VOL (DC) = 0.4V, IOL = 2mA
50pF
19L3265.E35856B
01/00
870Ω
©IBM Corporation. All rights reserved.
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Page 39 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Operating, Standby, and Refresh Currents (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
Parameter
Notes
55
mA
1, 2, 3
1
1
mA
1, 8
1
1
1
mA
1, 8
35
25
25
25
mA
1, 5
6
6
6
6
6
mA
1, 7
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
45
40
30
30
30
mA
1, 5
ICC3P
CKE ≤ VIL(max), tCK = min,
3
3
3
3
3
mA
1, 6, 8
Operating Current
(Burst Mode)
ICC4
tCK = min,
Read/ Write command cycling,
Multiple banks active, gapless
data, BL = 4
135
120
90
90
90
mA
1, 3, 4
Auto (CBR) Refresh
Current
ICC5
tCK = min, tRC = tRC(min)
CBR command cycling
150
145
140
140
110
mA
1, 8
ICC6
SP
1
1
1
1
1
mA
Self Refresh Current
LP
400
400
400
400
400
µA
Precharge Standby
Current in Power Down
Mode
Precharge Standby
Current in Non-Power
Down Mode
No Operating Current
(Active state: 4 bank)
Test Condition
ICC1
Speed
Units
Operating Current
Symbol
-68
-75A
-260
-360
-10
1 bank operation
tRC = tRC(min), tCK = min
Active-Precharge command
cycling without burst operation
75
75
70
70
ICC2P
CKE ≤ VIL(max), tCK = min,
CS = VIH(min)
1
1
1
ICC2PS
CKE ≤ VIL(max), tCK = Infinity,
CS = VIH(min)
1
1
ICC2N
CKE ≥ VIH(min), tCK = min,
CS = VIH (min)
40
ICC2NS
CKE ≥ VIH(min), tCK = Infinity,
ICC3N
CKE ≤ 0.2V
1, 8
1. Currents given are valid for a single device. The total current for a stacked device depends on the operation being performed on the
other deck.
2. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input
signals are changed up to three times during tRC(min).
3. The specified values are obtained with the output open.
4. Input signals are changed once during tCK(min).
5. Input signals are changed once during three clock cycles.
6. Active Standby Current will be higher if Clock Suspend is entered during a burst read cycle (add 1mA per DQ).
7. Input signals are stable.
8. SP: Standard power; LP: Low power.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 40 of 73
19L3265.E35856B
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
AC Characteristics (TA = 0 to +70°C, VDD = 3.3V ±0.3V)
1. An initial pause of 200µs, with DQM and CKE held high, is required after power-up. A Precharge All
Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after
the Mode Register Set operation.
2. The Transition time is measured between VIH and VIL (or between VIL and VIH)
3. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL
(or between VIL and VIH) in a monotonic manner.
4. Load Circuit A: AC timing tests have VIL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.40V
crossover point
5. Load Circuit A: AC measurements assume tT = 1.0ns.
6. Load Circuit B: AC timing tests have VIL = 0.8 V and VIH = 2.0 V with the timing referenced to the 1.40V
crossover point
7. Load Circuit B: AC measurements assume tT = 1.2ns.
.
AC Output Diagrams
tT
tCKL
Clock
tSETUP
Vtt = 1.4V
VIH
1.4V
VIL
tCKH
50Ω
Output
Zo = 50Ω
50pF
AC Output Load Circuit (A)
tHOLD
Input
1.4V
Output
Zo = 50Ω
tOH
tAC
50pF
tLZ
AC Output Load Circuit (B)
1.4V
Output
Clock and Clock Enable Parameters
Symbol
Parameter
-68
-75A
-260
Min.
Max.
Min.
Max.
Min.
-360
Max.
Min.
-10
Max.
Min.
Max.
Units Notes
tCK3
Clock Cycle Time, CAS Latency = 3
6.67
1000
7.5
1000
10
1000
10
1000
10
1000
ns
tCK2
Clock Cycle Time, CAS Latency = 2
—
—
—
—
10
1000
15
1000
15
1000
ns
tAC3 (A) Clock Access Time, CAS Latency = 3
—
6
—
—
—
—
—
—
—
7
ns
1
tAC2 (A) Clock Access Time, CAS Latency = 2
—
—
—
—
—
—
—
—
—
8
ns
1
tAC3 (B) Clock Access Time, CAS Latency = 3
—
—
—
5.4
—
6
—
6
—
9
ns
2
tAC2 (B) Clock Access Time, CAS Latency = 2
—
—
—
—
—
6
—
9
—
9
ns
2
tCKH
Clock High Pulse Width
3
—
2.5
—
3
—
3
—
3
—
ns
tCKL
Clock Low Pulse Width
3
—
2.5
—
3
—
3
—
3
—
ns
tCES
Clock Enable Set-up Time
2
—
1.5
—
2
—
2
—
3
—
ns
tCEH
Clock Enable Hold Time
1
—
0.8
—
1
—
1
—
1
—
ns
tSB
Power down mode Entry Time
0
6.67
0
7.5
0
10
0
10
0
10
ns
tT
Transition Time (Rise and Fall)
0.5
10
0.5
10
0.5
10
0.5
10
0.5
10
ns
1. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 4, 5 and load circuit A.
2. Access time is measured at 1.4V. See AC Characteristics: notes 1, 2, 3, 6, 7 and load circuit B.
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 41 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Common Parameters
-68
Symbol
-75A
-260
-360
-10
Parameter
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tCS
Command Setup Time
2
—
1.5
—
2
—
2
—
3
—
ns
tCH
Command Hold Time
1
—
0.8
—
1
—
1
—
1
—
ns
tAS
Address and Bank Select Set-up
Time
2
—
1.5
—
2
—
2
—
3
—
ns
tAH
Address and Bank Select Hold Time
1
—
0.8
—
1
—
1
—
1
—
ns
tRCD
RAS to CAS Delay
20
—
20
—
20
—
20
—
30
—
ns
1
tRC
Bank Cycle Time
66.7
—
67.5
—
70
—
70
—
90
—
ns
1
tRAS
Active Command Period
46.7
100K
45
100K
50
100K
50
100K
60
100K
ns
1
tRP
Precharge Time
20
—
20
—
20
—
20
—
30
—
ns
1
1
tRRD
Bank to Bank Delay Time
13.3
—
15
—
20
—
20
—
20
—
ns
tCCD
CAS to CAS Delay Time
1
—
1
—
1
—
1
—
1
—
CLK
1. These parameters account for the number of clock cycle and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
Mode Register Set Cycle
-68
Symbol
tRSC
-75A
-260
-360
-10
Parameter
Mode Register Set Cycle Time
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
2
—
2
—
2
—
2
—
2
—
CLK
1
1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows:
the number of clock cycles = specified value of timing / clock period (count fractions as a whole number).
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 42 of 73
19L3265.E35856B
01/00
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Read Cycle
-68
Symbol
-75A
-260
-360
-10
Parameter
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
2.5
—
—
—
2.5
—
2.5
—
3
—
ns
1
—
—
2.7
—
3
—
3
—
3
—
ns
2, 4
tOH
Data Out Hold Time
tLZ
Data Out to Low Impedance Time
0
—
0
—
0
—
0
—
0
—
ns
tHZ3
Data Out to High Impedance Time
3
6
3
5.4
3
6
3
6
3
7
ns
3
tHZ2
Data Out to High Impedance Time
3
6
—
—
3
6
3
8
3
8
ns
3
tDQZ
DQM Data Out Disable Latency
2
—
2
—
2
—
2
—
2
—
CLK
1.
2.
3.
4.
AC Output Load Circuit A.
AC Output Load Circuit B.
Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Data Out Hold Time with no load must meet 1.8ns (-75A).
Refresh Cycle
-68
Symbol
tREF
tSREX
-75A
-260
-360
-10
Parameter
Units Notes
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Refresh Period
—
64
—
64
—
64
—
64
—
64
Self Refresh Exit Time
10
10
10
10
ms
10
1
ns
1. 4096 auto refresh cycles.
Write Cycle
-68
Symbol
-75A
-260
-360
-10
Parameter
Units
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
tDS
Data In Set-up Time
2
—
1.5
—
2
—
2
—
3
—
ns
tDH
Data In Hold Time
1
—
0.8
—
1
—
1
—
1
—
ns
tDPL
Data input to Precharge
13.3
—
15
—
15
—
15
—
15
—
ns
tDAL3
Data In to Active Delay
CAS Latency = 3
5
—
5
—
5
—
5
—
4
—
CLK
tDAL2
Data In to Active Delay
CAS Latency = 2
—
—
—
—
4
—
3
—
3
—
CLK
tDQW
DQM Write Mask Latency
0
—
0
—
0
—
0
—
0
—
CLK
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Page 43 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Clock Frequency and Latency
Symbol
Parameter
-68
-75A
-260
-360
-10
Units
fCK
Clock Frequency
150
133
100
100
100
66
100
66
MHz
tCK
Clock Cycle Time
6.67
7.5
10
10
10
15
10
15
ns
tAA
CAS Latency
3
3
3
2
3
2
3
2
CLK
tRP
Precharge Time
3
3
2
2
2
2
3
2
CLK
tRCD
RAS to CAS Delay
3
3
2
2
2
2
3
2
CLK
tRC
Bank Cycle Time
10
9
7
7
7
6
9
6
CLK
tRAS
Minimum Bank Active Time
7
6
5
5
5
4
6
4
CLK
tDPL
Data In to Precharge
2
2
2
2
2
1
2
1
CLK
tDAL
Data In to Active/Refresh
5
5
5
4
5
3
4
3
CLK
tRRD
Bank to Bank Delay Time
2
2
2
2
2
2
2
2
CLK
tCCD
CAS to CAS Delay Time
1
1
1
1
1
1
1
1
CLK
tWL
Write Latency
0
0
0
0
0
0
0
0
CLK
tDQW
DQM Write Mask Latency
0
0
0
0
0
0
0
0
CLK
tDQZ
DQM Data Disable Latency
2
2
2
2
2
2
2
2
CLK
tCSL
Clock Suspend Latency
1
1
1
1
1
1
1
1
CLK
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Page 44 of 73
19L3265.E35856B
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IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Timing Diagrams
Page
AC Parameters for Write Timing............................................................................................................... 46
AC Parameters for Read Timing (3/3/3), BL=4......................................................................................... 47
AC Parameters for Read Timing (2/2/2), BL=2......................................................................................... 48
AC Parameters for Read Timing (3/2/2), BL=2......................................................................................... 49
AC Parameters for Read Timing (3/3/3), BL=2......................................................................................... 50
Mode Register Set.................................................................................................................................... 51
Power on Sequence and Auto Refresh (CBR) ......................................................................................... 52
Clock Suspension / DQM During Burst Read .......................................................................................... 53
Clock Suspension / DQM During Burst Write .......................................................................................... 54
Power Down Mode and Clock Suspend ................................................................................................... 55
Auto Refresh (CBR).................................................................................................................................. 56
Self Refresh (Entry and Exit) .................................................................................................................... 57
Random Row Read (Interleaving Banks) with Precharge, BL=8.............................................................. 58
Random Row Read (Interleaving Banks) with Auto-precharge, BL=8...................................................... 59
Random Row Write (Interleaving Banks) with Auto-Precharge, BL=8 ..................................................... 60
Random Row Write (Interleaving Banks) with Precharge, BL=8 .............................................................. 61
Read/Write Cycle
................................................................................................................................ 62
Interleaved Column Read Cycle............................................................................................................... 63
Auto Precharge after a Read Burst, BL=4 ................................................................................................ 64
Auto Precharge after a Write Burst, BL=4 ................................................................................................ 65
Burst Read and Single Write Operation ................................................................................................... 66
Full Page Burst Read and Single Write Operation ................................................................................... 67
CS Function (Only CS signal needs to be asserted at minimum rate) ..................................................... 68
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 45 of 73
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCKH
CKE
tCK2
tCKL
tCS
tCES
tCEH
tCH
CS
RAS
CAS
WE
* BS1
tAH
A10
RAx
RBx
RAy
RAz
RBy
RAz
RBy
tAS
A0-A9,A11
RAx
CAx
RBx
CBx
RAy
CAy
DQM
tRCD
tDAL‡
DQ
tDPL‡
tDS
tRC
tDH
tRP
tRRD
Hi-Z
19L3265.E35856B
01/00
*BS0 = ”L”
Bank2,3 = Idle
Ax0
Ax1
Ax2
Ax3
Bx0
Bx1
Activate
Write with
Activate
Write with
Command Auto Precharge Command Auto Precharge
Bank 0
Command
Bank 1
Command
Bank 0
Bank 1
Bx2
Bx3
Ay0
Activate
Command
Bank 0
Write
Command
Bank 0
Ay1
Ay2
Ay3
‡ tDPL and tDAL depend on clock cycle time and
speed sort. See the Clock Frequency and
Latency Table.
Precharge
Command
Bank 0
Activate
Command
Bank 0
Activate
Command
Bank 1
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
AC Parameters for Write Timing
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 46 of 73
(Burst length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
T13
CLK
tCK3
Begin Auto
Precharge
Bank 0
CKE
Begin Auto
Precharge
Bank 1
CS
RAS
CAS
AC Parameters for Read Timing (3/3/3)
\
19L3265.E35856B
01/00
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
WE
* BS1
RAx
A0-A9,A11
RBx
RAx
CAx
tRRD
DQM
RAy
CBx
RBx
tRAS
RAy
tRP
tRC
tAC3
tOH
tRCD
DQ
Hi-Z
* BS0 = ”L”
Bank2,3 = Idle
Ax0
Activate
Command
Bank 0
Read with
Auto Precharge
Command
Bank 0
Activate
Command
Bank 1
Ax1
Ax2
Read with
Auto Precharge
Command
Bank 1
Ax3
Bx0
Activate
Command
Bank 0
Bx1
Bx2
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 47 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
CLK
tCK2
tCKH tCKL
CKE
tCS
tCES
Begin Auto
Precharge
Bank 0
tCH
Begin Auto
Precharge
Bank 1
tCEH
CS
RAS
CAS
WE
* BS1
tAH
A10
RBx
RAx
RAy
tAS
A0-A9,A11
RBx
CAx
RAx
tRRD
tRAS(min)
DQM
Note: Must satisfy tRAS(min)
For -260: extend tRCD1 clock
19L3265.E35856B
01/00
DQ
tRCD
* BS0 = ”L”
Bank2,3 = Idle
tOH
Ax0
Activate
Command
Bank 0
Read with
Auto Precharge
Command
Bank 0
tRP
tHZ
tLZ
Hi-Z
RAy
tRP
tRC
tAC2
CBx
Activate
Command
Bank 1
Ax1
Read with
Auto Precharge
Command
Bank 1
tHZ
Bx0
Bx1
Activate
Command
Bank 0
T13
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
AC Parameters for Read Timing (2/2/2)
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 48 of 73
(Burst length = 2, CAS latency = 2; tRCD, tRP = 2)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
CLK
tCK3
tCKH tCKL
CKE
tCS
tCES
Begin Auto
Precharge
Bank 0
tCH
Begin Auto
Precharge
Bank 1
tCEH
CS
RAS
CAS
T13
AC Parameters for Read Timing (3/2/2)
\
19L3265.E35856B
01/00
(Burst length = 2, CAS latency = 3; tRCD, tRP = 2)
WE
* BS1
A10
RAx
RBx
RAy
tAS
A0-A9,A11
RAx
CAx
tRRD
DQM
Note: Must satisfy tRAS(min).
Extended tRCD 1 clock.
Not required for BL ≥ 4.
DQ
tRAS
RBx
CBx
tAC3
Bank2,3=Idle
tOH
tHZ
tLZ
Hi-Z
* BS0=” L”
tRP
tRC
tRCD
Ax0
Activate
Command
Bank 0
Read with
Activate
Auto Precharge Command
Command
Bank 1
Bank 0
RAy
Ax1
Read with
Auto Precharge
Command
Bank 1
tRP
tHZ
Bx0
Bx1
Activate
Command
Bank 0
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 49 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
tAH
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
T13
T14
CLK
tCK3
Begin Auto
Precharge
Bank 0
CKE
Begin Auto
Precharge
Bank 1
tCEH
CS
RAS
CAS
WE
* BS1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RAy
RBx
CBx
tRRD
tRAS (mIn)
DQM
RAy
tRP
tRC
tAC3
tOH
tRP
tRCD
DQ
Hi-Z
Ax0
19L3265.E35856B
01/00
Bank 2,3=Idle
*BS0=” L”
Activate
Command
Bank 0
Note: Must satisfy
Read with
tRAS(min).
Auto Precharge
Extended tRCD not required
Command
for BL≥4.
Bank 0
Activate
Command
Bank 1
Bx0
Ax1
Read with
Auto Precharge
Command
Bank 1
Activate
Command
Bank 0
Bx1
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
AC Parameters for Read Timing (3/3/3)
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 50 of 73
(Burst length = 2, CAS latency = 3; tRCD, tRP = 3)
tCK2
BS0,BS1
A0-A9,
A11
DQM
tRP
DQ
Hi-Z
Precharge
Command
All Banks
Mode Register
Set Command
Any
Command
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Address Key
Page 51 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
Mode Register Set
\
CLK
T22
T21
T20
T19
T18
T17
T16
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
19L3265.E35856B
01/00
(CAS latency = 2)
CKE
tRSC
CS
RAS
CAS
WE
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CLK
tCK
High level
is required
CKE
2 Clock min.
Minimum of 8 Refresh Cycles are required
CS
RAS
CAS
WE
BS
A10
Address Key
A0-A9,
A11
DQM
DQ
tRP
Hi-Z
19L3265.E35856B
01/00
Precharge 1st Auto Refresh
Command
Command
All Banks
Inputs must be
stable for 200µs
tRC
8th Auto Refresh
Command
Mode Register
Set Command
Any
Command
T20
T21
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T1
Power-On Sequence and Auto Refresh (CBR)
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 52 of 73
T0
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCES
tCK3
tCEH
CKE
CS
RAS
CAS
WE
T22
Clock Suspension / DQM During Burst Read
\
19L3265.E35856B
01/00
(Burst length = 8, CAS latency = 3; tRCD = 3)
* BS1
RAx
A0-A9,
A11
RAx
CAx
DQM
tHZ
DQ
Hi-Z
* BS0=” L”
Bank2,3=Idle
Ax0
Activate
Command
Bank 0
Read
Command
Bank 0
Ax1
Ax2
Ax3
Clock Suspend
1 Cycle
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
Ax4
Ax6
Ax7
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 53 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CLK
tCK3
CKE
CS
RAS
CAS
WE
* BS1
A10
RAx
A0-A9,
A11
RAx
CAx
DQM
DQ
Hi-Z
19L3265.E35856B
01/00
* BS0=” L”
Bank2,3=Idle
DAx0
Activate
Command
Bank 0
DAx1
Clock Suspend
1 Cycle
Write
Command
Bank 0
DAx3
DAx2
Clock Suspend
2 Cycles
Clock Suspend
3 Cycles
DAx5
DAx6
DAx7
T20
T21
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Clock Suspension / DQM During Burst Write
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 54 of 73
(Burst length = 8, CAS latency = 3; tRCD = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCES
tCK2
tCES
tCES
tSB
CKE
VALID
CS
RAS
CAS
WE
Power Down Mode and Clock Suspend
\
19L3265.E35856B
01/00
(Burst length = 4, CAS latency = 2)
* BS1
RAx
A0 -A9,
A11
RAx
CAx
DQM
DQ
* BS0=” L”
Bank2,3=Idle
tHZ
tSB
Hi-Z
Ax0
Activate
Command
Bank 0
Clock Suspension
Start
ACTIVE
STANDBY
NOP
Ax1
Read
Command
Bank 0
Ax2
Clock Suspension
End
Ax3
Precharge
Command
Bank 0
PRECHARGE
STANDBY
NOP
Any
Command
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 55 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
CS
RAS
CAS
Page 56 of 73
WE
BS
A10
A0-A9,
A11
Hi-Z
Auto Refresh
Command
Auto Refresh
Command
Precharge
Command
All Banks
19L3265.E35856B
01/00
DQ
tRC
tRC
tRP
DQM
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
tCK2
CKE
Auto Refresh (CBR)
\
CLK
T22
T21
T20
T19
T18
T17
T16
T15
T14
T13
T12
T11
T10
T9
T8
T7
T6
T5
T4
T3
T2
T1
T0
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
(CAS latency = 2)
T0
T1
T2
T3
T4
Tm
Tm+1 Tm+2 Tm+3 Tm+4 Tm+5 Tm+6 Tm+7 Tm+8 Tm+9 Tm+10 Tm+11 Tm+12 Tm+13 Tm+14 Tm+15
CLK
tCES
tCES
CKE
CS
RAS
Self Refresh (Entry and Exit)
\
19L3265.E35856B
01/00
(Note: The CLK signal must be reestablished prior to CKE returning high.)
CAS
WE
BS
A0-A9,
A11
DQM
DQ
Hi-Z
tSB
All Banks
must be idle
Self Refresh
Entry
Power Down
Entry
tSREX
Self Refresh
Exit
Power Down
Exit
tRC
Any Command
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 57 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
CLK
tCK3
CKE
High
CS
RAS
CAS
WE
* BS1
A10
RBx
A0-A9,
A11
RBx
RBy
RAx
CBx
CAx
CBy
RBy
tAC3
tRCD
DQM
DQ
RAx
Hi-Z
Bx0
19L3265.E35856B
01/00
Activate
Command
Bank 1
* BS0=” L”
Bank2,3=Idle
Read
Command
Bank 1
Bx1
Activate
Command
Bank 0
Bx2
Bx3
Bx4
Read
Command
Bank 0
Bx5
Bx6
Precharge
Command
Bank 1
Ax0
Ax1
Ax4
Activate
Command
Bank 1
Ax5
Read
Command
Bank 1
Ax6
Ax7
By0
Precharge
Command
Bank 0
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Random Row Read (Interleaving Banks) with Precharge
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 58 of 73
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
Start Auto Precharge
Bank 1
Start Auto Precharge
Bank 0
CS
RAS
CAS
WE
* BS1
A0-A9,A11
tRCD
RBy
RAx
RAx
CBx
RBx
DQM
DQ
RAx
RAx
RBx
CAx
CBy
RBy
tAC3
Hi-Z
Bx0
Activate
Command
Bank 1
* BS0=” L”
Bank2,3=Idle
Read with
Auto Precharge
Command
Bank 1
Bx1
Bx2
Activate
Command
Bank 0
Bx3
Bx4
Bx5
Bx6
Read with
Auto Precharge
Command
Bank 0
Bx7
Ax0
Ax4
Ax1
Activate
Command
Bank 1
Ax5
Ax6
Read with
Auto Precharge
Command
Bank 1
Ax7
By0
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 59 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
Random Row Read (Interleaving Banks) with Auto-Precharge
\
19L3265.E35856B
01/00
(Burst length = 8,CAS latency = 3; tRCD, tRP = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T12
T11
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
CS
RAS
CAS
WE
* BS1
A10
RAx
A0-A9,A11
CAX
RAx
RBx
CAy
RAy
CBx
tDAL‡
tRCD
DQM
DQ
RAy
RBx
tDAL‡
Hi-Z
DAx0
19L3265.E35856B
01/00
Activate
Command
Bank 0
* BS0=” L”
Bank2,3=Idle
DAx1
Write with
Auto Precharge
Command
Bank 0
DAx4
DAx5
DAx6
Activate
Command
Bank 1
DAx7
DBx0
DBx1
Write with
Auto Precharge
Command
Bank 1
‡
DBx2
DBx3
DBx4
DBx5
DBx6
Activate
Command
Bank 0
DBx7
DAy0
Write with
Auto Precharge
Command
Bank 0
Number of clocks depends on clock cycle time and speed sort.
See the Clock Frequency and Latency table.
Bank may be reactivated at the completion of tDAL.
DAy1
DAy2
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Random Row Write (Interleaving Banks) with Auto-Precharge
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 60 of 73
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
CS
RAS
CAS
WE
A10
RAx
A0-A9,
A11
RAx
CAX
RBx
CAy
RAy
CBx
tRCD
DQM
DQ
RAy
RBx
tDPL
tRP
Hi-Z
Activate
Command
* BS0=” L” Bank 0
Bank2,3=Idle
DAx0
DAx1
Write
Command
Bank 0
DAx4
DAx5
DAx6
Activate
Command
Bank 1
DAx7
DBx0
DBx1
Write
Command
Bank 1
DBx2
DBx3
Precharge
Command
Bank 0
DBx4
DBx5
Activate
Command
Bank 0
DBx6
DBx7
DAy0
DAy1
DAy2
Write
Command
Bank 0
Precharge
Command
Bank 1
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 61 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
* BS1
Random Row Write (Interleaving Banks) with Precharge
\
19L3265.E35856B
01/00
(Burst length = 8,CAS latency = 3; tRCD, tRP = 3)
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
CLK
tCK3
CKE
CS
RAS
CAS
WE
* BS1
A10
RAx
A0-A9,
A11
RAx
CAy
CAx
DQM
DQ
Hi-Z
19L3265.E35856B
01/00
* BS0=” L”
Bank2,3=Idle
Ax0
Activate
Command
Bank0
Read
Command
Bank 0
Ax1
Ax2
Ax3
DAy0
DAy1
DAy3
The Read Data
Write
The Write Data
is Masked with a Command is Masked with a
Two Clock
Bank 0
Zero Clock
Latency
Latency
DAy4
Precharge
Command
Bank 0
T19
T20
T21
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Read / Write Cycle
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 62 of 73
(Burst length = 8, CAS latency = 3; tRCD, tRP = 3)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T17
T16
T18
T19
T20
CLK
tCK3
CKE
Start Auto Precharge
Bank 0
CS
RAS
T21
T22
Interleaved Column Read Cycle
\
19L3265.E35856B
01/00
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
CAS
WE
* BS1
RAx
A0-A9,
A11
RAx
CAx
Bank2,3=Idle
Ax0
Activate
Command
Bank 0
CBy
CBz
CAy
tAC3
Hi-Z
* BS0=” L”
CBx
RBx
tRCD
DQM
DQ
RBx
Read
Command
Bank 0
Activate
Command
Bank 1
Ax1
Read
Command
Bank 1
Ax2
Ax3
Read
Command
Bank 1
Bx0
Bx1
By0
By1
Bz0
Bz1
Read with
Read
Precharge
Command Auto Precharge Command
Command
Bank 1
Bank 1
Bank 0
Ay0
Ay1
Ay2
Ay3
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 63 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T12
T11
T13
T14
T15
T17
T16
T18
T19
T20
T21
CLK
tCK3
CKE
High
CS
RAS
CAS
WE
* BS1
A10
RAx
A0-A9,
A11
RAx
RBx
CAx
RBy
RBx
CBx
CAy
Start Auto Precharge
Bank 1
DQM
DQ
RBy
CBy
Start Auto Precharge
Bank 0
Start
Auto Precharge
Bank 1
Hi-Z
19L3265.E35856B
01/00
Activate
Command
* BS0=” L”
Bank 0
Bank2,3=Idle
Ax0
Activate
Command
Bank 1
Read
Command
Bank 0
Ax1
Ax2
Read with
Auto Precharge
Command
Bank 1
Ax3
Bx0
Bx1
Bx2
Read with
Auto Precharge
Command
Bank 0
Bx3
Ay0
Activate
Command
Bank 1
Ay1
Ay2
Ay3
Read with
Auto Precharge
Command
Bank 1
By0
By1
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Auto Precharge after Read Burst
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 64 of 73
(Burst length = 4, CAS latency = 3; tRCD, tRP = 3)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
High
CS
RAS
Auto Precharge after Write Burst
\
19L3265.E35856B
01/00
(Burst length = 4, CAS latency = 2)
CAS
WE
* BS1
RBx
RAx
A0-A9,
A11
RAx
RBy
CBx
RBx
CAx
CAy
RBy
CBy
tDAL‡
DQM
DQ
RAz
CAz
RAz
tDAL‡
tDAL‡
Hi-Z
DAx0
Activate
Command
Bank 0
* BS0=” L”
Bank2,3=Idle
DAx1
Write
Command
Bank 0
DAx2
DAx3
DBx0
DBx1
Write with
Activate
Command Auto Precharge
Command
Bank 1
Bank 1
DBx2
DBx3
DAy0
DAy1
DAy2
DAy3
DBy0
DBy1
DBy2
DBy3
DAz0
DAz1
Write with
Write with
Write with
Activate
Activate
Auto Precharge Command Auto Precharge Command Auto Precharge
Command
Command
Command
Bank 1
Bank 0
Bank 0
Bank 0
Bank 1
‡ Number of clocks depends on clock cycle and speed sort.
See the Clock Frequency and Latency table.
Bank may be reactivated at the completion of tDAL.
DAz2
DAz3
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 65 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK2
CKE
High
CS
RAS
CAS
WE
* BS1
A10
RAv
A0-A9,A11
RAv
CAv
CAw
CAx
CAy
CAz
LDQM
UDQM
DQ0 - DQ7
19L3265.E35856B
01/00
DQ8 - DQ15
Hi-Z
Hi-Z
* BS0=” L”
Bank2,3=Idle
Activate
Command
Bank 0
Read
Command
Bank 0
Av0
Av1
Av2
Av3
DAw0
Av0
Av1
Av2
Av3
DAw0
Single Write
Command
Bank 0
Ay0
DAx0
Single Write
Command
Bank 0
Ay1
Ay0
Lower Byte
Read
is masked
Command
Upper Byte
Bank 0
is masked
Ay2
Ay3
DAz0
Ay3
DAz0
Single Write
Command
Bank 0
Lower Byte
is masked
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
Burst Read and Single Write Operation
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 66 of 73
(Burst length = 4, CAS latency = 2)
T0
T1
T2
T3
T4
T5
T7
T6
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
T21
T22
CLK
tCK3
CKE
High
CS
RAS
CAS
WE
* BS1
RAv
A0-A9,
A11
RAv
CAv
CAw
CAx
CAy
LDQM
UDQM
DQ0-DQ7
DQ8-DQ15
Hi-Z
Av0
Av1
Av2
Av3
DAw0
DAx0
Ay0
Ay1
Ay2
Ay3
Av0
Av1
Av2
Av3
DAw0
DAx0
Ay0
Ay1
Ay2
Ay3
Hi-Z
*BS0=” L”
Bank2,3=Idle
Activate
Command
Bank 0
Read
Command
Bank 0
Burst Stop
Command
Single Write
Command
Bank 0
Single Write
Command
Bank 0
Read
Command
Bank 0
Burst Stop
Command
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Page 67 of 73
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
A10
Full Page Burst Read and Single Write Operation
\
19L3265.E35856B
01/00
(Burst length = Full page, CAS latency = t3;
RCD, tRP = 3)
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
CLK
tCK3
CKE
CS
RAS
CAS
WE
A11(BS)
A10
RAx
A0 - A9
RAx
DQM
CAx
CAy
Low
tDPL
tRCD
19L3265.E35856B
01/00
DQ
Hi-Z
Ax0
Activate
Command
Bank A
Read
Command
Bank A
Ax1
Ax2
Ax3
DAy0
DAy1
Write
Command
Bank A
DAy2
DAy3
Precharge
Command
Bank A
T19
T20
T21
T22
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
T0
CS Function (Only CS signal needs to be asserted at minimum rate)
\
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 68 of 73
(at 100MHz Burst Length = 4,CAS Latency = 3, tRCD, tRP = 3)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Package Dimensions
(400mil; 54 lead; Thin Small Outline Package)
22.22 ± 0.13
Detail A
10.16
± 0.13
11.76
± 0.20
Lead #1
Seating Plane
0.10
0.80 Basic
0.35
+ 0.10
- 0.05
0.805REF
1.20 Max
Detail A
0.25 Basic
Gage Plane
0.5 ± 0.1
0.05 Min
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 69 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Package Dimensions
(400mil; 54 lead; 2 High Stack; Thin Small Outline J Lead Package)
22.22 ± 0.28
3.20 Max
0.75 Min
10.15
± 0.05
9.90
± 0.40
11.4
± 0.25
Lead #1
0.10
0.80 Basic
+ 0.10
0.30
- 0.04
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 70 of 73
+ 0.13
0.50
- 0.04
Seating Plane
19L3265.E35856B
01/00
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Revision Log
Revision
11/21/97
4/17/98
Contents of Modification
Initial release.
page 1
Change PN designations: -322 -> -360, -222 -> -260. Also, page 5, page 21-page 25, page 27,
page 40-page 43.
page 1
Add 2 high stack (x4). Also, page 3-page 5, page 7, page 11, page 29, page 33, page 38-page 40,
page 70.
page 30
Clarify Power Down Mode.
page 40
Add low power current specification. Also, page 1.
Modify sorts/timing information: 1) separate -80 sort added and/or
page 41-page 2) 322 (360) and 222 (260) sorts modified (t
CK3, tSB, tRAS, tRRD, tRSC, tDPL3 (tCK3 changed from 8ns to
43
10ns); tHZ). Also, page 1, page 5, page 12, page 40.
page 1
Add -68; changed CL = 3 timings (-260, -360) and CL = 2 timings (-260) to encompass JEDEC 125
MHz requirements. Also, page 5, page 41-page 43.
page 24
Add note for -68 tDPL (2 clocks) / update wording. Also, page 28, page 61.
page 40
Update currents based on timing changes.
page 44
Add -68; update -260, -360 (125MHz), remove -10 CL = 1.
page 47
Correct CKE. Also, page 51, page 53.
page 50
Add note: tRAS(min).
5/14/98
page 38
Include minimum capacitance specification, update maximum for CLK.
5/29/98
page 21
Clarify Read with auto-precharge description.
page 1
Change -260, -360 timings.
page 5
Remove x4, -68. Add x8, x16, -260, LP. Change clock cycle for -260, -360.
pages 22 to
25, and 60
and 65
Update of notes, description, regarding Auto Precharge.
Change in implementation of auto-precharge for Write with Auto-Precharge command and for interruption of Auto Precharge.
page 25
Clarify wording for timing of precharge (Read).
5/1/98
pages 26, 28, t
or tDAL updated.
43, 44, and 46 DPL
12/14/98
page 30
Correct Power Down Mode Exit requirements (NOP required on clock following CKE transition).
Remove note (buffer enable) in diagram.
page 33
Change WE in Self Refresh Exit Command from “X” to “H” (NOP). Also, in Power Down Mode
Entry/Exit. Note edited: NOP or Device Deselect required.
page 34
Correct note regarding CKE low to high transition.
page 40
Update currents to reflect -260, -360 timing changes (scale for tCK(min)).
Drop LP requirements for ICC3P, ICC2P, ICC2PS, ICC5.
page 41
Correct tCKH, tCKL in diagram.
Remove note 4 (tCKH, tCKL measurement). Update -260, -360 timings. Also page 42-page 44. Revise
method of specifying tRSC (clk versus ns).
page 43
Clarify tOH / load conditions across speed sorts.
page 49
Correct Read (322) timing: Auto-precharge start, extend tRCD.
page 50
Clarify note about tRAS(min).
page 59
Correct timing (last activate/read commands).
page 1
Change timings, delete -68, add -75A.
page 5
Remove -68, add -75A, change clock cycle for -260, -360.
page 38
Update Capacitance Table (max values), add typical values.
page 40
Update currents to reflect -260, -360 timing changes, added sort.
page 41
Update sorts, timings. Also, page 42 - page 44.
3/21/99
page 42
Change tRP, tRCD for -75A (22.5 to 20ns)
4/22/99
page 40
Update ICC2NS (5 to 6mA)
5/14/99
page 51
Corrected addessing in timing diagram - Mode Register Set.
2/3/99
19L3265.E35856B
01/00
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 71 of 73
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision C
Revision Log
Revision
7/2/99
Contents of Modification
page 1,page
5,
page 39-47
10/20/99
01/00
Add x16, -68
Removed Preliminary.
page 5
Updated Ordering infomration.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 72 of 73
19L3265.E35856B
01/00

Copyright and Disclaimer
 Copyright International Business Machines Corporation 1999, 2000
All Rights Reserved
Printed in the United States of America August 2000
The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both.
IBM
IBM Logo
Other company, product and service names may be trademarks or service marks of others.
All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury
or death to persons. The information contained in this document does not affect or change IBM product specifications
or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary.
THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM
be liable for damages arising directly or indirectly from any use of the information contained in this document.
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Hopewell Junction,
NY 12533-6351
The IBM home page can be found at
http://www.ibm.com
The IBM Microelectronics Division home page
can be found at http://www.chips.ibm.com
19L3265.E35856B.EOL7_00.
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