. IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 32Mx72 Synchronous DRAM DIMM • Performance: -260 CL=2 -360 CL=3 -360 CL=2 Units Reg. Buff. Reg. Buff Reg. Buff. 3 2 4 3 3 2 DIMM CAS Latency fCK Clock Frequency 100 100 100 100 66 66 MHz fCK Clock Cycle 10 10 10 10 15 15 ns tAC Clock Access 7.2 7.2 7.2 7.2 10.2 10.2 ns • Intended for 66/100MHz and PC100 applications • Inputs and outputs are LVTTL (3.3V) compatible • Single 3.3V ± 0.3V Power Supply • Single Pulsed RAS interface • SDRAMs have four internal banks • Module has one physical bank • Fully Synchronous to positive Clock Edge • Programmable Operation: - DIMM CAS Latency: 3, 4 (Registered mode); 2, 3 (Buffered mode) - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8 - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Data Mask for Byte Read/Write control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 12/11/2 Addressing (Row/Column/Bank) • 4096 refresh cycles distributed across 64ms • Card size: 5.25" x 0.157" x 1.70" • Gold contacts • SDRAMs in TSOP • Serial Presence Detect with Write protect Description IBM13M32734CCA is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 32Mx72 high-speed memory array. The DIMM uses eighteen 32Mx4 SDRAMs in 400 mil TSOP packages. The DIMM achieves highspeed data-transfer rates of up to 100 MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system clock. The DIMM is intended for use in applications operating from 66MHz to 100 MHz, PC100, memory bus speeds, and/or heavily loaded bus applications. All control and address signals are re-driven through registers/buffers to the SDRAM devices. The DIMM can be operated in either registered mode (REGE pin tied high), where the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock), or in buffered mode (REGE pin tied low) where the input signals pass through the register/buffer to the SDRAM devices on the same clock. XTK simulation models of the DIMM are available to determine which mode to design for. A phase-lock loop (PLL) on the DIMM is used to redrive the clock signals to both the SDRAM devices and the registers to minimize system clock loading. 09K3541.F38352 10/99 (CK0 is connected to the PLL, and CK1, CK2, and CK3 are terminated on the DIMM.) A single clock enable (CKE0) controls all devices on the DIMM, enabling the use of SDRAM power-down modes. Prior to any access operation, the device CAS latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A9 and A11 using the mode register set cycle. The DIMM CAS latency when operated in buffered mode is the same as the device CAS latency as specified in the SPD EEPROM. The DIMM CAS latency when operated in registered mode is one clock later due to the address and control signals being clocked to the SDRAM devices. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and may be write protected by providing a high level to pin 81 on the DIMM. An on-board pulldown resistor keeps this in the write-enable mode. All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Card Outline (Front) (Back) 1 85 10 11 94 95 40 124 84 168 41 125 Pin Description CK0-CK3 Clock Inputs CKE0 Clock Enable RAS Row Address Strobe CAS Column Address Strobe VDD Power (3.3V) WE Write Enable VSS Ground S0, S2 Chip Selects NC No Connect Address Inputs SCL Serial Presence Detect Clock Input Serial Presence Detect Data Input/Output A0-A9, A11 DQ0 - DQ63 CB0 - CB7 DQMB0 - DQMB7 Data Input/Output Check Bit Data Input/Output Data Mask A10/AP Address Input/Autoprecharge SDA BA0, BA1, (A13,A12) SDRAM Bank Address Inputs SA0-2 Serial Presence Detect Address Inputs SPD Write Protect REGE Register Enable WP ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 VSS 85 VSS 22 CB1 106 CB5 43 VSS 127 VSS 64 VSS 148 VSS 2 DQ0 86 DQ32 23 VSS 107 VSS 44 NC 128 CKE0 65 DQ21 149 DQ53 3 DQ1 87 DQ33 24 NC 108 NC 45 S2 129 NC 66 DQ22 150 DQ54 4 DQ2 88 DQ34 25 NC 109 NC 46 DQMB2 130 DQMB6 67 DQ23 151 DQ55 110 VDD 47 DQMB7 68 VSS 152 VSS 111 CAS 5 DQ3 89 DQ35 26 VDD 6 VDD 90 VDD 27 WE DQMB3 131 48 NC 132 NC 69 DQ24 153 DQ56 7 DQ4 91 DQ36 28 DQMB0 112 DQMB4 49 VDD 133 VDD 70 DQ25 154 DQ57 8 DQ5 92 DQ37 29 DQMB1 113 DQMB5 50 NC 134 NC 71 DQ26 155 DQ58 9 DQ6 93 DQ38 30 S0 114 NC 51 NC 135 NC 72 DQ27 156 DQ59 157 VDD 10 DQ7 94 DQ39 31 NC 115 RAS 52 CB2 136 CB6 73 VDD 11 DQ8 95 DQ40 32 VSS 116 VSS 53 CB3 137 CB7 74 DQ28 158 DQ60 12 VSS 96 VSS 33 A0 117 A1 54 VSS 138 VSS 75 DQ29 159 DQ61 13 DQ9 97 DQ41 34 A2 118 A3 55 DQ16 139 DQ48 76 DQ30 160 DQ62 14 DQ10 98 DQ42 35 A4 119 A5 56 DQ17 140 DQ49 77 DQ31 161 DQ63 162 VSS 15 DQ11 99 DQ43 36 A6 120 A7 57 DQ18 141 DQ50 78 VSS 16 DQ12 100 DQ44 37 A8 121 A9 58 DQ19 142 DQ51 79 CK2 163 CK3 17 DQ13 101 DQ45 38 A10/AP 122 BA0 59 VDD 143 VDD 80 NC 164 NC 18 VDD 102 VDD 39 BA1 123 A11 60 DQ20 144 DQ52 81 WP 165 SA0 DQ46 40 VDD 124 VDD 61 NC 145 NC 82 SDA 166 SA1 VDD 125 CK1 62 NC 146 NC 83 SCL 167 SA2 CK0 126 NC 63 NC 147 REGE 84 VDD 168 VDD 19 DQ14 103 20 DQ15 104 DQ47 41 21 CB0 105 CB4 42 Note: All pin assignments are consistent with all 8-byte unbuffered versions. Ordering Information Part Number Organization IBM13M32734CCA-260T 32Mx72 Device Device Clock Cycle Leads CAS Latency Access Time 3, 2 6.0ns 3 6.0ns 2 9.0ns Dimension Power Note 10ns IBM13M32734CCA-360T Gold 5.25" x 0.157" x 1.70" 3.3V 1 32Mx72 15ns 1. PC100 applications 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module x72 ECC SDRAM DIMM Block Diagram RS0 RDQMB0 # (1 Bank, x4 SDRAMs) RDQMB4 CS DQ0 DQ1 DQ2 DQ3 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS DQ4 DQ5 DQ6 DQ7 D0 D1 RDQMB1 DQ32 DQ33 DQ34 DQ35 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ36 DQ37 DQ38 DQ39 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D9 CS D10 RDQMB5 DQ8 DQ9 DQ10 DQ11 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ12 DQ13 DQ14 DQ15 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS CB0 CB1 CB2 CB3 CS DQ16 DQ17 DQ18 DQ19 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ20 DQ21 DQ22 DQ23 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ40 DQ41 DQ42 DQ43 DQM I/O 0 I/O 1 I/O 2 I/O 3 D11 DQ44 DQ45 DQ46 DQ47 DQM I/O 0 I/O 1 I/O 2 I/O 3 D12 CB4 CB5 CB6 CB7 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D2 CS D3 D4 RS2 RDQMB2 CS CS CS D13 RDQMB6 D5 DQ48 DQ49 DQ50 DQ51 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ52 DQ53 DQ54 DQ55 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D6 RDQMB3 CS D14 CS D15 RDQMB7 DQ24 DQ25 DQ26 DQ27 DQM I/O 0 I/O 1 I/O 2 I/O 3 DQ28 DQ29 DQ30 DQ31 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS D7 DQ56 DQ57 DQ58 DQ59 CS D8 DQ60 DQ61 DQ62 DQ63 CS DQM I/O 0 I/O 1 D16 I/O 2 I/O 3 DQM I/O 0 I/O 1 I/O 2 I/O 3 CS Serial Presence Detect SCL WP 47K D17 SDA A0 A1 A2 SA0 SA1 SA2 #Unless otherwise noted, resistor values are 10 Ohms. S0/S2 DQMB0 to DQMB7 BA0-BA1 A0-A11 RAS CAS CKE0 WE 10k VDD REGE PCK R E G I S T E R RS0/RS2 RDQMB0 - RDQMB7 BA0-BA1: SDRAMs D0-D17 RBA0 - RBA1 A0-A11: SDRAMs D0-D17 RA0-RA11 RRAS RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 RCAS CKE: SDRAMs D0 - D17 RCKE0 RWE WE: SDRAMs D0 - D17 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 20 VDD D0 - D8 VSS D0 - D8 Note: DQ wiring may differ from that described in this drawing; however, DQ/DQMB relationships are maintained as shown. PLL CK0 CK1, CK2, CK3 Terminated 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Clock Wiring Clock Net Wiring (CK0): SDRAM 10 Ohms CK0 IN OUT1 TO OUT6 12pF SDRAM SDRAM Phase Lock Loop One of six SDRAM outputs is shown. All PLL clock SDRAM loads are equal-achieved in part through equal-length wiring. OUT7 FDBK OUT10 IN PCK Register 1:1 Register 1:1 (PLL out to Feedback input) 12pF Notes: Terminated Clock Nets (CK1, CK2, CK3): 10 0hms CK1, CK2, and CK3 12pf 09K3541.F38352 10/99 PCK 1. The PLL is programmed via a combination of the feedback path and on-DIMM loading. PLL feedback produces zero phase shift from the delayed CK0 input. 2. Card wiring and capacitance loading variation: ± 100 ps. 3. Timing is based on a driver with a 1 Volt/ns rise time. 4. Feedback Capacitor Valve determined by PLL phase characteristics. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Input/Output Functional Description Symbol Type Signal Polarity CK0 - CK3 Input Pulse Positive Edge CKE0 Input Level Active High S0, S2 Input Pulse Enables the associated SDRAM command decoder when low and disables the command Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0, 1 Input Level A0 - A9, A11 A10/AP Input DQ0 - DQ63, Input CB0 - CB7 Output DQMB0 DQMB7 Input VDD, VSS Supply Function The system clock inputs. All the SDRAM inputs are sampled on the rising edge of their associated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated. Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend mode, or the Self Refresh mode. — Selects which SDRAM bank of four is activated. Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 and A11 defines the column address (CA0-CA9, CA11) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. Level — Data and Check Bit Input/Output pins Pulse Active High The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high-impedance state when sampled high. In Read mode, DQMB has a latency of two clock cycles in Buffered mode or three clock cycles in Registered mode, and controls the output buffers like an output enable. In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by allowing input data to be written if it is low but blocking the write operation if it is high. Power and ground for the module. Active High The Register Enable pin is used to permit the DIMM to operate in “buffered” mode (inputs (Register re-driven asynchronously) or “registered” mode (signals re-driven to SDRAMs when Mode clock rises, and held valid until next rising clock). Enable) REGE Input Level SA0 - 2 Input Level — These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. SDA Input Output Level — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup. SCL Input Pulse — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup. WP Input Level Active High This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD EEPROM. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Serial Presence Detect (Part 1 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type SDRAM 04 3 Number of Row Addresses on Assembly 12 0C 4 Number of Column Addresses on Assembly 11 0B 5 Number of DIMM Banks 1 01 6-7 Data Width of Assembly x72 4800 8 Assembly Voltage Interface Levels LVTTL 01 9 SDRAM Device Cycle Time (CL = 3) 10.0ns A0 10 SDRAM Device Access Time from Clock at CL=3 6.0ns 60 11 Assembly Error Detection/Correction Scheme ECC 02 12 Assembly Refresh Rate/Type SR/1X(15.625us) 80 13 SDRAM Device Width x4 04 14 Error Checking SDRAM Device Width x4 04 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 16 SDRAM Device Attributes: Burst Lengths Supported 17 SDRAM Device Attributes: Number of Device Banks 18 SDRAM Device Attributes: CAS Latency 19 SDRAM Device Attributes: CS Latency 20 SDRAM Device Attributes: WE Latency 4 04 2, 3 06 0 01 01 IF Write-1/Read Burst, Precharge All, Auto-Precharge 0E -260 10.0ns A0 -360 15.0ns F0 Maximum Data Access Time (tAC) from Clock at -260 6.0ns 60 CLX-1 (CL = 2) -360 9.0ns 90 N/A 00 N/A 00 22 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CLX-1 (CL = 2) 26 8F 0 SDRAM Module Attributes 25 01 1,2,4,8, Full Page Registered/Buffered with PLL 21 24 1 Clock Minimum Clock Cycle Time at CLX-2 (CL = 1) Maximum Data Access Time (tAC) from Clock at CLX-2 (CL = 1) 27 Minimum Row Precharge Time (tRP) 20.0ns 14 28 Minimum Row Active to Row Active delay (tRRD) 20.0ns 14 29 Minimum RAS to CAS delay (tRCD) 20.0ns 14 30 Minimum RAS Pulse width (tRAS) 50.0ns 32 Note s 1, 2 1, 2 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 10ns for -260 CL=2 and for -360 CL=3 and 15ns for -360 CL=2. 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Serial Presence Detect (Part 2 of 2) Byte # Description SPD Entry Value 31 Module Bank Density 32 Address and Command Setup Time Before Clock 2.0ns 40 20 33 Address and Command Hold Time After Clock 1.0ns 10 34 Data Input Setup Time Before Clock 2.0ns 20 35 Data Input Hold Time After Clock 1.0ns 10 Undefined 00 PC100 1.2A 12 36 - 61 Reserved 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 72 73 - 90 256MB Serial PD Data Entry (Hexadecimal) Manufacturers’ JEDEC ID Code 93 - 94 Assembly Manufacturing Date 95 - 98 Assembly Serial Number Module Supports this Clock Frequency 127 Attributes for clock frequency defined in Byte 126 128 - 255 Open for Customer Use 3 Vimercate, Italy 53 -260 31334D33323733344343rr 2D323630542020 -360 ASCII ‘13M32734CC”R”360T’ 31334D33323733344343rr 2D333630542020 “R” plus ASCII blank rr20 5 Year/Week Code yyww 6, 7 Serial Number ssssssss 8 Undefined 100MHz Not Specified 64 -260 CLK0, CL=2,3, ConAP 87 -360 CLK0 CL=3, ConAP 85 Undefined 00 99 - 125 Reserved 126 A400000000000000 91 ASCII ‘13M32734CC”R”260T’ Assembly Part Number Assembly Revision Code cc IBM Toronto, Canada Assembly Manufacturing Location 91 - 92 Checksum Data Note s 4, 5 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 10ns for -260 CL=2 and for -360 CL=3 and 15ns for -360 CL=2. 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Absolute Maximum Ratings Symbol VDD VIN VOUT TA TSTG PD Parameter Rating Power Supply Voltage Units Notes -0.3 to +4.6 Input Voltage Output Voltage SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Register 0 - VDD PLL 0 - VDD V 1 0 to +70 °C 1 -55 to +125 °C 1 11.4 W 1, 2 1 SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Operating Temperature (ambient) Storage Temperature Power Dissipation IOUT Short Circuit Output Current 50 mA FMIN Minimum Operating Frequency 66 MHz 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power is calculated assuming the physical bank is in Auto Refresh Mode. Recommended DC Operating Conditions Symbol Parameter (TA= 0 to 70˚C) Rating Min. Typ. Max. Units Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 — VDD + 0.3 V 1 VIL Input Low Voltage -0.3 — 0.8 V 1 1. All voltages referenced to VSS. 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Capacitance (TA= 25˚C, f=1MHz, VDD= 3.3V ± 0.3V) Organization Symbol Parameter Units x72 Max. CI1 Input Capacitance (A0 - A9, A10/AP, BA0, BA1, A11) CI2 10.5 pF Input Capacitance (RAS) 9 pF CI3 Input Capacitance (CAS) 9.5 pF CI4 Input Capacitance (S0, S2) 12 pF CI5 Input Capacitance (CKE0) 19 pF CI6 Input Capacitance (CK0) 28 pF CI7 Input Capacitance (DQMB0 - DQMB7) 11 pF CI8 Input Capacitance (SA0 - SA2, SCL, WP) 9 pF CI9 Input Capacitance (REGE) 10 pF CI10 Input Capacitance (CK1 - CK3) 16 pF CI11 Input Capacitance (WE) 11 pF CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 16 pF CIO2 Input/Output Capacitance (SDA) 11 pF ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 870Ω Input/Output Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) x72 Symbol Parameter Units Min. Max. Address and Control Inputs 10 10 DQ0-63, CB0 - 7 -2 +2 DQ0-63, CB0 - 7 -2 +2 SDA -1 +1 II(L) Input Leakage Current, any input (0.0V ≤ VIN ≤ 3.6V), All Other Pins Not Under Test = 0V IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V) VOH Output Level Output “H” Level Voltage (IOUT = -2.0mA) 2.4 VDD VOL Output Level Output “L” Level Voltage (IOUT = +2.0mA) 0.0 0.4 Notes µA µA V 1 1. See DC output load circuit. 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Operating, Standby, and Refresh Currents (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) Clock Cycle Parameter Symbol Test Condition 10ns 15ns Units Notes ICC1 tRC = tRC(min), tCK = min Active-Precharge command cycling without burst operation 1692 1354 mA 1 ICC2P CKE0 ≤ VIL(max), tCK = min, CS =VIH (min) 270 202 mA 1 ICC2PS CKE0 ≤ VIL (max), tCK = Infinity, S0, S2 =VIH (min) 33 33 mA ICC2N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 882 598 mA ICC2NS CKE0 ≥ VIH (min), tCK = Infinity, S0, S2 =VIH (min) 195 195 mA ICC3N CKE0 ≥ VIH (min), tCK = min, S0, S2 =VIH (min) 972 904 mA 1 ICC3P CKE0 ≤ VIL (max), tCK = min, S0, S2 =VIH (min) (Power Down Mode) 432 364 mA 1 Burst Operating Current (Active state: 4bank) ICC4 tCK = min, Read command cycling 1872 1264 mA 1, 2 Auto (CBR) Refresh Current ICC5 tCK = min, CBR command cycling 3159 2702 mA 1 Self Refresh Current ICC6 CKE0 ≤ 0.2V 51 51 mA Operating Current 1 bank operation Precharge Standby Current in Power Down Mode Precharge Standby Current in NonPower Down Mode No Operating Current (Active state: 4bank) 1 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK(min). tCK(min) = 10ns for -260 CL=2 and for -360 CL=3 and 15ns for -360 CL=2. 2. The specified values are obtained with the DIMM data outputs open. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module AC Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200µs, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1.2ns (1 Volt/ns rise time). 5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6. A 1 ms stabilization time is required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. AC Characteristics Diagrams tCKH Clock 2.0V 1.4V 0.8V tCKL tSETUP tT Output Zo = 50Ω tHOLD 50pF Input 1.4V AC Output Load Circuit for -260 and -360 tAC tOH tLZ Output 09K3541.F38352 10/99 1.4V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Clock and Clock Enable Parameters Symbol -260 max. (Device CL, tRCD, tRP = 2, 2, 2) -360 max. (Device CL, tRCD, tRP = 3, 2, 2) Min. Max. Min. Max. Registered 10 1000 10 Registered 10 1000 Buffered 10 Parameter Units Notes 1000 ns 1 15 1000 ns 1000 10 1000 ns tCK4 Clock Cycle Time, DIMM CAS Latency = 4 tCK3 Clock Cycle Time, DIMM CAS Latency = 3 tCK2 Clock Cycle Time, DIMM CAS Latency = 2 Buffered 10 1000 15 1000 ns 1 tAC4 Clock Access Time, DIMM CAS Latency = 4 Registered — 7.2 — 7.2 ns 1, 2 tAC3 Clock Access Time, DIMM CAS Latency = 3 Registered — 7.2 — 10.2 ns Buffered — 7.2 — 7.2 ns tAC2 Clock Access Time, DIMM CAS Latency = 2 Buffered — 7.2 — 10.2 ns 1, 2 tCKH Clock High Pulse Width 3 — 3 — ns 3 tCKL Clock Low Pulse Width 3 — 3 — ns 3 tCES Clock Enable Setup Time Registered 2.0 — 2.0 — ns Buffered 7.2 — 7.2 — ns tCEH Clock Enable Hold Time Registered 1.0 — 1.0 — ns Buffered 0.2 — 0.2 — ns tSB Power down mode Entry Time 0 10 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 0.5 10 ns 1 1, 2 1 1 1. DIMM CAS latency = device CL [clock cycles] + 1 for Register mode; DIMM CAS latency is one clock less for Buffer mode. 2. Access time is measured at 1.4V. See AC output load circuit. 3. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Common Parameters -260 Symbol tCS tCH tAS tAH -360 Parameter Units Min. Max. Min. Max. Registered 2.0 — 2.0 — ns Buffered 7.4 — 7.4 — ns Registered 1.1 — 1.0 — ns Buffered 0.0 — 0.0 — ns Registered 2.0 — 2.0 — ns Buffered 7.4 — 7.4 — ns Registered 1.0 — 1.0 — ns Buffered 0.0 — 0.0 — ns Notes 1, 2 Command Setup Time 1, 2 Command Hold Time 1, 2 Address and Bank Select Setup Time 1, 2 Address and Bank Select Hold Time tRCD RAS to CAS Delay 20 — 20 — ns 1 tRC Bank Cycle Time 70 — 70 — ns 1 tRAS Active Command Period 50 100000 50 100000 ns 1 tRP Precharge Time 20 — 20 — ns 1 tRRD Bank to Bank Delay Time 20 — 20 — ns 1 tCCD CAS to CAS Delay Time (Same Bank) 1 — 1 — CLK 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). 2. The set up and hold times refer to the addition of the register. Note that although the Buffered set up times appear much greater, there is no additional clock cycle as there is in Registered mode. Mode Register Set Cycle -260 Symbol tRSC -360 Parameter Mode Register Set Cycle Time Min. Max. Min. Max. 2 — 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). Refresh Cycle -260 Symbol tREF -360 Parameter Refresh Period Units Notes Min. Max. Min. Max. — 64 — 64 ms 1 1. 4096cycles. 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Read Cycle -260 Symbol -360 Parameter Units Min. Max. Min. Max. Notes tOH Data Out Hold Time 3.6 — 3.6 — ns tLZ Data Out to Low Impedance Time 0.6 — 0.6 — ns tHZ3 Data Out to High Impedance Time 3.6 7.2 3.5 7.2 ns 1 tHZ2 Data Out to High Impedance Time 3.6 7.2 3.6 9.2 ns 1 Registered 3 — 3 — CLK tDQZ DQM Data Out Disable Latency Buffered 2 — 2 — CLK 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Write Cycle -260 Symbol -360 Parameter Units Min. Max. Min. Max. tDS Data In Setup Time 2.1 — 2.1 — ns tDH Data In Hold Time 1.6 — 1.6 — ns Registered 10 — 10 — ns tDPL Data input to Precharge Buffered 20 — 20 — ns Registered 4 — 4 — CLK Buffered 5 — 5 — CLK Registered 4 — 4 — CLK Buffered 5 — 5 — CLK Registered 1 — 1 — CLK Buffered 0 — 0 — CLK tDAL3 tDAL2 tDQW Data input to Active, CL = 3 Data input to Active CL = 2 DQM Write Mask Latency ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 20 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Presence Detect Read and Write Cycle Symbol Min. Max. Units SCL Clock Frequency — 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs — 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 — µs Start Condition Hold Time 4.0 — µs tLOW Clock Low Period 4.7 — µs tHIGH Clock High Period 4.0 — µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 — µs tHD:DAT Data in Hold Time 0 — µs tSU:DAT Data in Setup Time 250 — ns fSCL tHD:STA Parameter tR SDA and SCL Rise Time — 1 µs tF SDA and SCL Fall Time — 300 ns Stop Condition Setup Time 4.7 — µs tDH Data Out Hold Time 300 — ns tWR Write Cycle Time — 15 ms tSU:STO Notes 1 1. The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Functional Description and Timing Diagrams Refer to the IBM 128Mb Synchronous DRAM Die Revision A datasheet (Document 33L8019) for the functional description and timing diagrams for buffered-mode operation. Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 20 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Layout Drawing 133.35 5.25 131.35 5.171 127.35 5.014 6.35 .250 3.0 .118 43.33 1.7 (2X) 4.00 .157 Front 42.18 1.661 66.68 2.63 17.80 .700 1.27 pitch .050 (2) 0 3.18 .1255 1.00 width .039 See Detail A Side 4.01 .158 max. Detail A Scale: 4/1 R 1.00 .0393 4.24 .167 4.24 .167 2.0 .078 3.0 .118 (Front) 1.27 ± 0.10 .050 ± .004 Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 20 Millimeters Inches 09K3541.F38352 10/99 IBM13M32734CCA 32M x 72 1 Bank Registered/Buffered SDRAM Module Revision Log Rev Contents of Modification 7/99 Initial release 10/99 Made minor updates. 09K3541.F38352 10/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 20 International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. 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