. IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Features • 168-Pin Registered 8-Byte Dual In-Line Memory Module • 64Mx72 Synchronous DRAM DIMM • Performance: DIMM CAS Latency fCK Clock Frequency fCK Clock Cycle tAC Clock Access • • • • • • • -75A 4 133 100 7.5 10 5.65 5.65 Units MHz ns ns Intended for 100MHz and 133MHz applications Inputs and outputs are LVTTL (3.3V) compatible Single 3.3V ± 0.3V Power Supply Single Pulsed RAS interface SDRAMs have four internal banks Module has two physical banks Fully Synchronous to positive Clock Edge • Programmable Operation: - DIMM CAS Latency: 3, 4 (Registered mode) - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8 - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Data Mask for Byte Read/Write control • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 13/10/2 Addressing (Row/Column/Bank) • 8192 refresh cycles distributed across 64ms • Card size: 5.25" x 0.157" x 1.70" • Gold contacts • SDRAMs in TSOP • Serial Presence Detect with Write protect Description IBM13M64734HCA is a registered 168-Pin Synchronous DRAM Dual In-Line Memory Module (DIMM) organized as a 64Mx72 high-speed memory array and is configured as two 32M x 72 physical banks. The DIMM uses eighteen 32Mx8 SDRAMs in 400 mil TSOP packages. The DIMM achieves highspeed data-transfer rates of 100MHz and 133MHz by employing a prefetch/pipeline hybrid architecture that synchronizes the output data to a system clock. The DIMM is intended for use in applications operating at 100MHz and 133MHz memory bus speeds. All control and address signals are re-driven through registers to the SDRAM devices. The DIMM operates in registered mode (REGE pin tied high), during which the control/address input signals are latched in the register on one rising clock edge and sent to the SDRAM devices on the following rising clock edge (data access is delayed by one clock). A phase-lock loop (PLL) on-board the DIMM redrives the clock signals to the SDRAM devices and registers to minimize system clock loading. (CK0 is connected to the PLL, and CK1, CK2, and CK3 are 06K8049.H03530 5/00 terminated on the DIMM.) A single clock enable (CKE0) controls all devices on the DIMM, enabling the use of SDRAM power-down modes. Prior to any access operation, the device CAS latency and burst type/length/operation type must be programmed into the DIMM by address inputs A0-A9 using the mode register set cycle. The DIMM CAS latency is one clock later due to the address and control signals being clocked to the SDRAM devices. The DIMM uses serial presence detects implemented via a serial EEPROM using the two-pin IIC protocol. The first 128 bytes of serial PD data are programmed and locked by the DIMM manufacturer. The last 128 bytes are available to the customer and can be write protected by providing a high level to pin 81 on the DIMM. An on-board pulldown resistor keeps this in the write-enable mode. All IBM 168-pin DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Card Outline (Front) (Back) 1 85 10 11 94 95 40 124 84 168 41 125 Pin Description CK0-CK3 CKE0 RAS CAS WE S0, S1, S2, S3 A0-A9, A11, A12 Clock Inputs Clock Enable Row Address Strobe Column Address Strobe DQ0 - DQ63 CB0 - CB7 DQMB0 - DQMB7 VDD VSS Write Enable Chip Selects Address Inputs NC SCL A10/AP Address Input/Autoprecharge SDA BA0, BA1 SDRAM Bank Address Inputs SA0-2 SPD Write Protect REGE WP ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 22 Data Input/Output Check Bit Data Input/Output Data Mask Power (3.3V) Ground No Connect Serial Presence Detect Clock Input Serial Presence Detect Data Input/Output Serial Presence Detect Address Inputs Register Enable 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side 1 VSS 85 VSS 22 CB1 106 CB5 43 VSS 127 VSS 64 VSS 148 VSS 107 VSS 44 NC 128 CKE0 65 DQ21 149 DQ53 108 NC 45 S2 129 S3 66 DQ22 150 DQ54 2 DQ0 86 DQ32 23 VSS 3 DQ1 87 DQ33 24 NC 4 DQ2 88 DQ34 25 NC 109 NC 46 DQMB2 130 DQMB6 67 DQ23 151 DQ55 5 DQ3 89 DQ35 26 VDD 110 VDD 47 DQMB3 131 DQMB7 68 VSS 152 VSS 6 VDD 90 VDD 27 WE 111 CAS 48 NC 132 NC 69 DQ24 153 DQ56 7 DQ4 91 DQ36 28 DQMB0 112 DQMB4 49 VDD 133 VDD 70 DQ25 154 DQ57 8 DQ5 92 DQ37 29 DQMB1 113 DQMB5 50 NC 134 NC 71 DQ26 155 DQ58 9 DQ6 93 DQ38 30 S0 114 S1 51 NC 135 NC 72 DQ27 156 DQ59 10 DQ7 94 DQ39 31 NC 115 RAS 52 CB2 136 CB6 73 VDD 157 VDD 11 DQ8 95 DQ40 32 VSS 116 VSS 53 CB3 137 CB7 74 DQ28 158 DQ60 12 VSS 96 VSS 33 A0 117 A1 54 VSS 138 VSS 75 DQ29 159 DQ61 13 DQ9 97 DQ41 34 A2 118 A3 55 DQ16 139 DQ48 76 DQ30 160 DQ62 14 DQ10 98 DQ42 35 A4 119 A5 56 DQ17 140 DQ49 77 DQ31 161 DQ63 15 DQ11 99 DQ43 36 A6 120 A7 57 DQ18 141 DQ50 78 VSS 162 VSS 16 DQ12 100 DQ44 37 A8 121 A9 58 DQ19 142 DQ51 79 CK2 163 CK3 17 DQ13 101 DQ45 38 A10/AP 122 BA0 59 VDD 143 VDD 80 NC 164 NC 18 VDD 102 VDD 39 BA1 123 A11 60 DQ20 144 DQ52 81 WP 165 SA0 VDD 124 VDD 61 NC 145 NC 82 SDA 166 SA1 VDD 125 CK1 62 NC 146 NC 83 SCL 167 SA2 84 VDD 168 VDD 19 DQ14 103 DQ46 40 20 DQ15 104 DQ47 41 21 CB0 105 CB4 42 CK0 126 A12 63 NC 147 REGE Note: All pin assignments are consistent with all 8-byte unbuffered versions. Ordering Information Part Number Organization Clock Cycle (CL, tRCD, tP) Device Access Time Leads Dimension Power IBM13M64734HCA-75AT 64Mx72 7.5ns (3,3,3) 5.65ns Gold 5.25" x 0.157" x 1.70" 3.3V 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module 64Mx72 SDRAM DIMM Block Diagram (2 Bank, 32Mx8 SDRAMs) RS1 RS0 DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 * DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D0 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D9 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D1 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D10 CS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D3 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 S0-S3 DQMB0 to DQMB7 BA0-BA1 A0-A12 RAS CAS CKE0 WE 10k VDD REGE PCK D11 CS D14 R E G I S T E R CS D4 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D6 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D15 DQMB6 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CS D7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D16 CS DQMB7 D12 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CS CS D8 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS D17 Note: Exact DQ wiring may differ from that shown above. #Unless otherwise noted, resistor values are 10 Ohms. D13 RS0-RS3 RDQMB0 - RDQMB7 BS0-BS1: SDRAMs D0-D17 RBA0 - RBA1 A0-A12: SDRAMs D0-D17 RA0-RA12 RRAS RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 RCAS CKE: SDRAMs D0 - D17 RCKE0 RWE WE: SDRAMs D0 - D17 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 22 D5 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM DQMB3 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS RS3 RS2 DQMB2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS DQMB5 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS Serial Presence Detect SCL WP 47K SDA A0 A1 A2 SA0 SA1 SA2 PLL CK0 CK1, CK2, CK3 Terminated VDD D0 - D17 VSS D0 - D17 Note: DQ wiring may differ from that described in this drawing; however, DQ/DQMB relationships are maintained as shown. 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Input/Output Functional Description Symbol Type Signal Polarity Function CK0 - CK3 Input Pulse Positive Edge CKE0 Input Level Activates the SDRAM CK signal when high and deactivates the CK signal when low. Active High By deactivating the clocks, CKE low initiates the Power Down mode, the Suspend mode, or the Self Refresh mode. S0-S3 Input Pulse Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. BA0, 1 Input Level — Selects which SDRAM bank of four is activated. The system clock inputs. All the SDRAM inputs are sampled on the rising edge of their associated clock. CK0 drives the PLL. CK1, CK2, and CK3 are terminated. A0 - A9 A10/AP A11, A12 Input Level — During a Bank Activate command cycle, A0-A12 defines the row address (RA0RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9 define the column address (CA0CA9) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0, BA1 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1. If AP is low, BA0 and BA1 are used to define which bank to precharge. DQ0 - DQ63, CB0 - CB7 Input Output Level — Data and Check Bit Input/Output pins. DQMB0 DQMB7 Input VDD, VSS Supply Pulse The Data Input/Output masks, associated with one data byte, place the DQ buffers in a high-impedance state when sampled high. In Read mode, DQMB has a latency of two clock cycles in Buffered mode or three clock cycles in Registered mode, and conActive High trols the output buffers like an output enable. In Write mode, DQMB has a zero clock latency in Buffered mode and a latency of one clock cycle in Registered mode. In this case, DQMB operates as a byte mask by allowing input data to be written if it is low but blocking the write operation if it is high. — Power and ground for the module. Active High (Register The Register Enable pin must be held high to permit the DIMM to operate in “registered” mode (signals re-driven to SDRAMs when clock rises, and held valid until next Mode rising clock). Enable) REGE Input Level SA0 - 2 Input Level — These signals are tied at the system planar to either VSS or VDD to configure the serial SPD EEPROM. SDA Input Output Level — This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to VDD to act as a pullup. SCL Input Pulse — This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to VDD to act as a pullup. WP Input Level 06K8049.H03530 5/00 Active High This signal is pulled low on the DIMM to enable data to be written into the last 128 bytes of the SPD EEPROM. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Serial Presence Detect (Part 1 of 2) Byte # Description 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 2 Fundamental Memory Type 3 SPD Entry Value Serial PD Data Entry (Hexadecimal) 128 80 256 08 SDRAM 04 Number of Row Addresses on Assembly 13 0D 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Banks 2 02 6-7 Data Width of Assembly x72 4800 8 Assembly Voltage Interface Levels LVTTL 01 9 SDRAM Device Cycle Time (CL = 3) 7.5ns 75 10 SDRAM Device Access Time from Clock at CL=3 5.4ns 54 11 Assembly Error Detection/Correction Scheme ECC 02 12 Assembly Refresh Rate/Type SR/1X(7.8125µs) 82 13 SDRAM Device Width x8 08 14 Error Checking SDRAM Device Width x8 08 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 1 Clock 01 16 SDRAM Device Attributes: Burst Lengths Supported 1,2,4,8 0F 17 SDRAM Device Attributes: Number of Device Banks 4 04 18 SDRAM Device Attributes: CAS Latency 2, 3 06 19 SDRAM Device Attributes: CS Latency 0 01 20 SDRAM Device Attributes: WE Latency 0 01 21 SDRAM Module Attributes Registered/Buffered with PLL IF 22 SDRAM Device Attributes: General Write-1/Read Burst, Precharge All, Auto-Precharge 0E 23 Minimum Clock Cycle at CLX-1 (CL = 2) 15.0ns 1F 24 Maximum Data Access Time (tAC) from Clock at CLX-1 (CL = 2) 9.0ns 90 25 Minimum Clock Cycle Time at CLX-2 (CL = 1) N/A 00 26 Maximum Data Access Time (tAC) from Clock at CLX-2 (CL = 1) N/A 00 27 Minimum Row Precharge Time (tRP) 20.0ns 14 28 Minimum Row Active to Row Active delay (tRRD) 15.0ns 0F 29 Minimum RAS to CAS delay (tRCD) 20.0ns 14 30 Minimum RAS Pulse width (tRAS) 45.0ns 2D 31 Module Bank Density 256MB 40 Notes 1, 2 1, 2 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 7.5ns (133 MHz). 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). 9. These values apply to PC100 applications only. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Serial Presence Detect (Part 2 of 2) Byte # Description SPD Entry Value Serial PD Data Entry (Hexadecimal) 32 Address and Command Setup Time Before Clock 1.5ns 15 33 Address and Command Hold Time After Clock 0.8ns 08 34 Data Input Setup Time Before Clock 1.5ns 15 35 Data Input Hold Time After Clock 0.8ns 08 Undefined 00 JEDEC 02 36 - 61 Reserved 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 72 Manufacturers’ JEDEC ID Code Assembly Manufacturing Location 73 - 90 Assembly Part Number 91 - 92 Assembly Revision Code 93 - 94 Assembly Manufacturing Date 95 - 98 Assembly Serial Number 99 - 125 Reserved 126 Module Supports this Clock Frequency 127 Attributes for clock frequency defined in Byte 126 128 - 255 Open for Customer Use Checksum Data cc IBM A400000000000000 Toronto, Canada 91 Vimercate, Italy 53 3 ASCII 31334D363437333448 ‘13M64734HC”R”-75AT’ 43rr2D373548542020 “R” plus ASCII blank Notes 4, 5 rr20 5 Year/Week Code yyww 6, 7 Serial Number ssssssss 8 Undefined Not Specified 100MHz 64 9 CLK0, CL=3, ConAP 85 9 Undefined 00 1. In a registered DIMM, data is delayed an additional clock cycle due to the on-DIMM pipeline register (that is, Device CL [clock cycles] + 1 = DIMM CAS latency). 2. Minimum application clock cycle time is 7.5ns (133 MHz). 3. cc = Checksum Data byte, 00-FF (Hex). 4. “R” = Alphanumeric revision code, A-Z, 0-9. 5. rr = ASCII coded revision code byte “R”. 6. ww = Binary coded decimal week code, 01-52 (Decimal) ‘ 01-34 (Hex). 7. yy = Binary coded decimal year code, 00-99 (Decimal) ‘ 00-63 (Hex). 8. ss = Serial number data byte, 00-FF (Hex). 9. These values apply to PC100 applications only. 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Absolute Maximum Ratings Symbol VDD VIN VOUT TA TSTG PD Parameter Rating Power Supply Voltage Units Notes V 1 0 to +70 °C 1 -55 to +125 °C 1 -0.3 to +4.6 Input Voltage Output Voltage SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Register 0 - VDD PLL 0 - VDD SDRAM Devices -1.0 to +4.6 Serial PD Device -0.3 to +6.5 Operating Temperature (ambient) Storage Temperature 11.9 W 1, 2 IOUT Power Dissipation Short Circuit Output Current 50 mA 1 FMIN Minimum Operating Frequency 66 MHz 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Maximum power is calculated assuming the physical bank is in Auto Refresh Mode. Recommended DC Operating Conditions Symbol Parameter (TA= 0 to 70˚C) Rating Units Notes 3.6 V 1 Min. Typ. Max. 3.0 3.3 VDD Supply Voltage VIH Input High Voltage 2.0 — VDD + 0.3 V 1 VIL Input Low Voltage -0.3 — 0.8 V 1 1. All voltages referenced to VSS. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Capacitance (TA= 25˚C, f=1MHz, VDD= 3.3V ± 0.3V) Organization Symbol Parameter Units x72 Max. CI1 Input Capacitance (A0 - A9, A10/AP, BA0, BA1, A11, A12) 21 pF CI2 Input Capacitance (RAS) 20 pF CI3 Input Capacitance (CAS) 20 pF CI4 Input Capacitance (S0, S3) 13 pF CI5 Input Capacitance (CKE0) 15 pF CI6 Input Capacitance (CK0) 28 pF CI7 Input Capacitance (DQMB0 - DQMB7) 13 pF CI8 Input Capacitance (SA0 - SA2, SCL, WP) 9 pF CI9 Input Capacitance (REGE) 10 pF CI10 Input Capacitance (CK1 - CK3) 14 pF CI11 Input Capacitance (WE) 23 pF CIO1 Input/Output Capacitance (DQ0 - DQ63, CB0 - CB7) 18 pF CIO2 Input/Output Capacitance (SDA) 11 pF 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module DC Output Load Circuit 3.3 V 1200Ω VOH (DC) = 2.4V, IOH = -2mA Output VOL (DC) = 0.4V, IOL = 2mA 50pF 870Ω Input/Output Characteristics Symbol II(L) (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) x72 Parameter Input Leakage Current, any input (0.0V ≤ VIN ≤ 3.6V), All Other Pins Not Under Test = 0V Min. Max. Address and Control Inputs 10 10 DQ0-63, CB0 - 7 -2 +2 DQ0-63, CB0 - 7 -2 +2 SDA -1 +1 IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ 3.6V) VOH Output Level Output “H” Level Voltage (IOUT = -2.0mA) 2.4 VDD VOL Output Level Output “L” Level Voltage (IOUT = +2.0mA) 0.0 0.4 Units Notes µA µA V 1 1. See DC output load circuit. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Operating, Standby, and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) Symbol (Physical Bank 0/ Physical Bank 1) Test Condition Speed -75A Clock Cycle 7.5ns Units Notes Burst Operating Mode/Active Standby ICC4/ICC3N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 2085 mA 1, 2 Burst Operating Mode/Precharge Standby ICC4/ICC2N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 1815 mA 1, 2 Burst Operating Mode/Auto Refresh ICC4/ICC5 CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 3279 mA 1, 2 Non-burst Operating Mode/Active Standby ICC1/ICC3N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 1929 mA 1, 2 Non-burst Operating Mode/Precharge Standby ICC1/ICC2N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 1407 mA 1, 2 Non-burst Operating Mode/Auto Refresh ICC1/ICC5 CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 2964 mA 1 Active Standby/Active Standby ICC3N/ICC3N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 1389 mA Active Standby/Precharge Standby ICC3N/ICC2N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 1119 mA Active Standby/Auto Refresh ICC3N/ICC5 CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 2424 mA Precharge Standby/Precharge Standby ICC2N/ICC2N CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 849 mA Precharge Standby/Auto Refresh ICC2N/ICC5 CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 2154 mA 1 Auto Refresh/Auto Refresh ICC5/ICC5 CKE ≥ VIH (min), tCK = min, S0 - S3 =VIH (min) 3300 mA 1 Active Standby Power Down/ Active Standby Power Down ICC3p/ICC3p CKE ≤ VIL (max), tCK = min, S0 - S3 =VIH (min) 417 mA Active Standby Power Down/Precharge Standby Power Down ICC3p/ICC2p CKE ≤ VIL (max), tCK = min, S0 - S3 =VIH (min) 381 mA Precharge Standby Power Down/ Precharge Standby Power Down ICC2p/ICC2p CKE ≤ VIL (max), tCK = min, S0 - S3 =VIH (min) 345 mA Precharge Standby Non-power Down/Precharge Standby Non-power Down (NO CLOCK) ICC2NS/ICC2NS CKE ≥ VIH (min), tCK = Infinity, S0 - S3 =VIH (min) 156 mA Precharge Standby Power Down/Precharge Standby Power Down (NO CLOCK) ICC2PS/ICC2PS CKE ≤ VIH (min), tCK = Infinity, S0 - S3 =VIH (min) 84 mA ICC6/ICC6 CKE ≤ VIH (min), tCK = Infinity, S0 - S3 =VIH (min) 102 mA Parameter Self Refresh Current /Self Refresh Current 1 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK(min). 2. The specified values are obtained with the output open. 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module AC Characteristics (TA= 0 to +70˚C, VDD= 3.3V ± 0.3V) 1. An initial pause of 200µs, with CKE0 held high, is required after power-up. A Precharge All Banks command must be given followed by a minimum of eight Auto (CBR) Refresh cycles before or after the Mode Register Set operation. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point. 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1.2ns (1 Volt/ns rise time). 5. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 6. A 1 ms stabilization time is required by the on-board PLL circuit to phase lock its feedback signal to its reference signal. 7. All timings are specified at the input receiver of the signal, not at the DIMM connector. AC Characteristics Diagrams tCKH Clock 2.0V 1.4V 0.8V tCKL tSETUP tT Output Zo = 50Ω tHOLD 50pF Input 1.4V AC Output Load Circuit tAC tOH tLZ Output ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 22 1.4V 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Clock and Clock Enable Parameters Symbol Parameter -75A max. (Device CL, tRCD, tRP= 3, 3, 3) Min. Max. Units Notes tCK4 Clock Cycle Time, DIMM CAS Latency = 4 7.5 1000 ns 1 tAC4 Clock Access Time, DIMM CAS Latency = 4 — 5.65 ns 1, 2 tCKH Clock High Pulse Width 2.5 — ns 3 tCKL Clock Low Pulse Width 2.5 — ns 3 tCES Clock Enable Setup Time 1.65 — ns 1 tCEH Clock Enable Hold Time 1 1. 2. 3. 0.35 — ns tSB Power Down Mode Entry Time 0 7.5 ns tT Transition Time (Rise and Fall) 0.5 10 ns DIMM CAS latency = device CL [clock cycles] + 1 for Register mode. Access time is measured at 1.4V. See AC output load circuit. tCKH is the pulse width of CLK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CLK measured from the negative edge to the positive edge referenced to VIL (max). 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Common Parameters -75A Symbol Parameter Min. Max. Units Notes tCS Command Setup Time 1.65 — ns 1 tCH Command Hold Time 0.35 — ns 1 tAS Address and Bank Select Setup Time 1.65 — ns 1 tAH Address and Bank Select Hold Time 0.35 — ns 1 20 — ns 1 67.5 — ns 1 tRCD RAS to CAS Delay tRC Bank Cycle Time tRAS Active Command Period 45 100000 ns 1 tRP Precharge Time 20 — ns 1 tRRD Bank to Bank Delay Time 15 — ns 1 tCCD CAS to CAS Delay Time (Same Bank) 1 — CLK 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). Mode Register Set Style -75A Symbol tRSC Parameter Mode Register Set Cycle Time Min. Max. 2 — Units Notes CLK 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock as follows: the number of clock cycles = specified value of timing/clock period (count fractions as a whole number). Refresh Cycle -75A Symbol Parameter Min. Max. Units Notes 1, 2 tREF Refresh Period — 64 ns tREFI Average Refresh Interval Time — 7.813 µs tSREX Self Refresh Exit Time 10 — ns 3 1. 8192 cycles 2. Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to ‘wake up’ the device. 3. Self Refresh exit is asynchronous, requiring 10ns to ensure initiation. Self Refresh exit is complete in 10ns + tRC. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 14 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Read Cycle Symbol -75A Parameter Min. Max. Units tOH Data Out Hold Time 3.1 — ns tLZ Data Out to Low Impedance Time 0.6 — ns tHZ3 Data Out to High Impedance Time 3.6 6.6 ns tDQZ DQM Data Out Disable Latency 3 — CLK Notes 1 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels. Write Cycle Symbol -75A Parameter Min. Max. Units tDS Data In Setup Time 1.75 — ns tDH Data In Hold Time 1.05 — ns tDPL Data input to Precharge 15 — ns tDAL3 Data in to Active Delay (CAS Latency = 3) 5 — CLK tDQW DQM Write Mask Latency 1 — CLK Presence Detect Read and Write Cycle Symbol fSCL -75A Parameter Min. Max. Units SCL Clock Frequency — 100 KHz TI Noise Suppression Time Constant at SCL, SDA Inputs — 100 ns tAA SCL Low to SDA Data Out Valid 0.3 3.5 µs tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 — µs 4 — µs 4.7 — µs tHD:STA Start Condition Hold Time tLOW Clock Low Period tHIGH Clock High Period 4 — µs 4.7 — µs Data in Hold Time 0 — µs Data in Setup Time 250 — ns — 1 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) tHD:DAT tSU:DAT tr SDA and SCL Rise Time tf SDA and SCL Fall Time — 300 ns Stop Condition Setup Time 4.7 — µs tDH Data Out Hold Time 300 — ns tWR Write Cycle Time — 15 ms tSU:STO Notes 1 1. The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 15 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Wiring and Topology This section contains the information needed to understand the timing relationships presented in AC Characteristics beginning on page 12. Each timing parameter is measured at the first receiving device (SDRAM DQ pin for data input, register input pin for address and control, and PLL Clk input pin for clock). This section will enable the user to understand the pin numbers on the DIMM, the net structures, and the loading associated with these devices. For detailed timing analysis, contact the IBM Marketing Representative for simulation models. Modeling is strongly recommended to determine delay adders of the entire net structure. Pin Assignments for the 256Mbit SDRAM Planar Component TOP VIEW VDD 1 54 VSS DQ0 VDDQ NC DQ1 2 3 4 5 53 52 51 50 DQ7 VSSQ NC DQ6 VSSQ NC DQ2 VDDQ NC 6 7 8 9 10 49 48 47 46 45 VDDQ NC DQ5 VSSQ NC DQ3 11 44 DQ4 VSSQ 12 43 VDDQ NC VDD NC WE CAS RAS CS BS0 13 14 15 16 17 18 19 20 42 41 40 39 38 37 36 35 NC VSS NC DQM CLK CKE A12 A11 BS1 A10/AP A0 21 22 23 34 33 32 A9 A8 A7 A1 A2 24 25 26 27 31 30 A6 A5 29 28 A4 VSS A3 VDD 54-pin Plastic TSOP(II) 400mil 16Mbit x 8 I/O x 4 Bank ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 16 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module The table below describes the physical DQ wiring information for each SDRAM on the DIMM. Note that the DQ wiring is different from that described in the Block Diagram on page 4; the DQs are scrambled within the same device for wiring optimization. Data Wiring Cross Reference DQ SDRAM Designator DQ SDRAM Pin Number DQ0 DQ1 Device position to DIMM Tab Data I/O1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 2 7 38 15 47 CB2 55 23 63 31 0 33 8 41 CB1 48 16 55 25 5 6 37 14 46 CB7 54 22 62 30 1 34 9 42 CB5 49 17 57 26 DQ2 8 5 36 13 45 CB3 53 21 61 29 2 35 10 40 CB4 50 18 58 27 DQ3 11 4 39 12 44 CB6 52 20 60 28 3 32 11 43 CB0 51 19 59 24 DQ4 44 3 32 11 43 CB0 51 19 59 24 4 39 12 44 CB6 52 20 60 28 DQ5 47 2 35 10 40 CB4 50 18 58 27 5 36 13 45 CB3 53 21 61 29 DQ6 50 1 34 9 42 CB5 49 17 57 26 6 37 14 46 CB7 54 22 62 30 DQ7 53 0 33 8 41 CB1 48 16 56 25 7 38 15 47 CB2 55 23 63 31 1. These numbers can be associated with the corresponding DIMM tab pin by referencing the DIMM connector pinout on page 3 of this specification. Example: DQ14 at the DIMM tab (pin 19) is wired to both SDRAM device position D2, pin 5 and SDRAM D11, pin 50. Data Topology 10Ω ± 5% DIMM Connector TL0 TL1 TL0 SDRAM Note: Transmission lines (“TL”) are represented as cylinders and labeled with length designators. These are the only lines which represent physical trace segments. For more detailed topology information please refer to the current PC133 SDRAM Registered DIMM specification. TL1 Total Unit Min Max Min Max Min 0.126 0.345 1.013 1.415 1.145 Max 1.658 in. The table below describes the input wiring for each clock on the DIMM. Clock Input Wiring CK0 CK1 CK2 CK3 PLL CLK Input Pin 24 Termination RC Termination RC Termination RC 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 17 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Clock Topology CK0 DIMM Connector 10Ω TL0 TL1 Phase Lock Loop (PLL) TL0 TL1 Unit 0.127 2.647 in. 12pF 10Ω CK1, CK2, and CK3 12pf ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 18 of 22 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module The table below describes the address and control information for each signal on the DIMM. Note that several signals are double loaded at the input of the register. Register Input Wiring Register Type:ALVCF162835 Register Pin number 30 31 33 34 36 37 38 40 41 42 43 44 45 47 48 49 51 52 54 Register 1 Signal CLK CAS RAS A1 A0 A3 A2 A5 A4 A7 A6 A9 A8 BS0 A10 A11 BS1 CKE0 CKE0 Register 2 Signal CLK NC NC BS1 A11 A10 BS0 A8 A9 A6 A7 A4 A5 A2 A3 A0 A1 RAS CAS Register 3 Signal CLK DQMB0 DQMB4 DQMB1 DQMB5 A12 A12 S0 NC WE WE NC S2 DQMB6 DQMB2 NC NC DQMB7 DQMB3 Address/Control Signal Topology DIMM Connector TL0 Register Input Unit Min TL0 Register Input 0.199 Max 1.336 in. Note: Each Signal has two register input loads with the exception of DQMBs and Chip Select which have one. For more detailed topology information please refer to the current PC133 SDRAM Registered DIMM specification. Functional Description and Timing Diagrams Refer to the IBM PC133 256Mb Synchronous DRAM data sheet (document 29L0000) for the functional description and timing diagrams for buffered-mode operation. Refer to the IBM Application Notes Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. 06K8049.H03530 5/00 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 19 of 22 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Layout Drawing 133.35 5.25 131.35 5.171 127.35 5.014 D2 D3 D4 D5 D6 D7 D8 43.33 1.7 D1 (2X) 4.00 .157 D0 Front Register 1 PLL 1.27 pitch .050 1.00 width .039 65.68 2.63 17.78 .700 42.18 1.661 3.0 .118 6.35 .250 (2) 0 3.1877 .1255 Register 3 See Detail A Back D17 D16 D15 D14 D13 D12 D11 D10 D9 Register 2 Side Detail A 3.99 0.157 max. Scale: 4/1 Back R 1.00 .0393 4.24 .167 min. 4.24 .167 min. 2.0 .078 3.0 .118 Front 1.273 ± 0.10 .050 ± .004 Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 20 of 22 Millimeters Inches 06K8049.H03530 5/00 IBM13M64734HCA 64M x 72 Two-Bank Registered SDRAM Module Revision Log Rev 5/00 06K8049.H03530 5/00 Contents of Modification Initial release ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 21 of 22 Copyright and Disclaimer Copyright International Business Machines Corporation 1999, 2000 All Rights Reserved Printed in the United States of America May 2000 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www.chips.ibm.com 06K8049.H03530. 5/00