Able Systems Limited Northwich, Cheshire, England www.able-systems.com USERS' GUIDE to the ABLE SYSTEMS A104C Single-Chip Printer Controller Contents Section 1 Introduction and On-line Information 2 Connections 3 Installation 4 Operation and Programming Appendix Recommended Operating Circuit Schematic Diagram 1 INTRODUCTION This document is a Users' Guide, written for the person designing-in, connecting and using the Able Systems A104C single-chip printer controller for the EPSON M-160 series of 4-needle mini-printer mechanisms. Please read it carefully before making any connection. The A104C is an enhanced replacement for the A160C series of controller chips, and shares many features of the range. However, it should be noted that although every effort has been made to simplify the re-drafting of PCB layouts, the pin connections are entirely different. Throughout this document, the designation A160C can generally be taken to represent the A150C, A160C, A163C, A164C, and national variants of these devices. 1.1 ON-LINE INFORMATION Able Systems maintains a site on the World Wide Web. This will include application data updates, product announcements, and e-mail facilities for customer support. The URL of our web site is: Our e-mail address is: http://www.able-systems.com [email protected] COPYRIGHT NOTICE and DISCLAIMER Note that copyright subsists in all Able Systems intellectual property, including controller firmware (embedded software) and circuit diagrams, pin connection lists and application data. No warranty in respect of patent rights of Able Systems Limited or of third parties is given. Unauthorised reproduction or amendment of controller firmware may result in prosecution. Note: EPSON is a registered mark of its owner Seiko Epson Corporation. References to this or other owners' marks in this document are for illustrative purposes only. Copyright © Able Systems Limited 1999 All Rights Reserved A104C_user_guide2.lwp//11/10/00, 17:08// IKE A104C Users’ Guide Page 2 of 8 2 A104C PIN CONNECTIONS The A104C is supplied as a 44-pin flatpack, suitable for surface mounting on a PCB. For designers converting from the A160C series of controllers, the old pinouts are given for reference. A104C pin no A160C pin no I/O Function 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 32 33 34 4 6 ----6 39 37 --1 24 3 2 20 ----- o/p o/p o/p i/p i/p ----i/p i/p o/p --i/p i/p o/p i/p i/p --i/p 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 22 23 36 ----------------12 13 14 15 16 17 18 19 40 --27 28 29 30 31 i/p i/p o/p --------------i/p i/p i/p i/p i/p i/p i/p i/p i/p ----o/p o/p o/p o/p o/p Solenoid C Solenoid D Solenoid D IC RESET (N.B. Inverted cf A160C) Serial Rx N/C Spare (N/C) Parallel Data Strobe Mech Tacho Mech Motor Drive Spare (N/C) Mech Reed Switch (Reset) Feed Switch XTAL OUT (N.B. Freq. altered cf A160C) XTAL IN Vss (OV power) N/C Classic/New Select (N/C = Classic) and alternative Parallel mode selection (Low = Parallel) Inverted Mode Select Self Test Mode Busy EEPROM CS, or character set selection B0 } EEPROM CLK, or character set selection B1 } See below EEPROM DI, or character set selection B2 } for details EEPROM DO, or character set selection B3 } N/C N/C N/C Must be tied to Vcc Data Input D0 } Data Input D1 } (N.B. D0-D7 require Data Input D2 } pullup resistors) Data Input D3 } Data Input D4 } Data Input D5 } (D5 is Baud Rate Select in serial mode) Data Input D6 } (D6 is Baud Rate Select in serial mode) Data Input D7 } (D7 is Parallel/Serial Mode Select at reset) Vcc (+5V power) N/C Solenoid A Solenoid A Solenoid B Solenoid B Solenoid C Notes: 1. N/C = Make no connection to this pin 2. Unless specified otherwise, all inputs/outputs function as before. 3. A recommended circuit schematic for the A104C is attached in an Appendix. A104C Users’ Guide Page 3 of 8 3 A104C INSTALLATION The A104C must be installed in a circuit generally corresponding to that in the Appendix. No responsibility can be accepted for customers’ applications based on any other design. The essential external requirements of the A104C are: Ÿ A clean DC power supply of 5V ± 5% Ÿ A timing crystal or ceramic resonator circuit (nominally 11 MHz if the serial data interface is to be used) Ÿ A reset generator providing a positive-going pulse of at least 24 oscillator cycles (typically 2.2 microseconds) after the oscillator is established. A pulse of 10 ms will normally be sufficient. Ÿ A motor drive and common solenoid drive circuit Ÿ Four (4) solenoid drive circuits Ÿ Processing circuits for the mechanism tacho, reed switch and user interface as applicable It is recommended that the power supply for the controller circuits is separate from the supply to the mechanism motor and solenoid circuits, to minimise interference. Optionally, an EEPROM (E2PROM) of the type 9346 may be attached to pins 22 to 25. The A104C will recognize the presence of the EEPROM and configure it appropriately on initial power-up. Serial and parallel data modes are selected using pin 37: Parallel mode is selected if this is held low (0V) at reset time Serial mode is selected if this is held high (pullup to +5V) at reset time Serial data Baud rates are selected on pins 35 (D5) and 36 (D6) when the chip is in serial mode. Serial data Baud rates: D5 D6 300 1 0 1200 0 1 2400 1 1 9600 0 0 Note that the combination for 9600 Baud was used to select 110 Baud in the A160C family. 4 A104C OPERATION and PROGRAMMING Mechanism selection All the four-needle EPSON mini-printer mechanisms (M150, M160, M163, M164 and M170) are now supported by a single A104C device. Mechanism selection is automatic. The chip exercises the mechanism on the first power-up, and its type is sensed by counting tacho pulses per head cycle. The result is stored in the EEPROM, and on subsequent power-ups the mechanism identity is read from there. If the EEPROM is not fitted, the chip will carry out the mechanism selection test at every power-up. Printing modes and data buffer Character printing modes include graphics, inverted, double height and double width as in the A160C series. Graphics mode is cancelled at the end of every dot line, whereas the combinations of double height and width remain in force until cancelled by a new command. Note that whereas in the A160C a new ESCape sequence cleared the data buffer, the A104 will print data before the new ESCape code and then implement the new mode selection. The data buffer accommodates 48 bytes, which (unlike the A160C) can extend over many physical print lines, depending on the mechanism in use and the data format; and new data can be entering the buffer as previous data are being printed. A104C Users’ Guide Page 4 of 8 Character sets In addition to the 8 country-specific sets of the A160C, a full 8 bit IBM 224-character set is supported. Previous versions of the A160C family of controller chips have been supplied programmed with UK, French, German, “Scandinavian”, Danish/Norwegian, Swedish, Japanese and Spanish character variations (often to special order). The A104C contains all these variants, which are selected by EEPROM setting (after a software command) or jumpers. If the selection is made from the host by software the structure of the command is as follows: <ESC><127><n> where n is a byte of the form [X,X,X,X,B3,B2,B1,B0] (X = don’t care) Country selection: B3 B2 B1 B0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 Character set Full 8 bit IBM UK French German Scandinavian Danish Swedish Japanese Spanish The command <ESC><126> stores the current country selection and print mode (double height, etc) in the EEPROM (if fitted). If this code is not received (or no EEPROM is fitted) the A104C reverts to default values on the next power up. If the selection is made by hardware links or PCB jumpers (no EEPROM fitted), please note that the internal data bits are logically inverted with respect to the outside connections, so to assert a “1” the input pin should be connected to logic 0 (GND, 0V), and to assert a “0” it should be left open or connected to Vcc (+5V). The software command <ESC><127><n> temporarily overrides the EEPROM or jumper settings. New A104C control codes and retained A160C control codes <ESC><n> (If buffer is not empty, print buffer contents and) Set print mode:. Note: n is a byte of the form [ 0,0,0,0,B3,B2,B1,B0] (all except the lower 4 bits must be zero, to avoid conflict with the new ESCape codes below). Mode selection: B3 B2 B1 B0 0 X X X 1 0 X X 1 X 0 X 1 X X 0 1 X X X Any combination of these modes is permissible. end of every dot line. Print Mode Default Inverted (reversed) mode Graphics mode Double width mode Double height mode As in the A160C, the graphics mode is reset at the <ESC><ESC> (Print any buffer contents, and) Print Self test message. <ESC><127><n> (Print any buffer contents, and) Select country character set. A104C Users’ Guide Page 5 of 8 /Section continues... A104C Users’ Guide Page 6 of 8 <ESC><126> (Print any buffer contents, and) Store country character set and print mode in EEPROM. <ESC><125> (Print any buffer contents, and) Clear the EEPROM. <CR> <LF> <CR><LF> <LF><CR> Print any buffer contents (line terminator). Print any buffer contents (line terminator). Print any buffer contents (line terminator). Print any buffer contents (line terminator). Treat as <CR><LF>. Treat as <CR><LF>. Treat as single <CR><LF>. Treat as single <CR><LF>. A character line is automatically terminated and printed if it reaches the full line width for a given mechanism and print mode setting. Note that if any of the above 4 line terminator codes is received immediately after a character which completes a printable line, it will be ignored. This treatment differs from the A160C but will generally be an improvement. <VTAB> Print any buffer contents, and feed 30 dotlines. Operational notes on the EEPROM for system designers On power up, the A104C chip attempts to read from the EEPROM memory location 00. If the code read back is “Hi” it assumes that there is an EEPROM connected, and that it contains useful information, which is read into the appropriate A104C RAM locations. The chip then exits the power on routine. If the code “Hi” is not read back from the EEPROM, there is either no useful information stored in the EEPROM or there is no EEPROM connected to the chip. In this event the chip will cycle the mechanism and identify the mechanism type and the tacho edge which is furthest away from the mechanism reset signal (to minimise dot line jitter). The chip will then attempt to write “Hi” and other default setup data to the EEPROM. The chip then attempts to read the EPROM: if the chip reads back the code “Hi”, the mechanism data and setup data has been stored in the EEPROM, and the chip exits the power on routine. If for the second time of reading the EEPROM the code word “Hi” is not found, the chip assumes there is no EEPROM attached and it uses the jumper settings for the character set information on Pins 22 to 25, and the inverted mode hardware select Pin 19. The chip exits the power on routine. If the print quality deteriorates due to dotlines being displaced, the EEPROM can be cleared and the chip forced to repeat the first-time initialisation by sending the code <ESC><125>. Parallel and Serial Interface Setup In “classic” mode, the parallel interface is selected by having D7 low (logic “0”) at power up. In some applications the port driving this pin may be indeterminate at power up and so an alternative parallel select Pin 18 is provided. If either of the two serial/parallel select pins are held to ground on start up, then parallel mode is selected. Both pins must be left high to select serial data. 8 bit data is selected when using the 8 bit IBM character set, otherwise the 8th data bit is ignored. In Serial mode, 8 bit data is selected when using the 8 bit IBM character set, otherwise 7 data bits are assumed. Busy Output Signal The controller asserts the Busy output (Pin 21 = logic “1”, +5V) when the input buffer is one character away from being full. The following character will, however, be loaded into the input buffer. This avoids any data being lost due to the host not responding to the busy signal immediately (such as with a double-buffered UART in a PC). /Attachment: Appendix (Schematic) A104C Users’ Guide Page 7 of 8 A104C Users’ Guide Page 8 of 8