ICS650-40A ETHERNET SWITCH CLOCK SOURCE Description Features The ICS650-40A is a clock chip designed for use as a core clock in Ethernet Switch applications. Using ICS’ patented Phase-Locked Loop (PLL) techniques, the device takes a 25 MHz crystal input and produces various output clock frequencies as listed in Output Select Table. • • • • • • Packaged in 16-pin TSSOP Operating voltage of 3.3 V Low power consumption Input frequency of 25 MHz Low long-term jitter Separate supply voltage for clock outputs (2.5 / 3.3 V clock outputs) • OE control capability Block Diagram VDD 2 S1:S0 2 VDDOA VDDOB Control Logic CLKB Phase Lock Loop CLKA CLKA X1/ICLK 25 MHz crystal or clock X2 Clock Buffer/ Crystal Oscillator Optional tuning crystal capacitors OE GND 1 MDS 650-40A B I n t e gra te d C i r c u i t S y s t e m s 4 ● 525 Race Street, San Jose, CA 951 26 121004 ● tel (408 ) 297 -1201 ● w w w. i c s t . c o m ICS650-40A ETHERNET SWITCH CLOCK SOURCE Pin Assignment Output Select Table (MHz) X1/ICLK 1 16 X2 VDD 2 15 VDD GNDA 3 14 OE VDDOA 4 13 GND CLKA 5 12 VDDOB CLKA 6 11 CLKB GNDA 7 10 GNDB S1 8 9 S1 S0 CLKA (MHz) CLKA (MHz) CLKB (MHz) 0 0 127 127 157 0 1 133 133 189 1 0 157 157 127 1 1 189 189 133 S0 16-pin (173 mil) TSSOP Pin Descriptions Pin Number Pin Name Pin Type Pin Description 1 X1/ICLK Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock. 2 VDD Power Connect to +3.3 V. 3 GNDA Power Connect to ground. 4 VDDOA Power Connect to +2.5 V or +3.3 V. For CLKA outputs only. 5 CLKA Output Clock A output with weak pull-down resistor. 6 CLKA Output Clock A output with weak pull-down resistor. 7 GNDA Power Connect to ground. 8 S1 Input Select pin 1. 9 S0 Input Select pin 0. 10 GNDB Power Connect to ground. 11 CLKB Output Clock B output with weak pull-down resistor. 12 VDDOB Power Connect to +2.5 V or 3.3 V. For clock output B only. 13 GND Power Connect to ground. 14 OE Input Output enable tri-states outputs and device is not shut down. This input has internal pull-up resistor. OE = 1 enables outputs A and B and OE=0 disables outputs A and B. When disabled the pull-down resistor pulls the outputs to GND. 15 VDD Power Connect to +3.3 V. 16 X2 Output Crystal connection. Leave unconnected for clock input. 2 MDS 650-40A B In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121004 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS650-40A ETHERNET SWITCH CLOCK SOURCE External Components A minimum number of external components are required for proper operation. Decoupling capacitors of 0.01 µF should be connected between VDD and GND pairs. The capacitors should be placed between pins VDD and GND, VDDOA and GND, and VDDOB and GND as close to the device as possible. A 33Ω series terminating resistor should be used on each clock output if the trace is longer than 1 inch. A 25 MHz fundamental mode parallel resonant crystal should be used with CL=18 pF. On chip capacitors. On Chip capacitors are used for a 18 pF load crystal. Small, 2-3 pF trimming capacitors are used from pins X1 to ground and X2 to ground to optimize the initial accuracy. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS650-40A. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5 V to VDD+0.5 V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 125°C Soldering Temperature 260°C Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Power Supply Voltage (measured in respect to GND) Max. Units 0 +70 °C +3.15 +3.45 V 3 MDS 650-40A B In te grated Circuit Systems Typ. ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121004 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS650-40A ETHERNET SWITCH CLOCK SOURCE DC Electrical Characteristics VDD=3.3 V ±5%, VDDOA = VDDOB= 3.3 V ±5% Ambient Temperature 0 to +70°C Parameter Symbol Operating Voltage Conditions Min. Typ. Max. Units VDD 3.15 3.45 V Output Operating Voltage VDDOA,B 2.375 3.45 V Input High Voltage, ICLK VIH Note 1 Input Low Voltage, ICLK VIL Note 1 Input High Voltage, S1:S0:OE VIH Input Low Voltage, S1:S0:OE VIL Output High Voltage VOH IOH = -12 mA, 3.3 V VDDO Output Low Voltage VOL IOL = 12 mA, 3.3 V VDDO Operating Supply Current IDD IDD at Output Disable Condition(OE low) VDD/2+0.5 V VDD/2-0.5 2 V VDD V 0.8 V 2.0 V 0.4 V No load 40 mA No load 16 mA Short Circuit Current IOS Each output ±70 mA Internal Pull-up Resistor RPU OE pin 300 kΩ Internal Pull-down Resistor RPD CLK outputs 300 kΩ Note: 1. Nominal switching threshold is VDD/2. AC Electrical Characteristics VDD=3.3 V ±5%, VDDOA = VDDOB = 3.3 V ±5%, CL=10 pF Ambient Temperature 0 to +70° C Parameter Symbol Conditions Min. Input Frequency Typ. Max. Units 25 MHz Output Rise Time tOR 20% to 80% of VDD 0.6 ns Output Fall Time tOF 80% to 20% of VDD 0.6 ns Output Clock Duty Cycle At VDD/2 Frequency Error All clocks 40 49-51 60 0 % ppm Output to Output Skew between clocks of the same frequency 250 ps Absolute Jitter, Short-term P-P Variation from mean ±120 ps Absolute Jitter, Short-term C-C Variation from mean ±120 ps Long-term Jitter 1000 clock cycles 600 ps 4 MDS 650-40A B In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121004 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS650-40A ETHERNET SWITCH CLOCK SOURCE Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Conditions Min. Typ. Max. Units θJA Still air 78 °C/W θJA 1 m/s air flow 70 °C/W θJA 3 m/s air flow 68 °C/W 37 °C/W θJC Marking Diagram 16 9 ICS 650G-40A ###### YYWW$$ 1 8 Notes: 1. ###### is the lot code. 2. YYWW is the last two digits of the year, and the week number that the part was assembled. 5 MDS 650-40A B In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121004 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m ICS650-40A ETHERNET SWITCH CLOCK SOURCE Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol Index Area E1 E IN D EX AR EA 1 E A A1 A2 b C D E E1 e L α aaa H 2 Pin 1 DD A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c A -C - a c e e b b S E A T IN G P LA N E L L aaa C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS650G-40A See Page 6 Tubes 16-pin TSSOP 0 to +70° C Tape and Reel 16-pin TSSOP 0 to +70° C ICS650G-40AT While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 650-40A B In te grated Circuit Systems ● 525 Ra ce Street, San Jose, CA 9512 6 Revision 121004 ● tel (4 08) 297-1 201 ● w w w. i c s t . c o m