ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83947I is a low skew, 1-to-9 LVCMOS Fanout Buffer and a member of the HiPerClockS™ HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 9 to 18 by utilizing the ability of the outputs to drive two series terminated lines. • 9 LVCMOS/LVTTL outputs Guaranteed output and part-to-part skew characteristics make the ICS83947I ideal for high performance, single ended applications that also require a limited output voltage. • 3.3V operating supply ICS • Selectable CLK0 and CLK1 can accept the following input levels: LVCMOS and LVTTL • Maximum output frequency: 110MHz • Output skew: 500ps (maximum) • Part-to-part skew: 2ns (maximum) • -40°C to 85°C ambient operating temperature • Lead-Free package available • Pin compatible with the MPC947 BLOCK DIAGRAM PIN ASSIGNMENT GND 32 31 30 29 28 27 26 25 Q0 Q1 CLK_SEL Q2 1 VDDO CLK1 Q1 0 GND CLK0 Q0 Q LE VDDO GND D CLK_EN Q2 Q3 Q4 Q5 GND 1 24 GND CLK_SEL 2 23 Q3 CLK0 3 22 VDDO CLK1 4 21 Q4 CLK_EN 5 20 GND OE 6 19 Q5 VDD 7 18 VDDO GND 8 17 GND ICS83947I 9 10 11 12 13 14 15 16 GND Q6 VDDO Q7 GND Q8 Q7 VDDO GND Q6 Q8 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View OE 83947AYI http://www.icst.com/products/hiperclocks.html 1 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 8, 9, 12, 16, 17, 20, 24, 25, 29, 32 GND Power 2 CLK_SEL Input 3, 4 CLK0, CLK1 Input 5 CLK_EN Input Pullup Clock enable. LVCMOS / LVTTL interface levels. 6 OE Input Pullup Output enable. LVCMOS / LVTTL interface levels. 7 VDD Power Power supply ground. Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels. Pullup Reference clock inputs. LVCMOS / LVTTL interface levels. Pullup Coree supply pin. 10, 14, 18, 22, 27, 31 VDDO Power Output supply pins. Q0 thru Q8 clock outputs. 11, 13, 15, 19, 21, Q8, Q7, Q6, Q5, Output 23, 26, 28, 30 Q4, Q3, Q2, Q1, Q0 LVCMOS / LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance C PD Test Conditions TABLE 3. OUTPUT ENABLE AND Control Inputs 83947AYI Minimum Typical Maximum 4 pF 25 pF 51 KΩ 51 5 Units 7 KΩ 12 Ω CLOCK ENABLE FUNCTION TABLE Output OE CLK_EN Q0:Q8 0 X Hi-Z 1 0 LOW 1 1 Follows CLK input http://www.icst.com/products/hiperclocks.html 2 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Coret Supply Voltage 3.0 3.3 3.6 V VDDO Output Supply Voltage 3.0 3.3 3.6 V IDD Input Supply Current 33 50 mA Maximum Units 3.6 V 0.8 V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIN Input Current VOH Output High Voltage IOH = -20mA VOL Output Low Voltage IOL = 20mA 83947AYI Minimum 2 CLK0, CLK1, CLK_SEL, OE, CLK_EN -100 µA 2.5 V http://www.icst.com/products/hiperclocks.html 3 Typical 0.4 V REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency Test Conditions Minimum 110 CLK to Q 1.8 Typical Maximum Units MHz 4.5 ns tPD Propagation Delay, NOTE 1 tsk(o) Output Skew; NOTE 2, 5 Measured on rising edge @VDDO/2 500 ps tsk(pp) Par t-to-Par t Skew; NOTE 3, 5 Measured on rising edge @VDDO/2 2 ns t PW Output Pulse Width tPeriod/2 + 800 ps tS tH tZL, tZH Clock Enable Setup Time; NOTE 6 Clock Enable Hold Time; NOTE 6 Output Enable Time; NOTE 4 11 ns ns ns tLZ, tHZ Output Disable Time; NOTE 4 11 ns tR Output Rise Time 1 ns tPeriod/2 - 800 CLK_EN to CLK CLK_EN to CLK 0.8V to 2.0V 0 1 0.2 Output Fall Time 0.8V to 2.0V 0.2 1 tF All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 4: These parameters are guaranteed by characterization. Not tested in production. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. 83947AYI http://www.icst.com/products/hiperclocks.html 4 ns REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V ± 0.15V SCOPE V DD V DDO Qx 2 Qx LVCMOS V DDO Qy GND 2 t sk(o) -1.65V ± 0.15V 3.3V OUTPUT LOAD AC TEST CIRCUIT PART 1 OUTPUT SKEW VDD 2 V DDO Qx CLK0, CLK1 2 VDDO 2 V PART 2 DDO Qy Q0:Q8 2 t sk(pp) t PD PROPAGATION DELAY PART-TO-PART SKEW V DDO 2 Q0:Q8 2V 2V Pulse Width t Clock Outputs PERIOD 0.8V 0.8V tR tF odc = t PW t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD OUTPUT RISE/FALL TIME 83947AYI http://www.icst.com/products/hiperclocks.html 5 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W 200 500 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83947I is: 1040 83947AYI http://www.icst.com/products/hiperclocks.html 6 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 83947AYI http://www.icst.com/products/hiperclocks.html 7 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS83947AYI ICS83947AYI 32 Lead LQFP 250 per tray -40°C to 85°C ICS83947AYIT ICS83947AYI 1000 -40°C to 85°C ICS83947AYILN ICS3947AYIN 250 per tray -40°C to 85°C ICS83947AYILNT ICS3947AYIN 32 Lead LQFP on Tape and Reel 32 Lead "Lead-Free/Annealed" LQFP 32 Lead "Lead-Free/Annealed" LQFP on Tape and Reel 1000 -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83947AYI http://www.icst.com/products/hiperclocks.html 8 REV. B OCTOBER 11, 2004 ICS83947I Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-9 LVCMOS FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page A T5 4 T2 1 2 T8 8 B 83947AYI Description of Change AC Characterisitics Table, tS and tH rows- revised Test Conditions to read CLK_EN to CLK. Added Lead Free bullet in Features section. Pin Characteristics Table - changed CIN from 4pF max. to 4pF min. ROUT added 5Ω min and 12Ω max. Ordering Information Table - add Lead-Free par t. Updated format throughout data sheet. http://www.icst.com/products/hiperclocks.html 9 Date 6/21/02 10/11/04 REV. B OCTOBER 11, 2004