ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVTTL Fanout Buffer and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS83948I-147 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The effective fanout can be increased from 12 to 24 by utilizing the ability of the outputs to drive two series terminated lines. • Twelve LVCMOS/LVTTL outputs ICS • Selectable LVCMOS/LVTTL clock or differential CLK, nCLK inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL • Output frequency: 350MHz (maximum) • Output skew (at 3.3V ± 5%): 100ps (maximum) • Part-to-part skew (at 3.3V ± 5%): 1ns (maximum) The ICS83948I-147 is characterized at full 3.3V or full 2.5V operating supply modes. Guaranteed output and part-to-part skew characteristics make the ICS83948I-147 ideal for those clock distribution applications demanding well defined performance and repeatability. • Full 3.3V or full 2.5V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages BLOCK DIAGRAM PIN ASSIGNMENT Q3 32 31 30 29 28 27 26 25 Q0 Q1 CLK_SEL VDDO 0 Q2 CLK nCLK GND 1 Q1 LVCMOS_CLK VDDO Q LE Q0 GND D CLK_EN Q2 Q3 Q4 CLK_SEL 1 24 GND LVCMOS_CLK 2 23 Q4 CLK 3 22 VDDO nCLK 4 21 Q5 CLK_EN 5 20 GND OE 6 19 Q6 VDD 7 18 VDDO GND 8 17 Q7 Q5 ICS83948I-147 9 10 11 12 13 14 15 16 GND Q8 VDDO Q9 GND Q10 Q7 VDDO Q11 Q6 Q8 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View Q9 Q10 Q11 OE 83948AYI-147 www.icst.com/products/hiperclocks.html 1 REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 CLK_SEL Input Pullup 2 LVCMOS_CLK Input Pullup Description Clock select input. Selects LVCMOS_CLK input when HIGH. Selects CLK, nCLK inputs when LOW. LVCMOS/LVTTL interface levels Clock input. LVCMOS/LVTTL interface levels. 3 CLK Input Pullup Non-inver ting differential clock input. 4 nCLK Input 5 CLK_EN Input Pulldown Inver ting differential clock input. Pullup Pullup Clock enable. LVCMOS/ LVTTL interface levels. 6 OE Input 7 8, 12, 16, 20, 24, 28, 32 9, 11, 13, 15, 17, 19, 21, 23 25, 27, 29, 31 10, 14, 18, 22, 26, 30 VDD Power Power supply pin. Output enable. LVCMOS/LVTTL interface levels. GND Power Power supply ground. Q11, Q10, Q9, Q8, Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0 Output Clock outputs. LVCMOS/LVTTL interface levels. VDDO Power Output supply pins. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN 4 pF 12 pF RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ ROUT Output Impedance CPD Test Conditions Minimum 5 Typical Maximum 7 12 Units Ω TABLE 3A. CLOCK SELECT FUNCTION TABLE Control Input Clock 0 CLK, nCLK inputs selected 1 LVCMOS_CLK input selected TABLE 3B. CLOCK INPUT FUNCTION TABLE Inputs Outputs CLK_SEL LVCMOS_CLK CLK nCLK Q0:Q11 0 — 0 1 LOW Input to Output Mode Polarity Differential to Single Ended Non Inver ting 0 — 1 0 HIGH Differential to Single Ended Non Inver ting 0 — 0 Biased; NOTE 1 LOW Single Ended to Single Ended Non Inver ting 0 — 1 Biased; NOTE 1 HIGH Single Ended to Single Ended Non Inver ting 0 — Biased; NOTE 1 0 HIGH Single Ended to Single Ended Inver ting 0 — Biased; NOTE 1 1 LOW Single Ended to Single Ended Inver ting 1 0 — — LOW Single Ended to Single Ended Non Inver ting 1 1 — — HIGH Single Ended to Single Ended Non Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 83948AYI-147 www.icst.com/products/hiperclocks.html 2 REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDDO + 0.5V Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Supply Voltage 3.135 3.3 3.465 V IDD Power Supply Current 55 mA TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 2.375 2.5 2.625 V VDDO Output Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 52 mA TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter Maximum Units VIH Input High Voltage LVCMOS Test Conditions Minimum 2 Typical VDD + 0.3 V VIL Input Low Voltage LVCMOS -0.3 0.8 V IIN Input Current 300 µA VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VIN = VDD or VIN = GND IOH = -24mA 2.4 IOL = 24mA 0.55 IOL = 12mA 0.30 V 1.3 V VDD - 0.85 V VPP Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2. See Parameter Measurement section, "3.3V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. 83948AYI-147 www.icst.com/products/hiperclocks.html 3 V V REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter Test Conditions Minimum Typical Maximum Units VIH Input High Voltage LVCMOS 1.7 VDD + 0.3 V VIL Input Low Voltage LVCMOS -0.3 0.7 V IIN Input Current 300 µA VOH Output High Voltage; NOTE 1 IOH = -15mA VOL Output Low Voltage; NOTE 1 IOL = 15mA VIN = VDD or VIN = GND 1.8 V Peak-to-Peak Input Voltage CLK, nCLK 0.15 Input Common Mode Voltage; VCMR CLK, nCLK GND + 0.5 NOTE 2, 3 NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2. See Parameter Measurement section, "2.5V Output Load AC Test Circuit". NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 3: Common mode voltage is defined as VIH. VPP 0.6 V 1.3 V VDD - 0.85 V Maximum 350 Units MHz TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = -40° TO 85° Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum Typical ƒ≤ 350MHz 2 4 ns ƒ≤ 350MHz 2 4 ns t sk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 100 ps t sk(pp) Par t-to-Par t Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 1 ns tR / tF Output Rise/Fall Time 1.0 ns odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 0.8V to 2V 0.2 ƒ≤ 150MHz, Ref = CLK, nCLK 45 55 % 5 ns Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK tS Setup Time; CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns tPLZ, tPHZ 83948AYI-147 www.icst.com/products/hiperclocks.html 4 50 ns ns ns ns REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85° Symbol Parameter fMAX Output Frequency tPD Propagation Delay; CLK, nCLK; NOTE 1 LVCMOS_CLK; NOTE 2 Test Conditions Minimum f ≤ 350MHz f ≤ 350MHz Typical Maximum 350 Units MHz 1.5 4.2 ns 1.7 4.4 ns tsk(o) Output Skew; NOTE 3, 7 Measured on rising edge @VDDO/2 160 ps tsk(pp) Par t-to-Par t Skew; NOTE 4, 7 Measured on rising edge @VDDO/2 2 ns tR / tF Output Rise/Fall Time odc Output Duty Cycle tPZL, tPZH Output Enable Time; NOTE 5 0.6V to 1.8V 0.1 1.0 ns ƒ≤ 150MHz, Ref = CLK, nCLK 40 60 % 5 ns Output Disable Time; NOTE 5 5 CLK_EN to 1 Clock Enable CLK, nCLK tS Setup Time; CLK_EN to NOTE 6 0 LVCMOS_CLK CLK, nCLK to 0 Clock Enable CLK_EN tH Hold Time; LVCMOS_CLK NOTE 6 1 to CLK_EN NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output. NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2. NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2. NOTE 5: These parameters are guaranteed by characterization. Not tested in production. NOTE 6: Setup and Hold times are relative to the rising edge of the input clock. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65. ns tPLZ, tPHZ 83948AYI-147 www.icst.com/products/hiperclocks.html 5 ns ns ns ns REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 1.65V ± 5% 1.25V±5% SCOPE VDD, VDDO Qx LVCMOS SCOPE VDD, VDDO Qx LVCMOS GND GND -1.65V ± 5% -1.25V±5% 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT VDD V DDO Qx nCLK V V Cross Points PP 2 CMR V CLK DDO Qy 2 tsk(o) GND DIFFERENTIAL INPUT LEVEL OUTPUT SKEW V DDO PART 1 V DDO Qx 2 Q0:Q11 2 t PW t PART 2 PERIOD V DDO Qy 2 tsk(pp) odc = VDD 2 2V 2V LVCMOS_CLK Clock Outputs VDD = VDDO = 3.3V 0.8V tR x 100% t PERIOD odc & tPERIOD PART-TO-PART SKEW t PW 0.8V nCLK tF CLK 1.8V Clock Outputs VDD = VDDO = 2.5V 0.6V tR 0.6V tF OUTPUT RISE/FALL TIME 83948AYI-147 VDDO 2 Q0:Q11 ➤ 1.8V t PD ➤ PROPAGATION DELAY www.icst.com/products/hiperclocks.html 6 REV. B NOVEMBER 21, 2005 Integrated Circuit Systems, Inc. ICS83948I-147 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS OUTPUT: All unused LVCMOS output can be left floating. We recommend that there is no trace attached. CLK INPUT: For applications not requiring the use of a clock input, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the CLK input to ground. CLK/nCLK INPUT: For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from CLK to ground. LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. 83948AYI-147 www.icst.com/products/hiperclocks.html 7 REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83948I-147 is: 1040 Pin compatible with the MPC9448 83948AYI-147 www.icst.com/products/hiperclocks.html 8 REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP TABLE 7. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 0.75 θ 0° -- 7° ccc -- -- 0.10 REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-026 83948AYI-147 www.icst.com/products/hiperclocks.html 9 REV. B NOVEMBER 21, 2005 ICS83948I-147 Integrated Circuit Systems, Inc. LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83948AYI-147 ICS83948AI147 ICS83948AYI-147T ICS83948AI147 32 Lead LQFP tray -40°C to 85°C 32 Lead LQFP 1000 tape & reel -40°C to 85°C ICS83948AYI-147LF ICS948AI147L 32 Lead "Lead-Free" LQFP tray -40°C to 85°C ICS83948AYI-147LFT ICS948AI147L 32 Lead "Lead-Free" LQFP 1000 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83948AYI-147 www.icst.com/products/hiperclocks.html 10 REV. B NOVEMBER 21, 2005 Integrated Circuit Systems, Inc. ICS83948I-147 LOW SKEW, 1-TO-12 DIFFERENTIAL-TO-LVCMOS/LVTTL FANOUT BUFFER REVISION HISTORY SHEET Rev Table T2 B 7 T8 83948AYI-147 Page 1 2 10 Description of Change Features Sectiton - added Lead-Free bullet. Pin Chararcteristics Table - changed CIN from 4pF max. to 4pF typical; and added 5Ω min. and 12Ω max to ROUT. Updated Single Ended Signal Driving Differential Input diagram Added Recommendations for Unused Input and Output Pins. Ordering Information Table - added lead-free par t number, marking, and note. www.icst.com/products/hiperclocks.html 11 Date 11/21/05 REV. B NOVEMBER 21, 2005