PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843003I-01 is a 3 differential output LVPECL Synthesizer designed to generate HiPerClockS™ Ethernet reference clock frequencies and is a member of the HiPerClocks™ family of high performance clock solutions from ICS. Using a 19.53125MHz or 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003I-01 has 2 output banks, Bank A with 1 differential LVPECL output pair and Bank B with 2 differential LVPECL output pairs. • Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs ICS • Using a 19.53125MHz or 25MHz crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • VCO range: 490MHz to 680MHz • RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.53ps (typical) • 3.3V output supply mode The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843003I-01 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical r ms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003I-01 is packaged in a small 24-pin TSSOP package. • -40°C to 85°C ambient operating temperature PIN ASSIGNMENT DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 CLK_ENB CLK_ENA FB_DIV VCCA VCC DIV_SELA0 BLOCK DIAGRAM VCO_SEL 24 23 22 21 20 19 18 17 16 15 14 13 DIV_SELB1 VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1 ICS843003I-01 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View CLK_ENA Pullup DIV_SELA[1:0] 1 2 3 4 5 6 7 8 9 10 11 12 Pullup Pullup QA0 TEST_CLK Pulldown 0 XTAL_IN OSC 1 0 Phase Detector VCO 00 01 10 11 ÷1 ÷2 ÷3 ÷4 (default) 00 01 10 11 ÷2 ÷4 ÷5 ÷8 (default) nQA0 1 XTAL_OUT XTAL_SEL Pullup QB0 FB_DIV 0 = ÷25 (default) 1 = ÷32 FB_DIV Pulldown DIV_SELB[1:0] MR nQB0 QB1 nQB1 Pullup Pulldown CLK_ENB Pullup The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843003AGI-01 www.icst.com/products/hiperclocks.html REV. A MAY 26, 2005 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1 24 Name DIV_SELB0 DIV_SELB1 Type 2 VCO_SEL Input 3 MR Input 4 VCCO_A Power 5, 6 QA0, nQA0 Ouput 7 CLK_ENB Input Pullup 8 CLK_ENA Input Pullup 9 FB_DIV Input Pulldown 10 VCCA Power 11 12 13 14 VCC DIV_SELA0 DIV_SELA1 VEE Power 15, 16 XTAL_OUT, XTAL_IN Input 17 TEST_CLK Input 18 XTAL_SEL Input 19, 20 nQB1, QB1 Output 21, 22 nQB0, QB0 Output Input Input Power Description Division select pin for Bank B. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. VCO select pin. When Low, the PLL is bypassed and the crystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the Pullup output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Output supply pin for Bank A outputs. Differential output pair. LVPECL interface levels. Synchronizing clock enable for Bank B outputs. Active High output enable. When logic HIGH, the output pair in Bank B is enabled. When logic LOW, the QB outputs are LOW and nQB outputs are HIGH. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Figure 1. Synchronizing clock enable for Bank A outputs. Active High output enable. When logic HIGH, the output pair in Bank A is enabled. When logic LOW, the QA output is LOW and nQA output is HIGH. Has an internal pullup resistor so the default power-up state of output is enabled. LVCMOS/LVTTL interface levels. See Figure 1. Feedback divide select. When Low (default), the feedback divider is set for ÷25. When HIGH, the feedback divider is set for ÷32. LVCMOS/LVTTL interface levels. Analog supply pin. Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Negative supply pin. Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a single-ended reference clock. Single-ended reference clock input. Has an internal pulldown resistor to pull Pulldown to low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended TEST_CLK or crystal Pullup interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Power Output supply pin for Bank B outputs. 23 VCCO_B NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ 843003AGI-01 Test Conditions Minimum www.icst.com/products/hiperclocks.html 2 Typical Maximum Units REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3A. BANK A FREQUENCY TABLE 25 0 0 0 25 1 25 QA0/nQA0 Output Frequency (MHz) 625 25 0 0 1 25 2 12.5 312.5 Inputs Crystal Frequency (MHz) FB_DIV DIV_SELA1 DIV_SELA0 Feedback Divider Bank A Output Divider M/N Multiplication Factor 20 0 0 1 25 2 12.500 250 22.5 0 1 0 25 3 8.333 187.5 25 0 1 1 25 4 6.25 156.25 24 0 1 1 25 4 6.25 150 20 0 1 1 25 4 6.25 125 19.44 1 0 0 32 1 32 622.08 19.44 1 0 1 32 2 16 311.04 15.625 1 0 1 32 2 16 250 18.75 1 1 0 32 3 10.667 200 19.44 1 1 1 32 4 8 155.52 18.75 1 1 1 32 4 8 150 15.625 1 1 1 32 4 8 125 Bank B Output Divider M/N Multiplication Factor TABLE 3B. BANK B FREQUENCY TABLE Crystal Frequency (MHz) FB_DIV DIV_SELB1 DIV_SELB0 Feedback Divider 25 0 0 0 25 2 12.5 QB0/nQB0 Output Frequency (MHz) 312.5 20 0 0 0 25 2 12.5 250 Inputs 25 0 0 1 25 4 6.25 156.25 24 0 0 1 25 4 6.25 150 20 0 0 1 25 4 6.25 12 5 25 0 1 0 25 5 5 125 25 0 1 1 25 8 3.125 78.125 24 0 1 1 25 8 3.125 75 20 0 1 1 25 8 3.125 62.5 19.44 1 0 0 32 2 16 311.04 15.625 1 0 0 32 2 16 250 19.44 1 0 1 32 4 8 155.52 18.75 1 0 1 32 4 8 150 15.625 1 0 1 32 4 8 12 5 15.625 1 1 0 32 5 6.4 10 0 19.44 1 1 1 32 8 4 77.76 18.75 1 1 1 32 8 4 75 15.625 1 1 1 32 8 4 62.5 843003AGI-01 www.icst.com/products/hiperclocks.html 3 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs Inputs Outputs DIV_SELA1 DIV_SELA0 QA DIV_SELB1 DIV_SELB0 QB 0 0 ÷1 0 0 ÷2 0 1 ÷2 0 1 ÷4 1 0 ÷3 1 0 ÷5 1 1 ÷4 1 1 ÷8 TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE Inputs FB_DIV Feedback Divide 0 ÷2 5 1 ÷32 Enabled Disabled TEST_CLK CLK_ENx nQA0, nQB0:nQB1 QA0, QB0:QB1 FIGURE 1. CLK_EN TIMING DIAGRAM TABLE 3E. CLK_ENA SELECT FUNCTION TABLE Inputs TABLE 3F. CLK_ENB SELECT FUNCTION TABLE Outputs Inputs Outputs CLK_ENA QA0 nQA0 CLK_ENB QB0:QB1 nQB0:nQB1 0 LOW HIGH 0 LOW HIGH 1 Active Active 1 Active Active 843003AGI-01 www.icst.com/products/hiperclocks.html 4 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_A, B Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 121 mA ICCA Analog Supply Current 15 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH IIL Input High Current Input Low Current Test Conditions Minimum Typical 2 -0.3 TEST_CLK, MR, FB_DIV DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB TEST_CLK, MR, FB_DIV DIV_SELA0, DIV_SELA1, DIV_SELB0, DIV_SELB1, VCO_SEL, XTAL_SEL, CLK_ENA, CLK_ENB Maximum Units VCC + 0.3 V 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA VCC = 3.465V, VIN = 0V -5 µA VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum Typical Maximum Units VCCO - 1.4 VCCO - 0.9 V VCCO - 2.0 VCCO - 1.7 V 0.6 1. 0 V NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. 843003AGI-01 www.icst.com/products/hiperclocks.html 5 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Frequency Typical Maximum Units Fundamental FB_DIV = ÷25 19.6 27.2 MHz FB_DIV = ÷32 15.313 21.25 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCA = VCCO_A = VCCO_B = 3.3V±5%, TA = -40°C TO 85°C Symbol fOUT Parameter Output Frequency Range tsk(b) Bank Skew, NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tjit(Ø) RMS Phase Jitter (Random); NOTE 3 t R / tF Output Rise/Fall Time Test Conditions Minimum Typical Output Divider = ÷1 490 680 MHz Output Divider = ÷2 245 340 MHz Output Divider = ÷3 163.33 226.67 MHz Output Divider = ÷4 122.5 170 MHz Output Divider = ÷5 98 136 MHz Output Divider = ÷8 61.25 85 MHz TBD ps Outputs @ Same Frequency TBD ps Outputs @ Different Frequencies TBD ps 625MHz (1.875MHz - 20MHz) 0.43 ps 312.5MHz (1.875MHz - 20MHz) 0.51 ps 156.25MHz (1.875MHz - 20MHz) 0.53 ps 125MHz (1.875MHz - 20MHz) 0.48 ps 20% to 80% 400 ps odc Output Duty Cycle 50 NOTE 1: Defined as skew winthin a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 843003AGI-01 www.icst.com/products/hiperclocks.html 6 % REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE AT 156.25MHZ ➤ 10Gb Ethernet Filter 156.25MHz RMS Phase Jitter (Random) 1.875Mhz to 20MHz = 0.53ps (typical) Raw Phase Noise Data -110 -120 -130 -140 ➤ -150 -160 -170 -180 -190 ➤ NOISE POWER dBc Hz 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 Phase Noise Result by adding 10Gb Ethernet Filter to raw data 1k 10k 100k 1M 10M 100M OFFSET FREQUENCY (HZ) 843003AGI-01 www.icst.com/products/hiperclocks.html 7 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot SCOPE Noise Power Qx V CC , VCCA, VCCO_A. _B LVPECL Phase Noise Mask nQx VEE f1 -1.3V±0.165V Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT nQA0, nQB0, nQB1 nQx QA0, QB0, QB1 Qx t PW t nQy Qy odc = tsk(o) PERIOD t PW x 100% t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD nQB0 80% 80% QB0 VSW I N G Clock Outputs nQB1 20% 20% tR tF QB1 tsk(b) BANK SKEW 843003AGI-01 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 8 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843003I-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCOx should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10 Ω VCCA .01μF 10μF FIGURE 2. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843003I-01 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 19.53125MHz or XTAL_OUT C1 22p X1 18pF Parallel Crystal XTAL_IN C2 22p ICS843003I-01 Figure 3. CRYSTAL INPUt INTERFACE 843003AGI-01 www.icst.com/products/hiperclocks.html 9 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 843003AGI-01 125Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 10 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65°C/W 62°C/W TRANSISTOR COUNT The transistor count for ICS843003I-01 is: 3822 843003AGI-01 www.icst.com/products/hiperclocks.html 11 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 24 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 24 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843003AGI-01 www.icst.com/products/hiperclocks.html 12 REV. A MAY 26, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS843003I-01 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843003AGI-01 ICS843003AI01 24 Lead TSSOP tube -40°C to 85°C ICS843003AGI-01T ICS843003AI01 24 Lead 2500 tape & reel -40°C to 85°C The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843003AGI-01 www.icst.com/products/hiperclocks.html 13 REV. A MAY 26, 2005