ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER General Description Features The ICS843003 is a 3 differential output LVPECL Synthesizer designed to generate Ethernet referHiPerClockS™ ence clock frequencies and is a member of the HiPerClocks™family of high performance clock solutions from IDT. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of 4 frequency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 843003 has 2 output banks, Bank A with 1 differential LVPECL output pair and Bank B with 2 differential LVPECL output pairs. • Three 3.3V LVPECL outputs on two banks, A Bank with one LVPECL pair and B Bank with 2 LVPECL output pairs • Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • • VCO range: 560MHz – 700MHz ICS Offset Noise Power 100Hz ................ -96.8 dBc/Hz 1kHz .................. -119.1 dBc/Hz 10kHz ................ -126.4 dBc/Hz 100kHz .............. -127.0 dBc/Hz The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843003 uses IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843003 is packaged in a small 24-pin TSSOP package. • • • • Pin Assignment DIV_SELB0 VCO_SEL MR VCCO_A QA0 nQA0 OEB OEA FB_DIV VCCA VCC DIV_SELA0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz): 0.51ps (typical) DIV_SELB1 VCCO_B QB0 nQB0 QB1 nQB1 XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT VEE DIV_SELA1 Full 3.3V supply mode 0°C to 70°C ambient operating temperature Industrial temperature available upon request Available in both standard (RoHS 5) and lead-free (RoHS 6) packages ICS843003 24-Lead TSSOP 4.4mm x 7.8mm x 0.925mm package body G Package Block Diagram OEA Pullup DIV_SELA[1:0] Pulldown:Pullup 2 VCO_SEL Pullup QA0 TEST_CLK Pulldown 0 0 XTAL_IN OSC Phase Detector 1 VCO 625MHz 00 01 10 11 ÷1 ÷2 (default) ÷4 ÷5 00 01 10 11 ÷1 ÷2 ÷4 (default) ÷5 nQA0 1 XTAL_OUT QB0 XTAL_SEL Pullup FB_DIV 0 = ÷20 (default) 1 = ÷24 FB_DIV Pulldown DIV_SELB[1:0] Pullup:Pulldown nQB0 QB1 nQB1 2 MR Pulldown OEB Pullup IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 1 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 1. Pin Descriptions Number Name 1 DIV_SELB0 2 VCO_SEL Type Input Input Description Pulldown Division select pin for Bank B. Default = Low. LVCMOS/LVTTL interface levels. Pullup VCO select pin. When Low, the PLL is bypassed and the crystal reference or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the output dividers. Has an internal pullup resistor so the PLL is not bypassed by default. LVCMOS/LVTTL interface levels. 3 MR Input 4 VCCO_A Power Output supply pin for Bank A outputs. 5, 6 QA0, nQA0 Output Differential output pair. LVPECL interface levels. 7 OEB Input Pulldown Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inverted outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. Has an internal pulldown resistor so the power-up default state of outputs and dividers are enabled. LVCMOS/LVTTL interface levels. Pullup Output enable Bank B. Active High output enable. When logic HIGH, the output pair on Bank B is enabled. When logic LOW, the output pair drives differential Low (QB0 = Low, nQB0 = High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 8 OEA Input Pullup Output enable Bank A. Active High output enable. When logic HIGH, the 2 output pairs on Bank A are enabled. When logic LOW, the output pair drives differential Low (QA0 = Low, nQA0 = High). Has an internal pullup resistor so the default power-up state of outputs are enabled. LVCMOS/LVTTL interface levels. 9 FB_DIV Input Pulldown Feedback divide select. When Low (default), the feedback divider is set for ÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. 10 VCCA Power Analog supply pin. 11 VCC Power Core supply pin. 12 DIV_SELA0 Input Pullup 13 DIV_SELA1 Input Pulldown 14 VEE Power Negative supply pin. XTAL_OUT, XTAL_IN Input Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal circuit with a single-ended reference clock. 17 TEST_CLK Input Pulldown 18 XTAL_SEL Input Pullup 19, 20 nQB1, QB1 Output Differential output pair. LVPECL interface levels. 21, 22 nQB01, QB0 Output Differential output pair. LVPECL interface levels. 23 VCCO_B Power Output supply pin for Bank B outputs. 24 DIV_SELB1 Input 15, 16 Pullup Division select pin for Bank A. Default = HIGH. LVCMOS/LVTTL interface levels. Division select pin for Bank A. Default = Low. LVCMOS/LVTTL interface levels. Single-ended reference clock input. Has an internal pulldown resistor to pull to low state by default. Can leave floating if using the crystal interface. LVCMOS/LVTTL interface levels. Crystal select pin. Selects between the single-ended TEST_CLK or crystal interface. Has an internal pullup resistor so the crystal interface is selected by default. LVCMOS/LVTTL interface levels. Division select pin for Bank B. Default = High. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 2 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 2. Pin Characteristics Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ Function Tables Table 3A. Bank A Frequency Table Inputs FB_DIV Feedback Divider Bank A Output Divider M/N Multiplication Factor QA0/nQA0 Output Frequency (MHz) 0 0 20 1 20 625 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Bank B Output Divider M/N Multiplication Factor QBx/nQBx Output Frequency (MHz) Crystal Frequency (MHz) DIV_SELA1 DIV_SELA0 31.25 0 31.25 Table 3B. Bank B Frequency Table Inputs Crystal Frequency (MHz) DIV_SELB1 DIV_SELB0 FB_DIV Feedback Divider 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 3 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 3C. Output Bank Configuration Select Function Table Inputs Inputs DIV_SELA1 DIV_SELA0 Bank A Output Divider DIV_SELB1 DIV_SELB0 Bank B Output Divider 0 0 1 0 0 1 0 1 2 0 1 2 1 0 4 1 0 4 1 1 5 1 1 5 Table 3D. Feedback Divider Configuration Select Function Table Inputs FB_DIV Feedback Divide 0 20 1 24 Enabled Disabled TEST_CLK OEA, OEB nQA0, nQBx QA0, QBx Figure 1. OE Timing Diagram IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 4 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Rating Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO (LVPECL) Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 70°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C DC Electrical Characteristics Table 4A. Power Supply DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VCC Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 158 mA ICCA Analog Supply Current 15 mA Table 4B. LVCMOS/LVTTL DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter VIH Input High Voltage VIL IIH IIL Input Low Voltage Input High Current Input Low Current Test Conditions Minimum Typical Maximum Units 2 VCC + 0.3 V DIV_SEL[A0:A1], FB_DIV, DIV_SEL[B0:B1], OEA, OEB, VCO_SEL, XTAL_SEL, MR -0.3 0.8 V TEST_CLK -0.3 1.3 V TEST_CLK, FB_DIV, MR, DIV_SELA1, DIV_SELB0 VCC = VIN = 3.465V 150 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB1, DIV_SELA0 VCC = VIN = 3.465V 5 µA TEST_CLK, FB_DIV, MR, DIV_SELA1, DIV_SELB0 VCC = 3.465V, VIN = 0V -5 µA OEA, OEB, VCO_SEL, XTAL_SEL, DIV_SELB1, DIV_SELA0 VCC = 3.465V, VIN = 0V -150 µA IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 5 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Table 4C. LVPECL DC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Symbol Parameter Test Conditions VOH Output High Current; NOTE 1 VOL Output Low Current; NOTE 1 VSWING Peak-to-peak Output Voltage Swing Minimum Typical Maximum Units VCCO – 1.4 VCCO – 0.9 µA VCCO – 2.0 VCCO – 1.7 µA 0.6 1.0 V Maximum Units NOTE 1: Outputs termination with 50Ω to VCCO_A, _B – 2V. Table 5. Crystal Characteristics Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental FB_DIV = ÷20 28 31.25 35 MHz FB_DIV = ÷24 23.33 26.04166 29.167 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Maximum Units Frequency NOTE: Characterized using an 18pF parallel resonant crystal. AC Electrical Characteristics Table 6. AC Characteristics, VCC = VCCA = VCCO_A = VCCO_B = 3.3V ± 5%, VEE = 0V, TA = 0°C to 70°C Parameter fOUT Symbol Output Frequency tsk(b) Bank Skew, NOTE 1 tsk(o) Output Skew; NOTE 2, 4 Test Conditions Minimum DIV_SELx[1:0] = 00 560 700 MHz DIV_SELx[1:0] = 01 280 350 MHz DIV_SELx[1:0] = 10 140 175 MHz DIV_SELx[1:0] = 11 112 140 MHz 20 ps Outputs @ Same Frequency 35 ps Outputs @ Different Frequencies 100 ps 625MHz, (1.875MHz – 20MHz) tjit(Ø) RMS Phase Jitter, (Random); NOTE 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Typical 0.42 ps 312.5MHz, (1.875MHz – 20MHz) 0.50 ps 156.25MHz, (1.875MHz – 20MHz) 0.51 ps 125MHz, (1.875MHz – 20MHz) 0.52 ps 20% to 80% 250 600 ps DIV_SELx[1:0] = 00 40 60 % DIV_SELx[1:0] ≠ 00 47 53 % NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions. NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 3: Please refer to the Phase Noise Plots. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 6 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 125MHz -10 -20 ➝ 0 125MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.52ps 10Gb Ethernet Filter -30 -40 -50 -60 -80 -90 -100 -110 ➝ Noise Power dBc Hz -70 Raw Phase Noise Data -120 -130 -140 ➝ -150 -160 -170 Phase Noise Result by adding a 10Gb Ethernet filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 7 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 156.25MHz -10 -20 ➝ 0 156.25MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.51ps 10Gb Ethernet Filter -30 -40 -50 -60 -80 -90 -100 -110 ➝ Noise Power dBc Hz -70 Raw Phase Noise Data -120 -130 -140 ➝ -150 -160 -170 Phase Noise Result by adding a 10Gb Ethernet filter to raw data -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 8 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 312.5MHz -10 -20 ➝ 0 312.5MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.50ps 10Gb Ethernet Filter -30 -40 -50 -60 -80 -90 -100 ➝ Noise Power dBc Hz -70 Raw Phase Noise Data -110 -120 -130 ➝ -140 -150 -160 Phase Noise Result by adding a 10Gb Ethernet filter to raw data -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 9 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Typical Phase Noise at 625MHz -10 -20 ➝ 0 625MHz RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.42ps 10Gb Ethernet Filter -30 -40 -50 -60 dBc Hz -70 -80 -100 ➝ Noise Power -90 Raw Phase Noise Data -110 -120 -130 ➝ -140 -150 Phase Noise Result by adding a 10Gb Ethernet filter to raw data -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M Offset Frequency (Hz) IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 10 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Parameter Measurement Information 2V% nQx VCC, VCCA, VCCO_A, _B Qx SCOPE Qx nQy LVPECL Qy nQx tsk(o) VEE -1.3V ± 0.165V LVPECL Output Load AC Test Circuit Output Skew Phase Noise Plot Noise Power nQB0 QB0 Phase Noise Mask nQB1 QB1 f1 Offset Frequency tsk(b) f2 RMS Jitter = Area Under the Masked Phase Noise Plot RMS Phase Jitter Bank Skew nQA0, nQB0, nQB1 QA0, QB0, QB1 80% 80% t PW VSW I N G t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD Output Duty Cycle/Pulse Width/Period IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER Output Rise/Fall Time 11 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Application Information Power Supply Filtering Technique As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS843003 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO_x should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 2 illustrates this for a generic VCC pin and also shows that VCCA requires that an additional 10Ω resistor along with a 10µF bypass capacitor be connected to the VCCA pin. 3.3V VCC .01µF 10Ω .01µF 10µF VCCA Figure 2. Power Supply Filtering Recommendations for Unused Input and Output Pins Inputs: Outputs: Crystal Inputs LVPECL Outputs For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. TEST_CLK Input For applications not requiring the use of the test clock, it can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from the TEST_CLK to ground. LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 12 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Crystal Input Interface The ICS843003 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 3 below were determined using a 31.25MHz or 26.041666MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. XTAL_IN C1 33p X1 18pF Parallel Crystal XTAL_OUT C2 27p Figure 3. Crystal Input Interface LVCMOS to XTAL Interface The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 4. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VCC impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. VCC R1 Ro Rs 0.1µf 50Ω XTAL_IN Zo = Ro + Rs R2 XTAL_OUT Figure 4. General Diagram for LVCMOS Driver to XTAL Input Interface IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 13 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω Figure 5A. 3.3V LVPECL Output Termination IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 84Ω Figure 5B. 3.3V LVPECL Output Termination 14 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Layout Guideline Figure 6A shows a schematic example of the ICS843003. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF parallel resonant 31.25MHz crystal is used. The C1= 27pF and C2 = 33pF are recommended for frequency accuracy. The C1 and C2 may be slightly adjusted for optimizing frequency accuracy. 3.3V VCC VCCA C3 10uF C4 0.01u 12 11 10 9 8 7 6 5 4 3 2 1 RU2 Not Install To Logic Input pins To Logic Input pins U1 RD2 1K ICS843003 VCC=3.3V 3.3V R7 133 R9 133 + Zo = 50 Ohm F p 8 1 C2 33pF R6 82.5 VCCO=3.3V Zo = 50 Ohm X1 31.25MHz - R4 82.5 VCCO RD1 Not Install Zo = 50 Ohm C7 0.1u DIV_SELA0 VCC VCCA FB_DIV OEA OEB nQA0 QA0 VCCO_A MR VCO_SEL DIV_SELB0 RU1 1K Set Logic Input to '0' VDD R5 133 VCCO DIV_SELA1 VEE XTAL_OUT XTAL_IN TEST_CLK XTAL_SEL nQB1 QB1 nQB0 QB0 VCCO_B DIV_SELB1 Set Logic Input to '1' R3 133 + VCC C6 0.1u Logic Control Input Examples VDD Zo = 50 Ohm 13 14 15 16 17 18 19 20 21 22 23 24 R2 10 C8 0.1u R8 82.5 - R10 82.5 C1 27pF Figure 6A. ICS843003 Schematic Example PC Board Layout Example Figure 5B shows an example of ICS843003 P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 7. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. Figure 6B. ICS843003 PC Board Layout Example Table 7. Footprint Table Reference Size C1, C2 0402 C3 0805 C4, C5, C6, C7, C8 0603 R2 0603 NOTE: Table 7, lists component sizes shown in this layout example. IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 15 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Power Considerations This section provides information on power dissipation and junction temperature for the ICS843003. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843003 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 158mA = 547.5mW • Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 3 * 30mW = 90mW Total Power_MAX (3.3V, with all outputs switching) = 547.5mW + 90mW = 637.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 8below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.638W * 65°C/W = 111.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer). Table 8. Thermal Resitance θJA for 24 Lead TSSOP, Forced Convection θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 0 1 2.5 70°C/W 65 62 16 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. VCCO Q1 VOUT RL 50Ω VCCO - 2V Figure 7. LVPECL Driver Circuit and Termination To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of VCCO – 2V. • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCOO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – (VCCO_MAX – VOH_MAX))/RL] * (VCCO_MAX – VOH_MAX) = [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – (VCCO_MAX – VOL_MAX))/RL] * (VCCO_MAX – VOL_MAX) = [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 17 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Reliability Information Table 9. θJA vs. Air Flow Table for a 24 Lead TSSOP θJA vs. Air Flow Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 70°C/W 65 62 Transistor Count The transistor count for ICS843003 is: 3767 Package Outline and Package Dimensions Package Outline - G Suffix for 24 Lead TSSOP Table 10. Package Dimensions All Dimensions in Millimeters Symbol Minimum Maximum N 24 A 1.20 A1 0.5 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 7.90 E 6.40 Basic E1 4.30 4.50 e 0.65 Basic L 0.45 0.75 α 0° 8° aaa 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 18 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Ordering Information Table 11. Ordering Information Part/Order Number 843003AG 843003AGT 843003AGLF 843003AGLFT Marking ICS843003AG ICS843003AG ICS843003AGLF ICS843003AGLF Package 24 Lead TSSOP 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP “Lead-Free” 24 Lead TSSOP Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER 19 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Revision History Sheet Rev Table Page Features Section - added Lead-Free bullet. Added Recommendations for Unused Input and Output Pins. Ordering Information table - added Lead-Free part number, marking and note. 1/25/06 T10 1 11 17 3 14 Bank B Frequency Table - corrected table labeling. Added LVCMOS to XTAL Interface section. Updated datasheet format. 2/19/08 A T3B A Description of Change IDT™ / ICS™ LVPECL FREQUENCY SYNTHESIZER Date 20 ICS843003AG REV. A OCTOBER 23, 2008 ICS843003 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Innovate with IDT and accelerate your future networks. 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