ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8431-01 is a general purpose clock frequency synthesizer for IA64/32 application and HiPerClockS™ a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8431-01 consists of one independent low bandwidth PLL timing channel. A 16.666MHz crystal is used as the input to the on-chip oscillator. The M is configured to produce a fixed output frequency of 200MHz. • Fully integrated PLL ,&6 • Differential 3.3V LVPECL output • 200MHz output frequency • 48% to 52% duty cycle • Crystal oscillator interface • Spread Spectrum Clocking (SSC) fixed at 1/2% modulation for environments requiring ultra low EMI. Typical10dB EMI reduction can be achieved with spread spectrum modulation Programmable features of the ICS8431-01 support four operational modes. The four modes are spread spectrum clocking (SSC), non-spread spectrum clock and two test modes which are controlled by the SSC_CTL[1:0] pins. Unlike other synthesizers, the ICS8431-01 can immediately change spread-spectrum operation without having to reset the device. • LVTTL / LVCMOS control inputs • PLL bypass modes supporting in-circuit testing and on-chip functional block characterization • 28 lead SOIC In SSC mode, the output clock is modulated in order to achieve a reduction in EMI. In one of the PLL bypass test modes, the PLL is disconnected as the source to the differential output allowing an external source to be connnected to the TEST_I/O pin. This is useful for incircuit testing and allows the differential output to be driven at a lower frequency throughout the system clock tree. In the other PLL bypass mode, the oscillator divider is used as the source to both the M and the Fout divide by 2. This is useful for characterizing the oscillator and internal dividers. • RMS cycle-to-cycle jitter of 2ps • Typical cycle-to-cycle jitter of 18ps • 0° to 85°C ambiant operating temperature BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 OSC XTAL2 ÷ 16 PLL PHASE DETECTOR VCO ÷2 FOUT nFOUT ÷M nc nc nc nc nc nc nc nc nc SSC_CTL0 SSC_CTL1 VEE TEST_I/O VDD TEST_I/O SSC_CTL0 SSC_CTL1 ICS8431CM-01 SSC Control Logic www.icst.com/products/hiperclocks.html 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 nc VDDI XTAL2 XTAL1 nc nc VDDA VEE RESERVED nc VDDO FOUT nFOUT VEE ICS8431-01 28-Lead SOIC M Package Top View REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number 1-9, 19, 23, 24, 28 Name Type nc Description Unused Unused pins. 12 SSC_CTL0, SSC_CTL1 GND 13 TEST_ I/O 14, 27 VDD Power Input / Output Power 15 GND Power 16, 17 nFOUT, FOUT Output 18 VDDO Power 20 RESERVED Reserve Reserve pin. 21 VEE Power Ground pin. 10, 11 Input Pullup SSC control pins. LVTTL/LVCMOS interface levels. Ground pin for core and test output. Programmed as defined in Table 3 Function Table.. Power supply pin for core and test output. Ground pin for output. These differential outputs are main output drivers for the synthesizer. They are compatible with terminated positive referenced LVPECL logic. Power supply pin for output. 22 VDDA Power PLL power supply pin. 25, 26 XTAL1, XTAL2 Input Crystal oscillator input. 27 VDDI Power Input and core power supply pin. Connect to 3.3V. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Pin Capacitance Test Conditions Minimum Typical Maximum Units 4 pF RPULLUP Input Pullup Resistor 51 KΩ RPULLDOWN Input Pulldown Resistor 51 KΩ TABLE 3. SSC CONTROL INPUTS FUNCTION TABLE Inputs SSC_CTL1 SSC_CTL0 TEST_I/O Source SSC Outputs FOUT, TEST_I/O nFOUT fXTAL ÷ 16 fXTAL ÷ 32 ÷M 200MHz Hi-Z 0 0 Internal Disabled 0 1 PLL Enabled 1 0 External Disabled Test Clk Input 1 1 PLL Disabled 200MHz Hi-Z Operational Modes PLL bypass; Oscillator, oscillator, M and N dividers test mode. NOTE 1 Default SSC; Modulation Factor = ½ Percent Diagnostic Mode; NOTE 1 (1MHz ≤ Test Clk ≤ 200MHz) No SSC Modulation NOTE 1: Used for in house debug and characterization. ICS8431CM-01 www.icst.com/products/hiperclocks.html 2 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage Inputs Outputs Ambient Operating Temperature Storage Temperature 4.6V -0.5V to VDD + 0.5V -0.5V to VDDO + 0.5V 0°C to 85°C -65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Minimum Typical Maximum Units VDD Power Supply Voltage Test Conditions 3.135 3.3 3.465 V VDDO Output Power Supply Voltage 3.135 3.3 3.465 V VDDA Analog Power Supply Voltage 3.135 3.3 3.465 V VDDI Input Power Supply Voltage 3.135 3.3 3.465 V 140 mA IEE TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current SSC_CTL0, SSC_CTL1, TEST_I/O SSC_CTL0, SSC_CTL1, TEST_I/O SSC_CTL0, SSC_CTL1, TEST_IO SSC_CTL0, SSC_CTL1, TEST_IO Test Conditions Minimum 3.135V ≤ VDD ≤ 3.465V 3.135V ≤ VDD ≤ 3.465V Typical Maximum Units 2 VDD + 0.3 V -0.3 0.8 V 5 µA VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions VDDO - 1.28 VDDO - 0.980 V VOL Output Low Voltage; NOTE 1 VDDO - 2.0 VDDO - 1.7 V 850 mV VSWING Peak-to-Peak Output Voltage Swing Minimum 600 Typical 700 NOTE 1: Output terminated with 50Ω to VDDO - 2V. ICS8431CM-01 www.icst.com/products/hiperclocks.html 3 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental Frequency 16.666 MHz Frequency Tolerance -50 +50 ppm Frequency Stability -100 +100 ppm Drive Level 100 µW Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitiance 3 Load Capacitiance 10 Series Pin Inductance Operating Temperature Range Aging Per year @25°C 7 pF 32 pF 3 7 nH 0 70 °C -5 +5 ppm 18 TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDI = VDDO = 3.3V±5%, TA = 0°C TO 85°C, 16.666MHZ CRYSTAL Symbol Parameter Test Conditions Minimum tPERIOD Average Output Period; NOTE 2 FOUT = 200 MHz 4995 t j it(cc) Cycle-to-Cycle Jitter ; NOTE 2 FOUT = 200 MHz odc Output Duty Cycle; NOTE 2 FOUT = 200 MHz 48 tR Output Rise Time; NOTE 1, 2 20% to 80% tF Output Fall Time; NOTE 1, 2 20% to 80% Fxtal Cr ystal Input Range SSC Modulation Frequency; NOTE 1, 2 SSC Modulation Factor ; NOTE 1, 2 Spectral Reduction; NOTE 1, 2 Fm Fmf SSCred ps 30 ps 52 % 300 450 600 ps 300 450 600 ps 14 16.666 18 MHz 33.33 KHz 0.6 % 10 ms 7 4 Units 5005 0.4 www.icst.com/products/hiperclocks.html Maximum 18 30 tSTABLE Power-up to Stable Clock Output NOTE 1: Spread Spectrum clocking enabled. NOTE 2: Outputs terminated with 50Ω to VDDO - 2V. tjit(cc), tR, tF, odc conform to JEDEC JESD65 definitions. ICS8431CM-01 Typical 10 dB REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER 80% ➤ PARAMETER MEASUREMENT INFORMATION 80% Vswing 20% ➤ 20% Clock Inputs and Outputs tfall ➤ FIGURE 1 — INPUT AND ➤ trise ➤ ➤ OUTPUT SLEW RATES X_CLK, 1X_FOUT nX_CLK, n1X_FOUT ➤ tcycle ➤ n tcycle n+1 ➤ ➤ t jit(cc) = tcycle n –tcycle n+1 FIGURE 2 — CYCLE-TO-CYCLE JITTER nX_CLK, n1X_FOUT X_CLK, 1X_FOUT Pulse Width (t pw) ➤ ➤ ➤ t PERIOD odc = ➤ tpw t PERIOD FIGURE 3 — odc & t PERIOD ICS8431CM-01 www.icst.com/products/hiperclocks.html 5 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. AND OSCILLATOR INTERFACE The ICS8431-01 features an internal oscillator that uses an external quartz crystal as the source of its reference frequency. A 16.666 MHz crystal divided by 16 before being sent to the phase detector provides the reference frequency. The oscillator is a series resonant, multi-vibrator type design. This design provides better stability and eliminates the need for large on chip capacitors. Though a series resonant crystal is preferred, a parallel resonant crystal can be used. A parallel resonant mode crystal used in a series resonant circuit will exhibit a frequency of oscillation a few hundred ppm lower than specified. A few hundred ppm translates to KHz inaccuracy. In general computing applications this level of inaccuracy is irrelevant. If better ppm accuracy is required, an external capacitor can be added to a parallel resonant crystal in series to pin 25. Figure 1A shows how to interface with a crystal. ICS8431-01 XTAL2 (Pin 26, SOIC) XTAL1 (Pin 25, SOIC) Optional Quartz Crystal Selection: (1) Raltron Series Resonant: AS-16.66-S-SMD-T-MI (2) Raltron Parallel Resonant: AS-16.66-18-SMD-T-MI Figures 1A, 1B, and 1C show various crystal parameters which are recommended only as guidelines. Figure 1A shows how to interface a capacitor with a parallel resonant crystal. Figure 1B shows the capacitor value needed for the optimum PPM performance over various parallel resonant crystals. Figure 1C shows the recommended tuning capacitance for a 16.666MHz parallel resonant crystal. FIGURE 1A. CRYSTAL INTERFACE FIGURE 1C. Recommended tuning capacitance for 16.666MHz parallel resonant crystal. FIGURE 1B. Recommended tuning capacitance for various parallel resonant crystals. 16.666MHz 60 100 14.318 50 80 15.000 40 16.667 30 Frequency Accuracy (ppm) Series Capacitor, C1 (pF) ➤ CRYSTAL INPUT 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER 19.440 20.000 20 24.000 10 0 14 15 16 17 18 19 20 21 22 23 24 25 Crystal Frequency (MHz) 60 40 20 0 -20 0 10 20 30 40 50 60 -40 -60 -80 -100 Series Capacitor, C1 (pF) ICS8431CM-01 www.icst.com/products/hiperclocks.html 6 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER SPREAD SPECTRUM Spread-spectrum clocking is a frequency modulation technique for EMI reduction. When spread-spectrum is enabled, a 30KHz triangle waveform is used with 0.5% down-spread (+0.0% / -0.5%) from the nominal 200MHz clock frequency. An example of a triangle frequency modulation profile is shown in Figure 2 below. The ramp profile can be expressed as: The ICS8431-01 triangle modulation frequency deviation will not exceed 0.6% down-spread from the nominal clock frequency (+0.0% / -0.5%). An example of the amount of down spread relative to the nominal clock frequency can be seen in the frequency domain, as shown in Figure 3. The ratio of this width to the fundamental frequency is typically 0.4%, and will not exceed 0.6%. The resulting spectral reduction will be greater than 7dB, as shown in Figure 3. It is important to note the ICS8431-01 7dB minimum spectral reduction is the component-specific EMI reduction, and will not necessarily be the same as the system EMI reduction. • Fnom = Nominal Clock Frequency in Spread OFF mode (200MHz with 16.666MHz IN) • Fm = Nominal Modulation Frequency (30KHz) • δ = Modulation Factor (0.5% down spread) 1 , 2 fm (1 - δ) fnom - 2 fm x δ x fnom x t when 1 < t < 1 2 fm fm ➤ (1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t < Fnom ∆ − 10 dBm A B (1 - δ) Fnom δ = .4% ➤ 0.5/fm 1/fm FIGURE 3. 200MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN FIGURE 2. TRIANGLE FREQUENCY MODULATION (A) SPREAD-SPECTRUM OFF (B) SPREAD-SPECTRUM ON POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8431-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDI, VDDA, and VDDO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, better power supply isolation is required. Figure 4 illustrates how a 10Ω along with a 10µF and a .01µF bypass capacitor should be connected to each power supply pin. ICS8431CM-01 3.3V VDD .01µF 10Ω VDDA .01µF 10 µF FIGURE 4. POWER SUPPLY FILTERING www.icst.com/products/hiperclocks.html 7 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. TERMINATION FOR 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER PECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. There are a few simple termination schemes. Figures 5A and 5B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is typical for IA64/32 platforms. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/PECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to Zo = 50Ω 3.3V Zo = 50Ω 5 2 Zo FOUT 5 2 Zo FIN Zo = 50Ω Zo = 50Ω Zo = 50Ω Zo = 50Ω FOUT 50Ω Zo = 50Ω VCC-2V ➤ RTT 1 RTT = FIN 50Ω (VOH + VOL / VCC –2) –2 Zo = 50Ω 3 2 Zo Zo FIGURE 5A. LVPECL OUTPUT TERMINATION 3 2 Zo FIGURE 5B. LVPECL OUTPUT TERMINATION LAYOUT GUIDELINE The schematic of the ICS8431-01 layout example used in this layout guideline is shown in Figure 6A. The ICS8431-01 recommended PCB board layout for this example is shown in Figure 6B. This layout example is used as a general guideline. The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of the P.C. board. U1 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 nc nc nc nc nc nc nc nc nc SSC_CTL0 SSC_CTL1 VEE TEST_IO VDD nc VDDI XTAL2 XTAL1 nc nc VDDA VEE nc nc VDDO FOUT nFOUT VEE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 C6 0.01uF VDD Termination A X1 R5 VDDA VDD0 Termination B (not shown in the layout) 10 C3 0.01uF VDD C4 10uF IN+ R1 125 IN- Zo = 50 Ohm IN+ TL1 R3 125 8431-01 Zo = 50 Ohm C1 0.1uF R2 50 R1 50 INC2 0.1uF TL2 R2 84 R4 84 R3 50 FIGURE 6A. RECOMMENDED SCHEMATIC LAYOUT ICS8431CM-01 www.icst.com/products/hiperclocks.html 8 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signals traces. All the resistors and capacitors are size 0603. The Crystal X1 is Raltron Part # AS-16.666-18-SMD. POWER AND • The traces with 50Ω transmission lines TL1 and TL2 at FOUT and nFOUT should have equal delay and run adjacent to each other. Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. GROUNDING Place the decoupling capacitors C1, C2 and C3, C4, C5, C6 as close as possible to the power pins. If space allows, placing the decoupling capacitor at the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin generated by the via. • Keep the clock trace on same layer. Whenever possible, avoid any vias on the clock traces. Any via on the trace can affect the trace characteristic impedance and hence degrade signal quality. Maximize the pad size of the power (ground) at the decoupling capacitor. Maximize the number of vias between power (ground) and the pads. This can reduce the inductance between the power (ground) plane and the component power (ground) pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow more space between the clock trace and the other signal trace. If VDDA shares the same power supply with VDD, insert the RC filter R5, C3, and C4 in between. Place this RC filter as close to the VDDA as possible. CLOCK TRACES AND • Make sure no other signal trace is routed between the clock trace pair. The matching termination resistors R1, R2, R3 and R4 should be located as close to the receiver input pins as possible. Other termination scheme can also be used but is not shown in this example. TERMINATION The component placements, locations and orientations should be arranged to achieve the best clock signal quality. Poor clock signal quality can degrade the system performance or cause system failure. In the synchronous high-speed digital system, the clock signal is less tolerable to poor signal quality than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The trace shape and the trace delay might be restricted by the available space on the board and CRYSTAL The crystal X1 should be located as close as possible to the pins 26 (XTAL1) and 25 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. U1 ICS8431-01 GND C6 VDD X1 Signals VIA C3 C4 R5 Close to the input pins of the receiver R1 C2 R2 TL1 (50 Ohm) C1 TL2 (50 Ohm) IN+ INR3 R4 FIGURE 6B. PCB BOARD LAYOUT FOR ICS8431-01 ICS8431CM-01 www.icst.com/products/hiperclocks.html 9 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER PACKAGE OUTLINE - M SUFFIX C N 28 15 L H E 14 1 h x 45º α D A2 A e A1 SEATING PLANE B .10 (.004) TABLE 7. PACKAGE DIMENSIONS Millimeters SYMBOL MIN Inches MAX N MIN MAX 28 A -- 2.65 -- 0.104 A1 0.10 -- 0.0040 -- A2 2.05 2.55 0.081 0.100 B 0.33 0.51 0.013 0.020 C 0.18 0.32 0.007 0.013 D 17.70 18.40 0.697 0.724 E 7.40 7.60 0.291 0.299 e 1.27 BASIC 0.050 BASIC H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.029 L 0.40 1.27 0.016 0.050 α 0° 8° 0° 8° REFERENCE DOCUMENT: JEDEC PUBLICATION 95, MS-013, MO-119 ICS8431CM-01 www.icst.com/products/hiperclocks.html 10 REV. A JUNE 5, 2001 ICS8431-01 Integrated Circuit Systems, Inc. 200MHZ, LOW JITTER, LVPECL FREQUENCY SYNTHESIZER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS8431CM-01 ICS8431CM-01 28 Lead SOIC 26 Per Tube 0°C to 85°C ICS8431CM-01T ICS8431CM-01 28 Lead SOIC on Tape and Reel 1000 0°C to 85°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. ICS8431CM-01 www.icst.com/products/hiperclocks.html 11 REV. A JUNE 5, 2001