PRELIMINARY Integrated Circuit Systems, Inc. CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS84327 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for HiPerClockS™ SONET, 10 Gigabit Fibre Channel and 10 Gigabit Ethernet applications and is a member of the HiperClockS family of High Performance Clock Solutions from ICS. The output frequency can be set using the frequency select pins and a 19.44MHz crystal for SONET frequencies, or a 25MHz crystal for 10 Gigabit Ethernet frequencies, or a 25.5MHz crystal for a 10 Gigabit Fibre Channel. The low phase noise characteristics of the ICS84327 make it an ideal clock for these demanding applications. • 6 LVPECL outputs ,&6 • Crystal oscillator interface • Output frequency range: 77.76MHz to 625MHz • Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz • RMS phase jitter at 155.52MHz, using a 19.44MHz crystal (12KHz to 20MHz): 3.4ps (typical) Phase noise: Offset Noise Power 100Hz .................. -92 dBc/Hz 1KHz ................ -105 dBc/Hz 10KHz ................ -122 dBc/Hz 100KHz ................ -123 dBc/Hz FUNCTION TABLE Inputs F_XTAL ICS84327 MR SEL2 SEL1 SEL0 Output Frequency F_OUT X 1 X X X LOW 19.44MHz 0 1 0 0 77.76MHz 19.44MHz 0 1 0 1 155.52MHz 19.44MHz 0 1 1 0 311.04MHz 19.44MHz 0 1 1 1 622.08MHz 25MHz 0 0 0 0 78.125MHz 25MHz 0 0 0 1 156.25MHz 25MHz 0 0 1 0 312.5 MHz • Full 3.3V or 3.3V core, 2.5V output supply mode • 0°C to 70°C ambient operating temperature • Industrial temperature information available upon request 25MHz 0 0 1 1 625MHz 25.5MHz 0 0 0 1 159.375MHz BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 0 OSC XTAL2 1 Output Divider PLL 6 Q0:Q5 6 nQ0:nQ5 / / Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Feedback Divider 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCCO F_SEL0 F_SEL1 MR XTAL1 XTAL2 F_SEL2 VCCA VCC PLL_SEL VEE VCCO ICS84327 F_SEL2 MR PLL_SEL F_SEL1 F_SEL0 24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 84327AM www.icst.com/products/hiperclocks.html 1 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1, 2 Q0, nQ0 Type Description Output Differential output pair. LVPECL interface levels. 3, 4 Q1, nQ1 Output Differential output pair. LVPECL interface levels. 5, 6 Q2, nQ2 Output Differential output pair. LVPECL interface levels. 7, 8 Q3, nQ3 Output Differential output pair. LVPECL interface levels. 9, 10 Q4, nQ4 Output Differential output pair. LVPECL interface levels. 11, 12 Q5, nQ5 Output Differential output pair. LVPECL interface levels. 13, 24 VCCO Power Output supply pins. 16 VCC Power Core supply pin. 14 VEE 15 PLL_SEL Input Pullup 17 VCCA Power Negative supply pin. Selects between the PLL and cr ystal inputs as the input to the dividers. When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2. LVCMOS / LVTTL interface levels. Analog supply pin. Pullup Feedback frequency select pin. LVCMOS/LVTTL interface levels. 18 F_SEL2 Input 19, 20 XTAL2, XTAL1 Input 21 MR Input 22 F_SEL1 Input 23 F_SEL0 Input Cr ystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low, and the inver ted Pulldown outputs nQx to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 4 RPULLUP Input Pullup Resistor 51 RPULLDOWN Input Pulldown Resistor 51 84327AM Test Conditions www.icst.com/products/hiperclocks.html 2 Minimum Typical Maximum Units pF KW KW REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 50°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Minimum Typical Maximum Units VCC Core Supply Voltage Test Conditions 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3.3 3.465 VCCO Output Supply Voltage I EE Power Supply Current 140 mA V ICCA Analog Supply Current 20 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions PLL_SEL, MR, F_SEL0, F_SEL1 PLL_SEL, MR, F_SEL0, F_SEL1 MR, F_SEL1 PLL_SEL, F_SEL0 Minimum Typical Maximum Units 2 VCC + 0.3 V -0.3 0.8 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA MR, F_SEL1 VCC = 3.465V, VIN = 0V -5 µA PLL_SEL, F_SEL0 VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing Minimum NOTE 1: Outputs terminated with 50W to VCCO - 2V. Typical Maximum Units VCCO - 1.4 VCCO - 1.0 V VCCO - 2.0 VCCO - 1.7 V 0.6 1.0 V TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage 3.135 3.3 3.465 V VCCO Output Supply Voltage 2.375 2.5 2.625 V IEE Power Supply Current 140 mA ICCA Analog Supply Current 20 mA 84327AM www.icst.com/products/hiperclocks.html 3 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25.5 MHz Equivalent Series Resistance (ESR) Frequency 19.44 50 Ω Shunt Capacitance 7 pF Maximum Units 625 MHz 700 ps NOTE: Characterized using an 18pf parallel resonant crystal. TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Minimum Typical 77.76 30 20% to 80% 200 ps 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. % 1 ms Maximum Units 625 MHz TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V±5%, VCCO = 2.5V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency tsk(o) Output Skew; NOTE 1, 2 tR / tF Output Rise/Fall Time odc Output Duty Cycle Minimum Typical 77.76 30 20% to 80% 200 50 PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. 84327AM ps 700 www.icst.com/products/hiperclocks.html 4 ps % 1 ms REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TYPICAL PHASE NOISE 0 -10 19.44MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.4ps (typical) -30 -40 622.08MHz 311.04MHz 155.52MHz 77.76MHz -60 Z (dBc H ) PHASE NOISE -50 -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 0 -10 25MHz Input -20 RMS Phase Noise Jitter 12K to 20MHz = 3.2ps (typical) -30 625MHz 312.5MHz 156.25MHz 78.125MHz -40 Z (dBc H ) PHASE NOISE -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 10 100 1k 10k 100k 1M 10M OFFSET FREQUENCY (HZ) 84327AM www.icst.com/products/hiperclocks.html 5 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 2V 2V 2.8V+0.04V VCC, VCCA, VCCO Qx SCOPE VCC, V CCA LVPECL Qx SCOPE VCCO LVPECL V EE nQx nQx V EE -1.3V ± 0.165V -0.5V ± 0.125V 3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT 3.3V OUTPUT LOAD AC TEST CIRCUIT nQx nQ0:nQ5 Qx Q0:Q5 Pulse Width t nQy Qy odc = tsk(o) PERIOD t PW t PERIOD OUTPUT SKEW OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 80% 80% VSW I N G Clock Outputs 20% 20% tR tF OUTPUT RISE/FALL TIME 84327AM www.icst.com/products/hiperclocks.html 6 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS84327 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10µF and a .01µF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01µF 10Ω V CCA .01µF 10 µF FIGURE 1. POWER SUPPLY FILTERING TERMINATION FOR 3.3V LVPECL OUTPUT The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Zo (VOH + VOL / VCC – 2) – 2 FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 2A. LVPECL OUTPUT TERMINATION 84327AM 125Ω 84Ω FIGURE 2B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 7 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. TERMINATION FOR ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER 2.5V LVPECL OUTPUT Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very close to ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE 84327AM www.icst.com/products/hiperclocks.html 8 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER CRYSTAL INPUT INTERFACE determined using a 25MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS84327 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 4 below were 19 XTAL2 C1 18pF 25MHz X1 20 XTAL1 C2 22pF ICS84327 Figure 4. CRYSTAL INPUt INTERFACE SCHEMATIC EXAMPLE Figure 5A shows a schematic example of using an ICS84327. In this example, the input is a 25MHz parallel resonant crystal with load capacitor CL=18pF. The frequency fine tuning capacitors C1 and C2 is 22pF and 18pF respectively. This example also shows logic control input handling. The configuration is set at F_SEL[2:0]=011, therefore, the output frequency is 625MHz. It is recommended to have one decouple capacitor per power pin. Each decoupling capacitor should be located as close as possible to the power pin. The low pass filter R7, C11 and C16 for clean analog supply should also be located as close to the VCCA pin as possible. VCC U1 VCC R4 1K VCC R7 24 VCCA 22p C11 0.1u C16 10u F_SEL2 C1 X1 25MHz,18pF F_SEL1 R5 F_SEL0 1K C2 VCC Zo = 50 13 14 15 16 17 18 19 20 21 22 23 24 VCCO VEE PLL_SEL VCC VCCA F_SEL2 XTAL2 XTAL1 MR F_SEL1 F_SEL0 VCCO nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 12 11 10 9 8 7 6 5 4 3 2 1 Zo = 50 + R2 50 R1 50 R3 50 18p ICS84327 RU1 SP RU2 1K RU3 1K VCC=3.3V F_SEL2 F_SEL1 F_SEL0 RD1 1K RD2 SP RD3 SP (U1,13) VCC (U1,16) C6 0.1u e.g. F_SEL[2:0]=011 (U1,24) C5 0.1u C3 0.1u SP = Spare, Not Installed FIGURE 5A. ICS84327 SCHEMATIC EXAMPLE 84327AM www.icst.com/products/hiperclocks.html 9 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C3, C5 and C6, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 20 (XTAL1) and 19 (XTAL2). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. C6 GND VCC C1 C5 Signals R7 VCCA C16 VIA C11 X1 C2 C3 U1 ICS84327 Pin1 50 Ohm Traces FIGURE 5B. PCB BOARD LAYOUT FOR ICS84327 84327AM www.icst.com/products/hiperclocks.html 10 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS84327. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS84327 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 6 * 30.2mW = 181mW Total Power_MAX (3.465V, with all outputs switching) = 485mW + 181mW = 666mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.666W * 43°C/W = 98.6°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 50°C/W 43°C/W 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 84327AM www.icst.com/products/hiperclocks.html 11 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX – 1.0V CCO_MAX ) = 1.0V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V ) = [(2V - (V OH_MAX CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V OH_MAX )= [(2V - 1V)/50Ω] * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 84327AM www.icst.com/products/hiperclocks.html 12 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Multi-Layer PCB, JEDEC Standard Test Boards 0 200 50°C/W 43°C/W 500 38°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS84327 is: 2804 84327AM www.icst.com/products/hiperclocks.html 13 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - M SUFFIX FOR ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER 24 LEAD SOIC TABLE 9. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N Maximum 24 A -- 2.65 A1 0.10 -- A2 2.05 2.55 B 0.33 0.51 C 0.18 0.32 D 15.20 15.85 E 7.40 7.60 e H 1.27 BASIC 10.00 10.65 h 0.25 0.75 L 0.40 1.27 a 0° 8° Reference Document: JEDEC Publication 95, MS-013, MO-119 84327AM www.icst.com/products/hiperclocks.html 14 REV. A SEPTEMBER 18, 2003 PRELIMINARY Integrated Circuit Systems, Inc. ICS84327 CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Count Temperature ICS84327AM ICS84327AM 24 Lead SOIC 30 per tube 0°C to 70°C ICS84327AMT ICS84327AM 24 Lead SOIC on Tape and Reel 1000 0°C to 70°C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 84327AM www.icst.com/products/hiperclocks.html 15 REV. A SEPTEMBER 18, 2003