PRELIMINARY ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS843242 is a 2 differential output LVPECL Synthesizer designed to generate Ether net HiPerClockS™ reference clock frequencies and is a member of the HiPerClocks™ family of high performance clock solutions from IDT. Using a 31.25MHz or 26.041666MHz, 18pF parallel resonant crystal, the follow-ing frequencies can be generated based on the settings of 4 frequency select pins (SEL[A1:A0], SEL[B1:B0]): 625MHz, 312.5MHz, 156.25MHz, and 125MHz. • Two 3.3V differential LVPECL output pairs The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The ICS843242 IDT’s 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS843242 is packaged in a small 16-pin TSSOP package. • Full 3.3V supply mode ICS • Using a 31.25MHz or 26.041666 crystal, the two output banks can be independently set for 625MHz, 312.5MHz, 156.25MHz or 125MHz • Crystal oscillator interface • VCO range: 560MHz to 700MHz • RMS phase jitter @ 625MHz (1.875MHz - 20MHz): 0.4ps (typical) • 0°C to 70°C ambient operating temperature • Industrial temperature available upon request • Available in both standard (RoHS 5) and lead-free (RoHS 6) compliant packages BLOCK DIAGRAM PIN ASSIGNMENT 0=Pullup SELA[0:1} 1=Pulldown 2 XTAL_IN Phase Detector OSC XTAL_OUT VCO 560MHz - 700MHz Feedback Divider 0 = ÷20 (default) 1 = ÷24 00 01 10 11 ÷1 ÷2 (default) ÷4 ÷5 00 01 10 11 ÷1 ÷2 ÷4 (default) ÷5 nQA QB nQB nQB QB VCCO_B SELB1 SELB2 VCCO_A QA nQA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XTAL_IN XTAL_OUT VEE SELA1 SELA0 VCC VCCA FB_SEL ICS843242 16-Lead TSSOP 4.4mm x 5.0mm x 0.92mm package body G Package Top View FB_SEL Pulldown 0=Pulldown SELB[0:1} 1=Pullup QA 2 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 1 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Νυ μ β ε ρ Ναμ ε Τψπ ε 1, 2 nQB, QB Output 3 VCCO_B Power 4 SELB1 Input 5 SELB0 Input 6 VCCO_A Power 7, 8 QA, nQA Output 9 FB_SEL Input 10 VCCA Power 11 VCC Power 12 SELA0 Input 13 SELA1 Input Δ ε σχριπ τιο ν Differential clock outputs. LVPECL interface levels. Output supply pin for QB, nQB outputs. Division select pin for Bank B. Default = High. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank B. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Output supply pin for QA, nQA outputs. Differential clock outputs. LVPECL interface levels. Feedback divide select. When Low (default), the feedback divider is set for ÷20. When HIGH, the feedback divider is set for ÷24. LVCMOS/LVTTL interface levels. Analog supply pin. Pulldown Core supply pin. Division select pin for Bank A. Default = HIGH. Pullup LVCMOS/LVTTL interface levels. Division select pin for Bank A. Default = Low. Pulldown LVCMOS/LVTTL interface levels. Negative supply pin. Power VEE XTAL_OUT, Cr ystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. 15, 1 6 Input XTAL_IN NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. 14 TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLDOWN Input Pulldown Resistor 51 kΩ RPULLUP Input Pullup Resistor 51 kΩ IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 2 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TABLE 3A. BANK A FREQUENCY TABLE Inputs Bank A Output Divider M/N Multiplication Factor QA/nQA Output Frequency Crystal Frequency SELA1 SELA0 FB_SEL Feedback Divider 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 Bank B Output Divider M/N Multiplication Factor QB/nQB Output Frequency TABLE 3B. BANK B FREQUENCY TABLE Inputs Crystal Frequency SELA1 SELA0 FB_SEL Feedback Divider 31.25 0 0 0 20 1 20 625 31.25 0 1 0 20 2 10 312.5 31.25 1 0 0 20 4 5 156.25 31.25 1 1 0 20 5 4 125 26.041666 0 0 1 24 1 24 625 26.041666 0 1 1 24 2 12 312.5 26.041666 1 0 1 24 4 6 156.25 26.041666 1 1 1 24 5 4.8 125 TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE Inputs Outputs SELA1 SELA0 0 0 Inputs Outputs QA SELB1 SELB0 QB 0 ÷1 0 0 ÷1 1 ÷2 (default) 0 1 ÷2 1 0 ÷4 1 0 ÷4 (default) 1 1 ÷5 1 1 ÷5 TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE Inputs FB_DIV Feedback Divide 0 ÷20 (default) 1 ÷24 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 3 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 92.4°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V VCCA Analog Supply Voltage VCC – 0.12 3.3 VCC V VCCO_A, VCCO_B Output Supply Voltage 3.135 3.3 3.465 V IEE Power Supply Current 125 mA ICCA Analog Supply Current 12 mA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions Minimum Typical Maximum Units V VIH Input High Voltage 2 VCC + 0.3 VIL Input Low Voltage -0.3 0.8 V VCC = VIN = 3.465V 150 µA SELA0, SELB1 VCC = VIN = 3.465V 5 µA IIH Input High Current FB_SEL, SELA1, SELB0 IIL Input Low Current FB_SEL, SELA1, SELB0 VCC = 3.465V, VIN = 0V -5 µA SELA0, SELB1 VCC = 3.465V, VIN = 0V -150 µA TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCO_A = VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Maximum Units VOH Output High Voltage; NOTE 1 Test Conditions VCCO_X - 1.4 Minimum Typical VCCO_X - 0.9 V VOL Output Low Voltage; NOTE 1 VCCO_X - 2.0 VCCO_X - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V NOTE 1: Outputs terminated with 50Ω to VCCO_X - 2V. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 4 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TABLE 5. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental FB_SEL = ÷20 28 31.25 35 MHz FB_SEL = ÷24 23.33 26.04166 29.167 MHz Equivalent Series Resistance (ESR) 50 Ω Shunt Capacitance 7 pF Drive Level 1 mW Maximum Units Frequency NOTE: Characterized using an 18pF parallel resonant cr ystal. TABLE 6. AC CHARACTERISTICS, VCC = VCCO_A, VCCO_B = 3.3V±5%, TA = 0°C TO 70°C Symbol fOUT tsk(o) tjit(Ø) t R / tF Parameter Output Frequency Range Output Skew; NOTE 1, 3 RMS Phase Jitter (Random); NOTE 2 Test Conditions Minimum Typical Output Divider = ÷1 490 680 MHz Output Divider = ÷2 245 340 MHz Output Divider = ÷4 122.5 170 MHz Output Divider = ÷5 98 136 MH z Outputs @ Same Frequency 20 ps Outputs @ Different Frequencies 30 ps 625MHz (1.875MHz - 20MHz) 0.4 ps 312.5MHz (1.875MHz - 20MHz) 0.5 ps 156.25MHz (1.875MHz - 20MHz) 0.5 ps 125MHz (1.875MHz - 20MHz) 0.6 ps 20% to 80% 300 ps Output Rise/Fall Time SELx[1:0] = 00 50 odc Output Duty Cycle SELx[1:0] ≠ 00 50 NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions. Measured at the output differential cross points. NOTE 2: Please refer to the Phase Noise Plots. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 5 % % ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TYPICAL PHASE NOISE AT 625MHZ 625MHz ➤ RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.4ps (typical) Raw Phase Noise Data ➤ ➤ NOISE POWER dBc Hz Ethernet Filter Phase Noise Result by adding an Ethernet Filter to raw data OFFSET FREQUENCY (HZ) IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 6 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY PARAMETER MEASUREMENT INFORMATION 2V 2V VCC, VCCO_A. _B Qx nQx SCOPE Qx VCCA nQy LVPECL Qy nQx VEE tsk(o) -1.3V±0.165V 3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW Noise Power Phase Noise Plot Phase Noise Mask 80% 80% VSW I N G f1 Offset Frequency Clock Outputs f2 20% 20% tR tF RMS Jitter = Area Under the Masked Phase Noise Plot RMS PHASE JITTER OUTPUT RISE/FALL TIME nQA, nQB QA, QB t PW t odc = PERIOD t PW x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 7 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843242 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, VCCO_A and VCCO_B should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a 0.01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω VCCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE 18pF parallel resonant crystal and were chosen to minimize the ppm error. The ICS843242 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using a 31.25MHz or 26.041666MHz XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 27p FIGURE 2. CRYSTAL INPUt INTERFACE IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 8 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY LVCMOS TO XTAL INTERFACE impedance of the driver (Ro) plus the series resistance (Rs) equals the transmission line impedance. In addition, matched termination at the crystal input will attenuate the signal in half. This can be done in one of two ways. First, R1 and R2 in parallel should equal the transmission line impedance. For most 50Ω applications, R1 and R2 can be 100Ω. This can also be accomplished by removing R1 and making R2 50Ω. The XTAL_IN input can accept a single-ended LVCMOS signal through an AC coupling capacitor. A general interface diagram is shown in Figure 3. The XTAL_OUT pin can be left floating. The input edge rate can be as slow as 10ns. For LVCMOS inputs, it is recommended that the amplitude be reduced from full swing to half swing in order to prevent signal interference with the power rail and to reduce noise. This configuration requires that the output VDD VDD R1 Ro .1uf Rs Zo = 50 XTAL_IN R2 Zo = Ro + Rs XTAL_OUT FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: CRYSTAL INPUTS For applications not requiring the use of the crystal oscillator input, both XTAL_IN and XTAL_OUT can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from XTAL_IN to ground. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 9 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TERMINATION FOR 3.3V LVPECL OUTPUTS designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are 3.3V Zo = 50Ω 125Ω FOUT FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 125Ω 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FIN 50Ω Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION 10 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843242. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843242 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 125mA = 433mW Power (outputs)MAX = 30mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30mW = 60mW Total Power_MAX (3.465V, with all outputs switching) = 433mW + 60mW = 493mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92.4°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.493W * 92.4°C/W = 115.5°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 16-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W 11 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 5. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – 2V. CCO • For logic high, VOUT = VOH_MAX = VCCO_MAX – 0.9V (VCCO_MAX – VOH_MAX) = 0.9V • For logic low, VOUT = VOL_MAX = VCCO_MAX – 1.7V (VCCO_MAX – VOL_MAX) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOH_MAX) = [(2V - (VCCO_MAX – VOH_MAX))/R ] * (VCCO_MAX – VOH_MAX) = L L [(2V – 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(VOL_MAX – (VCCO_MAX – 2V))/R ] * (VCCO_MAX – VOL_MAX) = [(2V - (VCCO_MAX – VOL_MAX))/R ] * (VCCO_MAX – VOL_MAX) = L L [(2V – 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 12 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 92.4°C/W 88.0°C/W 85.9°C/W TRANSISTOR COUNT The transistor count for ICS843242 is: 3751 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 13 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 α 0° 8° aaa -- 0.10 0.75 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 14 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843242AG 843242AG 16 Lead TSSOP tube 0°C to 70°C ICS843242AGT 843242AG 16 Lead TSSOP 2500 tape & reel 0°C to 70°C ICS843242AGLF TBD 16 Lead "Lead-Free" TSSOP tube 0°C to 70°C ICS843242AGLFT TB D 16 Lead "Lead-Free" TSSOP 2500 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 3.3V LVPECL FREQUENCY SYNTHESIZER 15 ICS843242AG REV. A OCTOBER 2, 2007 ICS843242 FEMTOCLOCKS™ CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA