IDT ICS844002AG

ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844002 is a 2 output LVDS Synthesizer
ICS
optimized to generate Fibre Channel reference
HiPerClockS™ clock frequencies and is a member of the
HiPerClocks TM family of high performance clock
solutions from IDT. Using a 26.5625MHz 18pF
parallel resonant crystal, the following frequencies can be
generated based on the 2 frequency select pins (F_SEL[1:0]):
212.5MHz, 187.5MHz, 159.375MHz, 106.25MHz and
53.125MHz. The ICS844002 uses IDT’s 3 rd generation low
phase noise VCO technology and can achieve <1ps typical rms
phase jitter, easily meeting Fibre Channel jitter requirements.
The ICS844002 is packaged in a small 20-pin TSSOP package.
• Two LVDS outputs
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
• Supports the following output frequencies: 212.5MHz,
187.5MHz, 159.375MHz, 106.25MHz and 53.125MHz
• VCO range: 560MHz - 680MHz
• RMS phase jitter @ 212.5MHz, using a 26.5625MHz crystal
(637kHz - 10MHz): 0.65ps (typical)
• Full 3.3V or 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTION TABLE
Inputs
Input
Frequency
(MHz)
26.5625
F_SEL1 F_SEL0
M Divider
Value
N Divider
Value
M/N Divider
Value
nc
VDDO
Q0
nQ0
MR
nPLL_SEL
nc
VDDA
F_SEL0
VDD
Output
Frequency
(MHz)
0
0
24
3
8
212.5
26.5625
0
1
24
4
6
159.375
26.5625
1
0
24
6
4
106.25
26.5625
1
1
24
12
2
53.125
23.4375
0
0
24
3
8
187.5
nPLL_SEL Pulldown
ICS844002
Q0
1
F_SEL[1:0]
0 0 ÷3
0 1 ÷4
1 0 ÷6
1
26.5625MHz
XTAL_IN
0
Phase
Detector
XTAL_OUT
nXTAL_SEL
VDDO
Q1
nQ1
GND
nc
nXTAL_SEL
REF_CLK
XTAL_IN
XTAL_OUT
F_SEL1
2
F_SEL[1:0] Pulldown
OSC
20
19
18
17
16
15
14
13
12
11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
G Package
Top View
BLOCK DIAGRAM
REF_CLK Pulldown
1
2
3
4
5
6
7
8
9
10
VCO
637.5MHz
(w/26.5625MHz
Reference)
11
÷12
nQ0
Q1
0
nQ1
Pulldown
M = 24 (fixed)
MR
Pulldown
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
1, 7
nc
Unused
2, 20
VDDO
Power
3, 4
Q0, nQ0
Ouput
5
MR
Input
6
nPLL_SEL
Input
8
Power
Input
Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Power
14
VDDA
F_SEL0,
F_SEL1
VDD
XTAL_OUT,
XTAL_IN
REF_CLK
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inver ted outputs nQx
Pulldown
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
Selects between the PLL and REF_CLK as input to the dividers. When
Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock
(PLL Bypass). LVCMOS/LVTTL interface levels.
Analog supply pin.
15
nXTAL_SEL
Input
Core supply pins.
Parallel resonant cr ystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Pulldown LVCMOS/LVTTL reference clock input.
Selects between cr ystal or REF_CLK inputs as the the PLL Reference
Pulldown source. Selects XTAL inputs when LOW. Selects REF_CLK when HIGH.
LVCMOS/LVTTL interface levels.
No connect.
9, 11
10
12, 13
Type
Input
Input
Description
No connect.
Output supply pins.
16
nc
Unused
17
GND
Power
Power supply ground.
18, 19
nQ1, Q1
Output
Differential output pair. LVDS interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
Test Conditions
2
Minimum
Typical
Maximum
Units
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Package Thermal Impedance, θJA 73.2°C/W (0 lfpm)
Storage Temperature, TSTG
-65°C to 150°C
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
VDD
Core Supply Voltage
3.135
3.3
3.465
V
VDDA
Analog Supply Voltage
VDD – 0.12
3.3
3.465
V
3.135
3.3
VDDO
Output Supply Voltage
3.465
V
IDD
Power Supply Current
105
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
120
mA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VDD
Core Supply Voltage
Test Conditions
Minimum
Typical
Maximum
Units
2.375
2.5
2.625
V
VDDA
Analog Supply Voltage
VDD – 0.10
2.5
2.625
V
VDDO
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
95
mA
IDDA
Analog Supply Current
10
mA
IDDO
Output Supply Current
90
mA
TABLE 3C. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIH
Input
High Current
IIL
Input
Low Current
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
REF_CLK, MR,
F_SEL0, F_SEL1,
nPLL_SEL, nXTAL_SEL,
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
Test Conditions
VDD = 3.3V
Minimum Typical
2
Maximum
VDD + 0.3
Units
V
VDD = 2.5V
1.7
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
V
VDD = 2.5V
-0.3
0.7
V
150
µA
VDD = VIN = 3.465
or 2.5V
VDD = 3.465V or 2.5V,
VIN = 0V
3
-150
µA
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
300
450
600
mV
50
mV
1.4
1.525
1.65
V
50
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
Parameter
VOD
Differential Output Voltage
Δ VOD
VOD Magnitude Change
VOS
Offset Voltage
Δ VOS
VOS Magnitude Change
Test Conditions
Minimum
Typical
Maximum
Units
250
400
550
mV
1.0
50
mV
1.4
V
50
mV
Maximum
Units
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Mode of Oscillation
Typical
Fundamental
28.33
MHz
Equivalent Series Resistance (ESR)
Frequency
23.33
26.5625
50
Ω
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
tjit(Ø)
tR / tF
RMS Phase Jitter (Random);
NOTE 3
Output Rise/Fall Time
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
Typical
Maximum
Units
226.66
MHz
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
15
ps
212.5MHz, (637kHz - 10MHz)
0.65
ps
159.375MHz, (637kHz - 10MHz)
0.61
ps
106.25MHz, (637kHz -10MHz)
0.74
ps
53.125MHz, (637kHz - 10MHz)
0.64
ps
187.5MHz, (637kHz - 10MHz)
0.80
ps
20% to 80%
250
F_SEL[1:0] ≠ ÷3
48
odc
Output Duty Cycle
F_SEL[1:0] = ÷3
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
500
ps
52
55
%
%
Maximum
Units
226.66
MHz
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol
fOUT
t sk(o)
t jit(Ø)
Parameter
Output Frequency
Test Conditions
Minimum
F_SEL[1:0] = 00
186.67
F_SEL[1:0] = 01
140
170
MHz
F_SEL[1:0] = 10
93.33
113.33
MHz
F_SEL[1:0] = 11
46.67
56.66
MHz
Output Skew; NOTE 2, 4
RMS Phase Jitter (Random);
NOTE 3
15
Output Rise/Fall Time
0.65
ps
159.375MHz, (637kHz - 10MHz)
0.61
ps
106.25MHz, (637kHz -10MHz)
0.74
ps
53.125MHz, (637kHz - 10MHz)
0.64
ps
20% to 80%
0.80
250
F_SEL[1:0] ≠ ÷3
48
F_SEL[1:0] = ÷3
45
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
odc
Output Duty Cycle
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
ps
212.5MHz, (637kHz - 10MHz)
187.5MHz, (637kHz - 10MHz)
tR / tF
Typical
5
ps
500
ps
52
55
%
%
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 212.5MHZ
➤
0
-10
-20
Fibre Channel Jitter Filter
-30
-40
212.5MHz
-50
RMS Phase Jitter (Random)
637khz to 10MHz = 0.65ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
➤
NOISE POWER dBc
Hz
-60
-110
-120
-130
-140
➤
-150
-160
-170
-180
-190
100
1k
Phase Noise Result by adding
Fibre Channel Filter to raw data
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 106.25MHZ
➤
0
-10
-20
Fibre Channel Jitter Filter
-30
-40
-50
106.25MHz
RMS Phase Jitter (Random)
637khz to 10MHz = 0.74ps (typical)
-70
-80
-90
-100
Raw Phase Noise Data
-110
➤
NOISE POWER dBc
Hz
-60
-120
-130
➤
-140
-150
-160
Phase Noise Result by adding
Fibre Channel Filter to raw data
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
SCOPE
VDD,
VDDO V
DDA
3.3V±5%
POWER SUPPLY
+ Float GND –
SCOPE
Qx
2.5V±5%
POWER SUPPLY
+ Float GND –
LVDS
VDD,
VDDO V
DDA
Qx
LVDS
nQx
nQx
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx
nQ0, nQ1
Qx
Q0, Q1
t PW
t
nQy
Qy
odc =
tsk(o)
PERIOD
t PW
x 100%
t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
Noise Power
Phase Noise Plot
80%
80%
VSW I N G
Phase Noise Mask
Clock
Outputs
f1
Offset Frequency
20%
20%
tR
tF
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT RISE/FALL TIME
VDD
VDD
out
➤
➤
LVDS
100
DC Input
VOD/Δ VOD
out
LVDS
➤
➤
DC Input
➤
out
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
OFFSET VOLTAGE SETUP
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ICS844002AG REV. A SEPTEMBER 28, 2007
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844002 provides separate power supplies to isolate any high switching noise from
the outputs to the internal PLL. VDD, VDDA, and VDDO should be
individually connected to the power supply plane through vias,
and bypass capacitors should be used for each pin. To achieve
optimum jitter performance, power supply isolation is required.
Figure 1 illustrates how a 10Ω resistor along with a 10μF and a
0.01μF bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
10Ω
VDDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 26.5625MHz, 18pF parallel resonant
crystal and were chosen to minimize the ppm error.
The ICS844002 has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
XTAL_OUT
C1
33p
X1
18pF Parallel Crystal
XTAL_IN
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
LVCMOS TO XTAL INTERFACE
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination
at the crystal input will attenuate the signal in half. This can be
done in one of two ways. First, R1 and R2 in parallel should equal
the transmission line impedance. For most 50Ω applications, R1
and R2 can be 100Ω. This can also be accomplished by removing
R1 and making R2 50Ω.
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to
half swing in order to prevent signal interference with the power
rail and to reduce noise. This configuration requires that the output
VDD
VDD
R1
Ro
.1uf
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OUT
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
REF_CLK INPUT
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844002.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844002 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (105mA + 12mA) = 405.4mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 120mA = 415.8mW
Total Power_MAX = 405.4mW + 415.8mW = 821.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.821W * 66.6°C/W = 124.6°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and
the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 20-LEAD TSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
FOR
20 LEAD TSSOP
θJA by Velocity (Linear Feet per Minute)
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
0
200
500
114.5°C/W
73.2°C/W
98.0°C/W
66.6°C/W
88.0°C/W
63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844002 is: 2914
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 20 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MIN
N
A
MAX
20
--
1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
6.40
6.60
E
E1
6.40 BASIC
4.30
e
4.50
0.65 BASIC
L
0.45
0.75
α
0°
8°
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
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ICS844002AG REV. A SEPTEMBER 28, 2007
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FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
Temperature
ICS844002AG
ICS844002AG
20 Lead TSSOP
tube
0°C to 70°C
ICS844002AGT
ICS844002AG
20 Lead TSSOP
2500 tape & reel
0°C to 70°C
ICS844002AGLF
ICS844002AGL
20 Lead "Lead-Free" TSSOP
tube
0°C to 70°C
ICS844002AGLFT
ICS844002AGL
20 Lead "Lead-Free" TSSOP
2500 tape & reel
0°C to 70°C
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
14
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
6
Added Phase Noise Plots.
7/24/06
A
11
1
2
Power Consideraitons - corrected sentence after the Tj calculation.
Pin Assignment - corrected Pin 16 from VDD to nc.
Pin Description Table - deleted number 16 from VDD row and added row
Pin 16 as a "nc".
1/19/07
A
T1
IDT ™ / ICS™ LVDS FREQUENCY SYNTHESIZER
15
9/28/07
ICS844002AG REV. A SEPTEMBER 28, 2007
ICS844002
FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER
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© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS, FemtoClocks and HiPerClockS
are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks
are or may be trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA