ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TOLVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS85411I is a low skew, high performance ICS 1-to-2 Differential-to-LVDS Fanout Buffer and a HiPerClockS™ member of the HiPerClockS™ family of High Performance Clock Solutions from IDT. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411I is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85411I ideal for those clock distribution applications demanding well defined perfor mance and repeatability. • Two differential LVDS outputs • One differential CLK, nCLK clock input • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Maximum output frequency: 650MHz • Translates any single ended input signal to LVDS levels with resistor bias on nCLK input • Output skew: 25ps (maximum) • Part-to-part skew: 300ps (maximum) • Additive phase jitter, RMS: 0.05ps (typical) • Propagation delay: 2.5ns (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead free (RoHS 6) packages BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT Q0 nQ0 Q0 nQ0 Q1 nQ1 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND ICS85411I 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 1 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name Type Description 1, 2 Q0, nQ0 Output 3, 4 Q1, nQ1 Output Differential output pair. LVDS interface levels. 5 GND Power Power supply ground. 6 nCLK Input 7 CLK Input 8 VDD Power Differential output pair. LVDS interface levels. Pulldown Inver ting differential clock input. Pullup Non-inver ting differential clock input. Positive supply pin. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance Test Conditions Minimum Typical 4 Maximum Units pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 2 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5V Outputs, IO Continuous Current Surge Current 10mA 15mA NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) -65°C to 150°C Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.97 3.3 3.63 V 50 mA Maximum Units TABLE 3B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage; NOTE 1 Minimum Typical CLK VDD = VIN = 3.63V 5 µA nCLK VDD = VIN = 3.63V 150 µA CLK VDD = 3.63, VIN = 0V nCLK VDD = 3.63V, VIN = 0V Common Mode Input Voltage; NOTE 1, 2 VCMR NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. -150 µA -5 µA 0.15 1. 3 V 0.5 VDD - 0.85 V Units TABLE 3C. LVDS DC CHARACTERISTICS, VDD = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter VOD Differential Output Voltage Δ VOD VOD Magnitude Change VOS Offset Voltage Test Conditions Minimum Typical Maximum 247 325 454 mV 0 50 mV 1.325 1.45 1.575 V 5 50 mV -20 ±1 +2 0 µA Δ VOS VOS Magnitude Change IOFF Power Off Leakage IOSD Differential Output Shor t Circuit Current -3.5 -5 mA IOS Output Shor t Circuit Current -3.5 -5 mA VOH Output High Voltage 1.34 1.6 V VOL Output Low Voltage IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 0.9 3 1.06 V ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 4. AC CHARACTERISTICS, VDD = 3.3V±10% TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical 1.5 Maximum Units 650 MHz 2.5 ns t sk(o) Output Skew; NOTE 2, 4 25 ps t sk(pp) Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time 300 ps t jit t R / tF odc Output Duty Cycle (12kHz to 20MHz) 0.05 20% to 80% @ 50MHz 150 350 ps f > 500MHz 46 54 % 52 % f ≤ 500MHz 48 All parameters measured at ƒ≤ 650MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER ps 4 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz 0 -10 -20 Input/Output Additive Phase Jitter @ 200MHz (12kHz to 20MHz) -30 = 0.05ps typical -40 -50 SSB PHASE NOISE dBc/HZ -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100 1k 10k 100k 1M 10M 100M 500M OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 5 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION VDD nCLK SCOPE Qx VDD 3.3V±10% POWER SUPPLY + Float GND – V V Cross Points PP CMR CLK LVDS nQx GND 3.3V OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx nQx PART 1 Qx Qx nQy PART 2 Qy nQy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nCLK 80% 80% CLK VOD Clock Outputs nQ0, nQ1 20% 20% tF tR Q0, Q1 tPD PROPAGATION DELAY OUTPUT RISE/FALL TIME VDD Q0, Q1 out t PW odc = ➤ PERIOD t PW DC Input LVDS 100 x 100% VOD/Δ VOD out ➤ t ➤ nQ0, nQ1 t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER DIFFERENTIAL OUTPUT VOLTAGE SETUP 6 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER VDD out LVDS ➤ DC Input LVDS ➤ out ➤ VOS/Δ VOS VDD IOFF ➤ POWER OFF LEAKAGE SETUP OFFSET VOLTAGE SETUP VDD VDD ➤ out DC Input out IOS LVDS DC Input ➤ LVDS IOSD ➤ IOSB out out OUTPUT SHORT CIRCUIT CURRENT SETUP IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER DIFFERENTIAL OUTPUT SHORT CIRCUIT CURRENT SETUP 7 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVDS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 8 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for IDT HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN IDT HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER BY 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 BY R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER BY BY 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER BY 9 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 3.3V 3.3V LVDS + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 10 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85411I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85411I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 10% = 3.63V, which gives worst case results. • Power (core)MAX = VDD_MAX * IDD_MAX = 3.63V * 50mA = 181.5mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3°C/W per Table 5 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.182W * 103.3°C/W = 103.8°C. This is below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 5. THERMAL RESISTANCE θJA FOR 8-LEAD SOIC, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 11 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85411I is: 636 IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 12 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PACKAGE OUTLINE - M SUFFIX FOR 8 LEAD SOIC TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUN N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 4.00 e 1.27 BASIC H 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 13 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS85411AMI 85411AI 8 lead SOIC tube -40°C to 85°C ICS85411AMIT 85411AI 8 lead SOIC 2500 tape & reel -40°C to 85°C ICS85411AMILF 85411AIL 8 lead "Lead Free" SOIC tube -40°C to 85°C ICS85411AMILFT 85411AIL 8 lead "Lead Free" SOIC 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 14 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER REVISION HISTORY SHEET Rev Table Page T3C 3 B B 3x, 4 8 11 3, 4 Description of Change Changed VDD from ±5% to ±10% throughout datasheet. LVDS DC Characteristics Table - changed VOD range from 200mV min./360mV max. to 247mV min./454mV max. Changed ΔVOD from 40mV max. to 50mV max. Changed VOS from 1.125mV min./1.375mV max. to 1.325mV min./1.575mV max. Changed ΔVOS from 25mV max. to 50mV max. Added Recommendations for Unused Output Pins. Added Power Considerations. Corrected temperature in tables. IDT ™ / ICS™ DIFFERENTIAL-TO-LVDS FANOUT BUFFER 15 Date 9/25/06 11/7/07 ICS85411AMI REV. B NOVEMBER 7, 2007 ICS85411I LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVDS FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA