ICS854S204I LOW SKEW, DUAL, PROGRAMMABLE 1-TO-2 DIFFERENTIALTO-LVDS, LVPECL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS854S204I is a low skew, high performance ICS dual, programmable 1-to-2 Differential-to-LVDS, HiPerClockS™ LVPECL Fanout Buffer and a member of the HiPerClock S™ family of High Performance Clock Solutions from IDT. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The ICS854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the ICS854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. • Two programmable differential LVDS or LVPECL output banks • Two differential clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML • Maximum output frequency: 3GHz • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs • Output skew: 15ps (maximum) • Bank skew: 15ps (maximum) • Propagation delay: 500ps (maximum) • Additive phase jitter, RMS: 0.15ps (typical) • Full 3.3V or 2.5V power supply • -40°C to 85°C ambient operating temperature POWER SUPPLY CONFIGURATION TABLE 3.3V Operation 2.5V Operation • Available in lead-free (RoHS 6) package VDD = 3.3V VTAP = nc VDD = 2.5V VTAP = 2.5V SEL_OUT FUNCTION TABLE SEL_OUT Output Level 0 LVDS 1 LVPECL BLOCK DIAGRAM PIN ASSIGNMENT VTAP PCLKA nPCLKA QA0 nQA0 QA1 nQA1 VTAP GND SEL_OUT Pulldown PCLKA Pulldown nPCLKA Pullup PCLKB Pulldown Pullup nPCLKB QA0 nQA0 QA1 nQA1 QB0 nQB0 16 15 14 13 12 11 10 9 nPCLKB PCLKB QB0 nQB0 QB1 nQB1 VDD SEL_OUT ICS854S204I QB1 nQB1 IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 1 2 3 4 5 6 7 8 16-Lead TSSOP 4.4mm x 5.0mm x 0.925mm package body G Package Top View 1 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number Name 1 PCLKA Type Input Description Pulldown Non-inver ting differential clock input. Inver ting differential clock input. 2 nPCLKA Input 3, 4 QA0, nQA0 Output Pullup Differential output pair. LVDS or LVPECL interface levels. 5, 6 QA1, nQA1 Output 7 VTAP Power 8 GND Power Differential output pair. LVDS or LVPECL interface levels. Power supply pin. Tie to VDD for 2.5V operation. For 3.3V operation, do not connect. Power supply ground. Pulldown Selects between LVDS or LVPECL outputs. 9 SEL_OUT Input 10 VDD Power Power supply pin. 1 1, 12 nQB1, QB1 Output Differential output pair. LVDS or LVPECL interface levels. 13, 14 nQB0, QB0 Output 15 PCLKB Input 16 nPCLKB Input Differential output pair. LVDS or LVPECL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions CIN Input Capacitance RPULLUP RPULLDOWN Minimum Typical Maximum Units 1 pF Input Pullup Resistor 51 kΩ Input Pulldown Resistor 51 kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs PCLKA or PCLKB 0 nPCLKA or nPCLKB 1 1 0 0 1 Outputs QA0, QA1, nQA0, nQA1, QB0, QB1 nQB0, nQB1 HIGH LOW Input to Output Mode Polarity Differential to Differential Non Inver ting Differential to Differential Non Inver ting HIGH LOW Biased; NOTE 1 LOW HIGH Single Ended to Differential Non Inver ting Biased; NOTE 1 HIGH LOW Single Ended to Differential Non Inver ting Biased; NOTE 1 0 HIGH LOW Single Ended to Differential Inver ting Biased; NOTE 1 1 LOW HIGH Single Ended to Differential Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 2 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, IO (LVDS) Continuous Current Surge Current 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. -0.5V to VDD + 0.5 V 50mA 100mA 10mA 15mA Package Thermal Impedance, θJA 92°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C (Junction-to-Ambient) TABLE 4A. LVDS POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 120 mA TABLE 4B. LVDS POWER SUPPLY DC CHARACTERISTICS, VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VDD Power Supply Voltage 2.375 2.5 2.625 V VTAP Power Supply Voltage 2.375 2.5 2.625 V IDD Power Supply Current 115 mA ITAP Power Supply Current 5 mA TABLE 4C. LVPECL POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Power Supply Voltage IDD Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 66 mA TABLE 4D. LVPECL POWER SUPPLY DC CHARACTERISTICS, VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VDD Test Conditions Minimum Typical Maximum Units Power Supply Voltage 2.375 2.5 2.625 V 2.375 2.5 VTAP Power Supply Voltage 2.625 V IDD Power Supply Current 60 mA ITAP Power Supply Current 5 mA IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 3 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TABLE 4E. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5% OR VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol VIH Parameter Input High Voltage Test Conditions Minimum Maximum Units VDD = 3.3V 2 VCC + 0.3 V VDD = 2.625V 1.7 VCC + 0.3 V VDD = 3.3V -0.3 0.8 V VDD = 2.625V -0.3 VIL Input Low Voltage IIH Input High Current SEL_OUT VDD = VIN = 3.465V or 2.625V IIL Input Low Current SEL_OUT VDD = 3.465V or 2.625V, VIN = 0V Typical 0.7 V 150 µA -10 µA TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5% OR VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V VDD = VIN = 3.465V or 2.625V VDD = 3.465V or 2.625V, VIN = 0V PCLKA, PCLKB IIH Input High Current nPCLKA, nPCLKB PCLKA, PCLKB IIL Input Low Current nPCLKA, nPCLKB Minimum Peak-to-Peak Input Voltage; NOTE 1 Common Mode Input Voltage; VCMR NOTE 1, 2 NOTE 1: VIL should not be less than -0.3V. NOTE 2: Common mode voltage is defined as VIH. Typical Maximum Units 150 µA 10 µA -10 µA -150 µA 0.15 1.3 V GND + 0.5 VDD - 0.85 V VPP TABLE 4G. LVDS DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Δ VOD Differential Output Voltage SEL_OUT = 0 247 350 454 mV VOD Magnitude Change SEL_OUT = 0 50 mV VOS Offset Voltage SEL_OUT = 0 1.38 V ∆ VOS VOS Magnitude Change SEL_OUT = 0 50 mV 1.11 1.25 NOTE: Please refer to Parameter Measurement Information for output information. TABLE 4H. LVDS DC CHARACTERISTICS, VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage SEL_OUT = 0 247 350 454 mV 50 mV 1.08 1.21 1.34 V 50 mV Δ VOD VOD Magnitude Change SEL_OUT = 0 VOS Offset Voltage SEL_OUT = 0 ∆ VOS VOS Magnitude Change SEL_OUT = 0 NOTE: Please refer to Parameter Measurement Information for output information. IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 4 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TABLE 4I. LVPECL DC CHARACTERISTICS, VDD = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Output High Voltage; NOTE 1 SEL_OUT = 1 VOL Output Low Voltage; NOTE 1 VSWING Peak-to-Peak Output Voltage Swing VOH Typical Maximum Units VDD - 1.3 VDD - 0.8 V SEL_OUT = 1 VDD - 2.0 VDD - 1.6 V SEL_OUT = 1 0.6 0.9 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VDD - 2V. TABLE 4J. LVPECL DC CHARACTERISTICS, VDD = VTAP = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum VOH VOL VSWING Typical Output High Voltage; NOTE 1 SEL_OUT = 1 VDD - 1.3 VDD - 0.8 V Output Low Voltage; NOTE 1 SEL_OUT = 1 VDD - 2.0 VDD - 1.55 V Peak-to-Peak Output Voltage Swing SEL_OUT = 1 0.6 0.9 V NOTE 1: Outputs terminated with 50Ω to VDD - 2V. TABLE 5A. LVDS AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(b) Bank Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF Test Conditions Minimum 100MHz, Integration Range: 12kHz – 20MHz 20% to 80% Typical Maximum Units 3 GHz 500 ps 15 ps 15 ps 0.15 100 ps 200 ps odc Output Duty Cycle 49 51 All parameters measured at 550MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5B. LVDS AC CHARACTERISTICS, VDD = VTAP = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(b) Bank Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF Test Conditions 100MHz, Integration Range: 12kHz – 20MHz 20% to 80% odc Output Duty Cycle For NOTES, see Table 5A above. IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 5 Minimum Typical Maximum Units 3 GHz 500 ps 15 ps 15 ps 0.13 ps 100 200 ps 49 51 % ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TABLE 5C. LVPECL AC CHARACTERISTICS, VDD = 3.3V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 Test Conditions Minimum Typical Maximum Units 3 GHz 500 ps tsk(o) Output Skew; NOTE 2, 4 15 ps tsk(b) Bank Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time 15 ps tjit tR / tF 100MHz, Integration Range: 12kHz – 20MHz 20% to 80% 0.12 100 ps 200 ps odc Output Duty Cycle 49 51 All parameters measured at 550MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 5D. LVPECL AC CHARACTERISTICS, VDD = VTAP = 2.5V ± 5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tsk(o) Output Skew; NOTE 2, 4 tsk(b) Bank Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Section Output Rise/Fall Time tjit tR / tF Test Conditions 100MHz, Integration Range: 12kHz – 20MHz 20% to 80% Minimum Typical Maximum Units 3 GHz 500 ps 15 ps 15 ps 0.07 200 ps odc Output Duty Cycle 49 51 All parameters measured at 550MHz unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured from the output differential cross points. NOTE 3: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. % IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 6 100 ps ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Input/Output Additive Phase Jitter at 100MHz SSB PHASE NOISE dBc/HZ = 0.12ps (typical) OFFSET FROM CARRIER FREQUENCY (HZ) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 7 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION SCOPE SCOPE Qx VDD 3.3V±5% POWER SUPPLY + Float GND – 2.5V±5% POWER SUPPLY + Float GND – LVDS Qx VDD, VTAP LVDS nQx nQx 3.3V LVDS OUTPUT LOAD AC TEST CIRCUIT 2.5V LVDS OUTPUT LOAD AC TEST CIRCUIT 2V 2V VDD Qx SCOPE VDD, VTAP LVPECL Qx SCOPE LVPECL nQx nQx VEE VEE -1.3V±0.165V -0.5V±0.125V 3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT 2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT VDD nQXx QXx nPCLKA, nPCLKB V PP Cross Points nQXy V CMR PCLKA, PCLKB QXy tsk(b) GND Where X = A or B BANK SKEW DIFFERENTIAL INPUT LEVEL IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 8 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION, CONTINUED nQx nCLKA, nCLKB Qx CLKA, CLKB nQy nQAx, nQBx QAx, QBx Qy tsk(o) tPD PROPAGATION DELAY OUTPUT SKEW nQAx, nQBx 80% 80% QAx, QBx 20% 20% t PW t odc = PERIOD t PW nQAx, nQBx VOD LVDS QAx, QBx 20% 20% tR OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD tF OUTPUT RISE/FALL TIME VDD VDD 100 ➤ out out ➤ DC Input VOD/Δ VOD out LVDS ➤ LVDS 80% 80% x 100% t PERIOD DC Input tF tR ➤ QAx, QBx VSW I N G LVPECL nQAx, nQBx out ➤ VOS/Δ VOS ➤ DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER OFFSET VOLTAGE SETUP 9 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input PCLK V_REF nPCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: PCLK/nPCLK INPUTS For applications not requiring the use of the differential input, both PCLK and nPCLK can be left floating. Though not required, but for additional protection, a 1kΩ resistor can be tied from PCLK to ground. LVDS OUTPUTS All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. LVPECL OUTPUTS All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 10 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER LVPECL CLOCK INPUT INTERFACE The PCLK /nPCLK accepts LVPECL, LVDS, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 3.3V 3.3V 3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm R2 50 Zo = 50 Ohm PCLK PCLK R1 100 Zo = 50 Ohm nPCLK nPCLK Zo = 50 Ohm HiPerClockS PCLK/nPCLK HiPerClockS PCLK/nPCLK CML Built-In Pullup FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A BUILT-IN PULLUP CML DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 3.3V R4 125 Zo = 50 Ohm 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 84 R4 84 PCLK PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 nPCLK HiPerClockS Input R5 100 - 200 R2 84 FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER R6 100 - 200 R1 125 HiPerClockS PCLK/nPCLK R2 125 FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE 2.5V 3.3V 2.5V R3 120 SSTL R4 120 Zo = 60 Ohm PCLK Zo = 60 Ohm nPCLK R1 120 HiPerClockS PCLK/nPCLK R2 120 FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 11 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER 3.3V, 2.5V LVDS DRIVER TERMINATION A general LVDS interface is shown in Figure 3. In a 100Ω differential transmission line environment, LVDS drivers require a matched load termination of 100Ω across near the receiver input. For a multiple LVDS outputs buffer, if only partial outputs are used, it is recommended to terminate the unused outputs. 2.5V or 3.3V VDD LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION TERMINATION FOR 3.3V LVPECL OUTPUTS be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω FOUT 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o Zo = 50Ω VCC - 2V RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER FIN 50Ω 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION 12 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TERMINATION FOR 2.5V LVPECL OUTPUTS Figure 5A and Figure 5B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50Ω to VDD – 2V. For VDD = 2.5V, the VDD – 2V is very close to ground level. The R3 in Figure 5B can be eliminated and the termination is shown in Figure 5C. 2.5V 2.5V 2.5V VCCO=2.5V VCCO=2.5V R1 250 R3 250 Zo = 50 Ohm Zo = 50 Ohm + + Zo = 50 Ohm Zo = 50 Ohm - - 2,5V LVPECL Driv er 2,5V LVPECL Driv er R2 62.5 R1 50 R4 62.5 R2 50 R3 18 FIGURE 5A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE FIGURE 5B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE 2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50 FIGURE 5C. 2.5V LVPECL TERMINATION EXAMPLE IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 13 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER POWER CONSIDERATIONS (LVPECL OUTPUTS) This section provides information on power dissipation and junction temperature for the ICS854S204I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S204I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 66mA = 228.69mW Power (outputs)MAX = 32mW/Loaded Output pair If all outputs are loaded, the total power is 4 * 32mW = 128mW Total Power_MAX (3.465V, with all outputs switching) = 228.69mW + 128mW = 356.69mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92°C/W per Table 6A below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.357W * 92°C/W = 117.8°C. This is below the limit of 125°C. TABLE 6A. THERMAL RESISTANCE θJA FOR 16-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 92°C/W 14 1 87.6°C/W 2.5 85.5°C/W ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VDD Q1 VOUT RL 50Ω VDD - 2V FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V – 2V. DD • For logic high, VOUT = VOH_MAX = VDD_MAX – 0.8V (V DD_MAX • –V OH_MAX ) = 0.8V For logic low, VOUT = VOL_MAX = VDD_MAX – 1.6V (VDD_MAX – VOL_MAX) = 1.6V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(VOH_MAX – (VDD_MAX – 2V))/R ] * (VDD_MAX – VOH_MAX) = [(2V – (VDD_MAX – VOH_MAX))/R ] * (VDD_MAX – VOH_MAX) = L L [(2V – 0.8V)/50Ω] * 0.8V = 19.2mW Pd_L = [(VOL_MAX – (VDD_MAX – 2V))/R ] * (VDD_MAX – VOL_MAX) = [(2V – (VDD_MAX – VOL_MAX))/R ] * (VDD_MAX – VOL_MAX) = L L [(2V – 1.6V)/50Ω] * 1.6V = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32mW IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 15 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER POWER CONSIDERATIONS (LVDS OUTPUTS) This section provides information on power dissipation and junction temperature for the ICS854S204I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S204I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. • Power_MAX = VDD_MAX * IDD_MAX = 3.465V * 120mA = 415.8mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS TM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 92°C/W per Table 6B below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.416W * 92°C/W = 123.3°C. This is below the limit of 125°C. TABLE 6B. THERMAL RESISTANCE θJA FOR 16-LEAD TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 92°C/W 16 1 87.6°C/W 2.5 85.5°C/W ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP θJA by Velocity (Meters per Second) 0 Multi-Layer PCB, JEDEC Standard Test Boards 92°C/W 1 2.5 87.6°C/W 85.5°C/W TRANSISTOR COUNT The transistor count for ICS854S204I is: 454 PACKAGE OUTLINE AND DIMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP TABLE 8. PACKAGE DIMENSIONS Millimeters SYMBOL Minimum N A Maximum 16 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 4.90 5.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 17 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS854S204BGILF 4S204BIL 16 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS854S204BGILFT 4S204BIL 16 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS, LVPECL FANOUT BUFFER 18 ICS854S204BGI REV. A JUNE 4, 2008 ICS854S204I LOW SKEW, DUAL, 1-TO-2 DIFFERENTIAL-TO-LVDS, LVPECL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support Corporate Headquarters 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT [email protected] +480-763-2056 Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800-345-7015 (inside USA) +408-284-8200 (outside USA) © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA