PRELIMINARY ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TOLVDS FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS854S14I is a high speed 1-to-4 DifferentialICS to-LVDS Fanout Buffer and is a member of the HiPerClockS™ HiPerClockS™ family of high performance clock solutions from IDT. The ICS854S14I is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF _AC pin allow other differential signal families such as LVPECL, LVDS, and SSTL to be easily interfaced to the input with minimal use of external components. The device also has output enable pins which may be useful for system test and debug purposes. • Four differential LVDS outputs A PPLICATIONS : • 2.5V operating supply • Processor clock distribution • -40°C to 85°C ambient operating temperature • 622MHz central office clock distribution • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages • IN, nIN pair can accept the following differential input levels: LVPECL, LVDS, SSTL • 50Ω internal input termination to VT • Output frequency: 1.5GHz • Output skew: 30ps (typical) • Part-to-part skew: TBD • Additive phase jitter, RMS: 0.135ps (typical) • Propagation delay: 1.1ns (typical) • High speed network routing • Wireless basestations • Serdes LVPECL output to FPGA LVDS input translator • Fibre channel clock distribution • AMC clock driver for ATCA systems • Gigabit ethernet clock distibution VDD OE3 OE2 OE1 OE0 PIN ASSIGNMENT GND BLOCK DIAGRAM OE0 24 23 22 21 20 19 Q0 50Ω nIN OE2 3 16 nQ3 nQ1 4 15 nQ2 Q1 5 14 Q2 VDD 6 13 GND VDD 7 Q2 VREF_AC Q3 nQ0 nQ2 8 9 10 11 12 GND nQ1 VT 17 VREF_AC Q1 50Ω VDD 2 IN IN 18 Q0 VT OE1 1 nIN nQ0 GND ICS854S14I OE3 24-Lead VFQFN 4mm x 4mm x 0.95 package body K Package Top View Q3 nQ3 The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ LVDS FANOUT BUFFER 1 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1, 12, 13, 24 GND Power Type Power supply ground. Description 2, 3 Q0, nQ0 Output Differential output pair. LVDS interface levels. 4, 5 nQ1, Q1 Output Differential output pair. LVDS interface levels. 6, 7, 18, 19 VDD Power Positive supply pins. 8 nIN Input Inver ting differential clock input. 50Ω internal input termination to VT. 9 VT Input Termination input. 10 IN Input Non-inver ting differential clock input. 50Ω internal input termination to VT. 11 VREF_AC Output 14, 15 16, 17 Q2, nQ2 nQ3, Q3 Output Output Reference voltage for AC-coupled applications. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Active high output enable. When logic HIGH, the output pair is enabled. 20, 21, OE3, OE2, When logic LOW, the output pair is in a high impedance state. The OEx Input Pullup 22, 23 OE1, OE0 pins have an internal pullup resistor so the default power-up state of the outputs are enabled. LVCMOS/LVTTL interface levels. NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter RPULLUP Input Pullup Resistor IDT ™ / ICS™ LVDS FANOUT BUFFER Test Conditions Minimum Typical 51 2 Maximum Units kΩ ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY TABLE 3. OEX TRUTH TABLE Inputs IN Outputs nIN OE0 Q0 nQ0 0 1 1 0 1 1 0 1 1 0 X X 0 HI-Z HI-Z IN nIN OE1 Q1 nQ1 0 1 1 0 1 1 0 1 1 0 X X 0 HI-Z HI-Z IN nIN OE2 Q2 nQ2 0 1 1 0 1 1 0 1 1 0 X X 0 HI-Z HI-Z IN n IN OE3 Q3 nQ3 0 1 1 0 1 1 0 1 1 0 X X 0 HI-Z HI-Z IN nIN OE[0:3] Q[0:3] Enabled Disabled High Impedance State nQ[0:3] FIGURE 1. OE TIMING DIAGRAM IDT ™ / ICS™ LVDS FANOUT BUFFER 3 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD NOTE: Stresses beyond those listed under Absolute 4.6V Maximum Ratings may cause permanent damage to the Inputs, VI -0.5V to VDD + 0.5 V Outputs, IO (LVDS) Continuous Current Surge Current 10mA 15mA Input Current, IN, nIN ±50mA VT Current, IVT ±100mA Input Sink/Source, IREF_AC ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Storage Temperature, TSTG -65°C to 150°C Package Thermal Impedance, θJA 50.2°C (0 mps) device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. (Junction-to-Ambient) TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 2.375 2.5 2.625 V 88 mA TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage VIL Input Low Voltage IIH Input High Current OE[0:3] VDD = VIN = 2.625V IIL Input Low Current OE[0:3] VDD = 2.625V, VIN = 0V Minimum Typical Maximum Units 1.7 VDD + 0.3 V 0 0.7 V 5 µA -150 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Sy m b o l Par am et er RIN Differential Input Resistance (IN, nIN) Tes t Co n d i t i o n s Mi n i m u m Ty p i c al Max i m u m Un i t s IN-to-VT 40 50 60 Ω VIH Input High Voltage (IN, nIN) 1.2 VDD V VIL Input Low Voltage (IN, nIN) 0 VIH - 0.15 V VIN Input Voltage Swing 0.15 2.8 V VREF_AC Reference Voltage VDIFF_IN Differential Input Voltage Swing IIN Input Current; NOTE 1 VDD - 1.42 0.3 (IN, nIN) VDD - 1.37 VDD - 1.32 V 3.4 V 35 mA NOTE 1: Guaranteed by design. IDT ™ / ICS™ LVDS FANOUT BUFFER 4 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY TABLE 4D. LVDS DC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOD Differential Output Voltage 350 mV Δ VOD VOD Magnitude Change 50 mV VOS Offset Voltage 1.2 V Δ VOS VOS Magnitude Change 50 mV TABLE 5. AC CHARACTERISTICS, VDD = 2.5V ± 5%; TA = -40°C TO 85°C Symbol Parameter fMAX Maximum Output Frequency Propagation Delay; (Differential); NOTE 1 Output Skew; NOTE 2, 4 t PD tsk(o) tsk(pp) tjit tR/tF Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Condition Minimum Typical Maximum Units 1.5 GHz 1.1 ns 30 ps TBD ps 200MHz, Integration Range: 12kHz - 20MHz 0.135 ps 20% to 80% 170 ps All parameters are measured at ≤ 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LVDS FANOUT BUFFER 5 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD SCOPE Qx VDD 2.5V±5% POWER SUPPLY + Float GND – nIN LVDS V Cross Points IN V IH IN nQx V IL GND OUTPUT LOAD AC TEST CIRCUIT DIFFERENTIAL INPUT LEVEL nQx PART 1 Qx nQx nQy nQy Qx PART 2 Qy Qy tsk(pp) tsk(o) PART-TO-PART SKEW OUTPUT SKEW nIN 80% 80% IN VOD Clock Outputs 20% 20% tR nQ0:nQ3 tF Q0:Q3 tPD OUTPUT RISE/FALL TIME IDT ™ / ICS™ LVDS FANOUT BUFFER PROPAGATION DELAY 6 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY VDD out VDIFF_IN, VDIFF_OUT 800mV (typical) DC Input LVDS ➤ VIN, VOUT 400mV (typical) ➤ out VOS/Δ VOS ➤ SINGLE ENDED & DIFFERENTIAL INPUT VOLTAGE SWING OFFSET VOLTAGE SETUP VDD ➤ out ➤ LVDS 100 VOD/Δ VOD out ➤ DC Input DIFFERENTIAL OUTPUT VOLTAGE SETUP IDT ™ / ICS™ LVDS FANOUT BUFFER 7 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY APPLICATION INFORMATION Ω TERMINATIONS INTERFACE LVPECL INPUT WITH BUILT-IN 50Ω The IN /nIN with built-in 50Ω terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. The signal must meet the V PP and V CMR input requirements. Figures 2A to 2F show interface examples for the HiPerClockS IN/nIN input with built-in 50Ω terminations driven by the most 3.3V or 2.5V common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements. 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm LVDS Receiver With Built-In 50 Ohm 2.5V LVPECL R1 18 Ω FIGURE 2A. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN LVDS DRIVER 2.5V VT Zo = 50 Ohm nIN Ω FIGURE 2B. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN LVPECL DRIVER 2.5V 2.5V 2.5V Zo = 50 Ohm Zo = 50 Ohm IN IN VT Zo = 50 Ohm nIN CML - Open Collector VT Zo = 50 Ohm nIN Receiver With Built-In 50 Ohm CML - Built-in 50 Ohm Pull-up Receiver With Built-In 50 Ohm Ω FIGURE 2D. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY A CML DRIVER WITH Ω PULLUP BUILT-IN 50Ω Ω FIGURE 2C. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY AN OPEN COLLECTOR CML DRIVER 2.5V 2.5V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 3.3V CML with Built-In Pullup IN Zo = 50 Ohm C1 IN 50 Ohm 50 Ohm VT Zo = 50 Ohm C2 VT 50 Ohm Zo = 50 Ohm nIN R5 100 - 200 Ohm REF_AC Receiver with Built-In 50Ω Receiver with Built-In 50Ω Ω FIGURE 2E. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY A 3.3V LVPECL DRIVER IDT ™ / ICS™ LVDS FANOUT BUFFER 50 Ohm nIN REF_AC R5 100 - 200 Ohm C2 Ω FIGURE 2F. HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN 50Ω DRIVEN BY A 3.3V CML DRIVER WITH BUILT-IN PULLUP 8 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: LVCMOS CONTROL PINS: All control pins have internal pull-ups; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. LVDS Output All unused LVDS outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 2.5V LVDS DRIVER TERMINATION transmission line environment. For buffer with multiple LVDS driver, it is recommended to terminate the unused outputs. Figure 3 shows a typical ter mination for LVDS driver in characteristic impedance of 100Ω differential (50Ω single) 2.5V 2.5V LVDS_Driv er + R1 100 - 100 Ohm Differential Transmission Line Ω 100Ω Differential Transmission Line FIGURE 3. TYPICAL LVDS DRIVER TERMINATION THERMAL RELEASE PATH solder as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor’s Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology. The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through EXPOSED PAD SOLDER M ASK SOLDER SIGNAL TRACE SIGNAL TRACE GROUND PLANE Expose Metal Pad THERM AL VIA (GROUND PAD) FIGURE 4. P.C. BOARD FOR EXPOSED PAD THERMAL RELEASE PATH EXAMPLE IDT ™ / ICS™ LVDS FANOUT BUFFER 9 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS854S14I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS854S14I is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. • Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 88mA = 231mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 43.9°C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.231W * 43.9°C/W = 95.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE θ JA FOR 24-PIN VFQFN, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards IDT ™ / ICS™ LVDS FANOUT BUFFER 10 0 1 2.5 50.2°C/W 43.9°C/W 39.3°C/W ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY RELIABILITY INFORMATION TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD VFQFN θJA vs. 0 Air Flow (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 50.2°C/W 43.9°C/W 39.3°C/W TRANSISTOR COUNT The transistor count for ICS854S14I is: 288 IDT ™ / ICS™ LVDS FANOUT BUFFER 11 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY PACKAGE OUTLINE - K SUFFIX FOR 24 LEAD VFQFN TABLE 8. PACKAGE DIMENSIONS FOR 24 LEAD VFQFN JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL MINIMUM A 0.80 A1 0 1.0 0.05 0.25 Reference A3 b MAXIMUM 24 N 0.18 0.30 e 0.50 BASIC ND 6 NE 6 D 4 D2 2.30 2.55 4 E E2 2.30 2.55 L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220 IDT ™ / ICS™ LVDS FANOUT BUFFER 12 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY TABLE 9. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature 854S14AKI TB D 24 Lead VFQFN, tube -40°C to 85°C 854S14AKT TBD 24 Lead VFQFN 2500 tape & reel -40°C to 85°C 854S14AKILF S14AIL 24 Lead "Lead-Free" VFQFN tube -40°C to 85°C 854S14AKILFT S14AIL 24 Lead "Lead-Free" VFQFN 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LVDS FANOUT BUFFER 13 ICS854S14AKI REV. A FEBRUARY 23, 2007 ICS854S14I LOW SKEW, 1-TO-4 DIFFERENTIAL-TO-LVDS FANOUT BUFFER PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. 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