Integrated Circuit Systems, Inc. ICS9248-90 Frequency Generator & Integrated Buffers for PENTIUM/ProTM General Description Features The ICS9248-90 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Features include two CPU, six PCI and thirteen SDRAM clocks. Two reference outputs are available equal to the crystal frequency. Plus the IOAPIC output powered by VDDL1. One 48 MHz for USB, and one 24 MHz clock for Super IO. Spread Spectrum built in at ±0.25% modulation to reduce the EMI. Serial programming I2C interface allows changing functions, stop clock programing and Frequency selection. Additionally, the device meets the Pentium power-up stabilization, which requires that CPU and PCI clocks be stable within 2ms after power-up. It is not recommended to use I/O dual function pin for the slots (ISA, PIC, CPU, DIMM). The add on card might have a pull up or pull down. • • • • • • • • • • • • • • • 3.3V outputs: SDRAM, PCI, REF, 48/24MHz 2.5V outputs: CPU, IOAPIC 20 ohm CPU clock output impedance 20 ohm PCI clock output impedance Skew from CPU (earlier) to PCI clock - 1.5 to 4 ns, center 2.6 ns. No external load cap for CL=18pF crystals ±175 ps CPU clock skew 250ps (cycle to cycle) CPU jitter Smooth frequency switch, with selections from 66.8 to 133 MHz CPU. I2C interface for programming 3ms power up clock stable time Clock duty cycle 45-55%. 48 pin 300 mil SSOP package 3.3V operation, 5V tolerant inputs (with series R) <5ns propagation delay SDRAM from Buffer Input Pin Configuration High drive PCICLK and SDRAM outputs typically provide greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs typically provide better than 1V/ns slew rate into 20pF loads while maintaining 50 ±5% duty cycle. The REF and 24 and 48 MHz clock outputs typically provide better than 0.5V/ns slew rates into 20pF. Block Diagram PLL2 48MHz 24MHz /2 X1 X2 XTAL OSC IOAPIC STOP BUFFER IN 2 REF(0:1) 48-Pin SSOP * Internal Pull-up Resistor of 240K to VDD ** Internal Pull-down resistor of 240K to GND CPUCLK_F PLL1 Spread Spectrum FS(0:3) 4 MODE CPUCLK 1 STOP STOP LATCH 12 SDRAM (0:11) SDRAM_F 4 POR CPU_STOP# PCI_STOP# Control Logic SDATA SCLK STOP 5 PCICLK (0:4) PCICLKF VDDREF = REF (0:1), X1, X2 VDDPCI = PCICLK_F, PCICLK(0:4) VDDSDR = SDRAM (0:12), supply for PLL core VDD48 = 24MHz, 48MHz VDDLIOAPIC = IOAPIC VDDLCPU = CPUCLK 1, CPUCLK_F Config. Reg. 9248-90 Rev C 4/19/00 PCI CLOCK DIVDER Power Groups Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-90 Pin Descriptions PIN NUMBER 1 P I N NA M E VDDREF REF0 TYPE PWR OUT 2 PCI_STOP#1 3,9,16,22, 33,39,45 GND IN PWR 4 X1 IN 5 X2 OUT VDDPCI PWR PCICLK_F OUT 6,14 7 MODE 2 IN PCICLK0 OUT PCICLK1 OUT FS3 8 10 IN 2 FS4 2 IN 11, 12, 13 PCICLK(2:4) OUT 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 BUFFER IN IN 25 26 DESCRIPTION Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) PCI clock output. Syncheronous to CPU clocks with 1-48ns skew (CPU early) Frequency select pin. Latched Input. PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM (11:0) OUT SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). VDDSDR SDATA SCLK PWR IN IN Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz OUT 24MHz output clock FS2 48MHz FS02 IN OUT IN Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input 27 VDD48 PWR Power for 24 & 48MHz output buffers and fixed PLL core. 40 SDRAM_F OUT 41 CPU_STOP#1 42 43 44 VDDLCPU CPUCLK1 CPUCLK_F REF1 FS22 I OA P I C V D D L I OA P I C Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK1, IOAPIC & SDRAM (0:11) at logic "0" level when driven low. Supply for CPU clocks, either 2.5V or 3.3V nominal CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Free running CPU clock. Not affected by the CPU_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L 1 . Supply for IOAPIC, either 2.5 or 3.3V nominal 46 47 48 IN PWR OUT OUT OUT IN OUT PWR Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 2 ICS9248-90 Mode Pin - Power Management Input Control MODE, Pin 7 (Latched Input) Pin 2 PCI_STOP# (Input) REF0 (Output) 0 1 Functionality VDD = 3.3V±5%, VDDL = 2.5V±5% TA=0 to 70°C Crystal (X1, X2) = 14.31818MHz FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 66.82 68.01 71.99 75.00 78.00 80.00 82.00 83.00 84.00 85.01 85.91 86.99 88.00 89.01 90.00 90.99 91.99 93.07 94.00 95.00 96.00 97.01 98.01 98.99 100.23 102.02 104.00 106.00 108.01 109.99 124.00 132.99 PCI MHz 33.40 34.00 35.99 37.49 38.99 39.99 41.00 41.50 41.99 42.50 42.95 43.49 43.99 44.50 44.99 45.49 30.66 31.02 31.33 31.66 31.99 32.33 32.67 32.99 33.41 34.01 34.66 35.33 36.00 36.66 30.99 33.25 3 ICS9248-90 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = 0) Bit Description Bit (2, 7:4) 0 Bit (2, 7:4) 0 0 0 0 PWD CPUCLK MHz PCICLK MHz 66.82 33.40 34.00 0 0 0 0 1 68.01 0 0 0 1 0 71.99 35.99 0 0 0 1 1 75.00 37.49 0 0 1 0 0 78.00 38.99 0 0 1 0 1 80.00 39.99 0 0 1 1 0 82.00 41.00 41.50 0 0 1 1 1 83.00 0 1 0 0 0 84.00 41.99 0 1 0 0 1 85.01 42.50 0 1 0 1 0 85.91 42.95 0 1 0 1 1 86.99 43.49 0 1 1 0 0 88.00 43.99 44.50 0 1 1 0 1 89.01 0 1 1 1 0 90.00 44.99 0 1 1 1 1 90.99 45.49 1 0 0 0 0 91.99 30.66 1 0 0 0 1 93.07 31.02 1 0 0 1 0 94.00 31.33 1 0 0 1 1 95.00 31.66 1 0 1 0 0 96.00 31.99 1 0 1 0 1 97.01 32.33 1 0 1 1 0 98.01 32.67 1 0 1 1 1 98.99 32.99 1 1 0 0 0 100.23 33.41 1 1 0 0 1 102.02 34.01 34.66 1 1 0 1 0 104.00 1 1 0 1 1 106.00 35.33 1 1 1 0 0 108.01 36.00 1 1 1 0 1 109.99 36.66 1 1 1 1 0 124.00 30.99 1 1 1 1 1 132.99 33.25 XXX Note1 Bit 3 0-Frequency is selected by hardware select, latched inputs 1-Frequency is selected by Bit 7:4,2 0 Bit 1 0- Normal 1- Spread spectrum enable 1 Bit 0 0- Running 1- Tristate all outputs 0 Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. 4 ICS9248-90 Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 40 43 44 PWD X X 1 1 1 1 1 1 Description Latched FS2# Latched FS4# (Reserved) (Reserved) SDRAM12 (Act/Inact) (Reserved) CPUCLK1 (Act/Inact) CPUCLK_F (Act/Inact) Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 7 14 12 11 10 8 PWD 1 1 1 1 1 1 1 1 Description (Reserved) PCICLK_F (Act/Inact) (Reserved) PCICLK4 (Act/Inact) PCICLK3 (Act/Inact) PCICLK2 (Act/Inact) PCICLK1 (Act/Inact) PCICLK0 (Act/Inact) Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 26 25 21,20,18,17 32,31,29,28 38,37,35,34 PWD Description X MODE# X Latched FS0# 1 48MHz (Act/Inact) 1 24 MHz (Act/Inact) 1 (Reserved) 1 SDRAM (8:11) (Active/Inactive) 1 SDRAM (4:7) (Active/Inactive) 1 SDRAM (0:3) (Active/Inactive) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 5 ICS9248-90 Byte 4: Reserved Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # - PWD 1 1 1 1 X 1 X 1 Description (Reserved) (Reserved) (Reserved) (Reserved) Latched FS1# (Reserved) Latched FS3# (Reserved) Byte 5: Peripheral Active/Inactive Register (1 = enable, 0 = disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # 47 46 2 PWD 1 1 1 1 1 1 1 1 Description (Reserved) (Reserved) (Reserved) IOAPIC0 (Act/Inact) (Reserved) (Reserved) REF1 (Act/Inact) REF0 (Act/Inact) Notes: 1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions. 6 ICS9248-90 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 7.0 V GND –0.5 V to VDD +0.5 V 0°C to +70°C 115°C –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD, VDDL = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Clk Stabilization 1 1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 IDD3.3OP124 IDD3.3OP133 Fi CIN CINX TSTAB CONDITIONS VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz CL = 0 pF; Select @ 124MHz CL = 0 pF; Select @ 133MHz VDD = 3.3 V Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq. MIN 2 VSS-0.3 TYP 12 0.1 2.0 -100 87 120 144 149 14.318 27 36 -5 -200 MAX UNITS VDD+0.3 V 0.8 V µA 5 µA µA 170 mA 180 mA 16 MHz 5 45 pF pF 3 ms Guaranteed by design, not 100% tested in production. Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70º C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Operating Supply Current 1 Skew 1 SYMBOL IDD2.5OP 66 IDD2.5OP 100 IDD2.5OP 124 IDD2.5OP 133 tCP U-P CI CONDITIONS CL = 0 pF; Select @ 66.8 MHz CL = 0 pF; Select @ 100 MHz CL = 0 pF; Select @ 124 MHz CL = 0 pF; Select @ 133 MHz VT = 1.5 V; VTL = 1.25 V Guaranteed by design, not 100% tested in production. 7 MIN 1.5 TYP 7 10 11 14 MAX 30 30 30 30 UNITS 2.7 4 ns mA ICS9248-90 Electrical Characteristics - CPUCLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current SYMBOL VOH2B VOL2B IOH2B IOL2B Rise Time tr2B1 VOL = 0.4 V, VOH = 2.0 V 1.1 1.6 ns Fall Time tf2B 1 VOH = 2.0 V, VOL = 0.4 V 1.1 1.6 ns Duty Cycle d t2B1 VT = 1.25 V, Freq. < 124 MHz VT = 1.25 V, Freq. >= 124 MHz 49 47 55 52 % % Skew tsk2B1 VT = 1.25 V 115 175 ps Jitter, One Sigma VT = 1.25 V 36 150 ps Jitter, Absolute tj1σ2B1 tjabs2B1 130 +250 ps Jitter, Cycle-to-cycle tjcyc-cyc2B1 140 250 ps 1 CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 19 VT = 1.25 V VT = 1.25 V 45 40 -250 TYP 2.3 0.31 -36 26 MAX UNITS V 0.4 V -19 mA mA Guaranteed by design, not 100% tested in production. Electrical Characteristics - SDRAM TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current CONDITIONS IOH = -25 mA IOL = 20 mA VOH = 2.0 V VOL = 0.8 V Tr3 VOL = 0.4 V, VOH = 2.4 V Fall Time Tf3 1 VOH = 2.4 V, VOL = 0.4 V Duty Cycle Dt3 1 VT = 1.5 V Tsk1 Tprop VT = 1.5 V VT = 1.5 V 1 Skew Propagation Delay MIN 2.4 41 1 Rise Time 1 SYMBOL VOH3 VOL3 IOH3 IOL3 45 Guarenteed by design, not 100% tested in production. 8 TYP 2.85 0.35 -60 44 MAX UNITS V 0.4 V -40 mA mA 1.5 2.4 ns 1.6 2.2 ns 51 55 % 220 2.8 500 4 ps ns ICS9248-90 Electrical Characteristics - PCICLK TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 1 Skew Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH1 VOL1 IOH1 IOL1 CONDITIONS IOH = -11 mA IOL = 9.4 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 25 TYP 3.1 0.17 -60 44 MAX UNITS V 0.4 V -22 mA mA tr1 VOL = 0.4 V, VOH = 2.4 V 1.87 2.6 ns tf1 VOH = 2.4 V, VOL = 0.4 V 1.5 2.3 ns d t1 VT = 1.5 V 49 55 % tsk1 VT = 1.5 V 124 500 ps tj1 σ1 VT = 1.5 V 70 150 ps tjabs1 tjcyc-cyc1 VT = 1.5 V VT = 1.5 V 160 500 ps 130 400 ps 45 -500 Guaranteed by design, not 100% tested in production. Electrical Characteristics - IOAPIC TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH4B VOL4B IOH4B IOL4B CONDITIONS IOH = -8 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V MIN 2 19 TYP 2.3 0.31 -25 27 MAX UNITS V 0.4 V -15 mA mA Tr4B VOL = 0.4 V, VOH = 2.0 V 1.4 2.2 ns Tf4B VOH = 2.0 V, VOL = 0.4 V 1.3 2 ns Dt4B VT = 1.25 V 52 55 % Tj1 σ4B VT = 1.25 V 175 350 ps Tjabs4B VT = 1.25 V VT = 1.25 V 395 800 ps 475 800 ps tjcyc-cyc4B 45 -800 Guaranteed by design, not 100% tested in production. 9 ICS9248-90 Electrical Characteristics - REF1:0 TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 10 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 TYP 2.9 0.33 -30 23 MAX UNITS V 0.4 V -22 mA mA tr5 VOL = 0.4 V, VOH = 2.4 V 2.1 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 2.1 4 ns d t5 VT = 1.5 V 52 55 % tj1 σ5 VT = 1.5 V 200 400 ps tjabs5 tjcyc-cyc5 VT = 1.5 V VT = 1.5 V 520 800 ps 790 1300 ps TYP 2.9 0.3 -34 30 MAX UNITS V 0.4 V -22 mA mA 45 -800 Guaranteed by design, not 100% tested in production. Electrical Characteristics - 24MHz, 48MHz TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time 1 1 Duty Cycle 1 Jitter, One Sigma 1 1 Jitter, Absolute Jitter, Cycle-to-cycle1 1 SYMBOL VOH5 VOL5 IOH5 IOL5 CONDITIONS IOH = -12 mA IOL = 12 mA VOH = 2.0 V VOL = 0.8 V MIN 2.4 16 tr5 VOL = 0.4 V, VOH = 2.4 V 1.6 4 ns tf5 VOH = 2.4 V, VOL = 0.4 V 1.7 4 ns d t5 VT = 1.5 V 51.6 55 % tj1 σ5 VT = 1.5 V 100 400 ps tjabs5 VT = 1.5 V VT = 1.5 V 250 800 ps 345 1000 ps tjcyc-cyc5 45 -800 Guaranteed by design, not 100% tested in production. 10 ICS9248-90 General I2C serial interface information The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note. How to Write: How to Read: Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit How to Write: Controller (Host) Start Bit Address D2(H) ICS (Slave/Receiver) How to Read: Controller (Host) Start Bit Address D3(H) ACK Dummy Command Code ACK ICS (Slave/Receiver) ACK Byte Count Dummy Byte Count ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK ACK Stop Bit Byte 0 Byte 0 Byte 1 Byte 1 Byte 2 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4 Byte 5 Byte 5 Stop Bit Notes: 1. 2. 3. 4. 5. 6. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown. 11 ICS9248-90 Shared Pin Operation Input/Output Pins Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor. The I/O pins designated by (input/output) on the ICS924890 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Via to VDD Programming Header 2K Via to Gnd Device Pad 8.2K Clock trace to load Series Term. Res. Fig. 1 12 ICS9248-90 CPU_STOP# Timing Diagram CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-90. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks. Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS9248-90. 3. IOAPIC output is Stopped Glitch Free by CPUSTOP# going low. 4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS9248-90 CPU_STOP# signal. SDRAM (0:11) are controlled as shown. 5. All other clocks continue to run undisturbed. 13 ICS9248-90 PCI_STOP# Timing Diagram PCI_STOP# is an asynchronous input to the ICS9248-90. It is used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-90 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock. Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS9248. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state. 14 ICS9248-90 Ferrite Bead General Layout Precautions: 1) Use a ground plane on the top routing layer of the PCB in all areas not used by traces. VDD C2 22µF/20V Tantalum C2 22µF/20V Tantalum 1 48 2 47 3 46 4 45 5 44 Ferrite Bead VDD C3 2) Make all power traces and ground traces as wide as the via pad for lower inductance. 2 C1 C1 Notes: 1 All clock outputs should have provisions for a 15pf capacitor between the clock output and series terminating resistor. Not shown in all places to improve readability of diagram. 2.5V Power Route 1 Clock Load C3 6 43 7 42 8 41 9 40 10 39 C3 3.3V Power Route 2 Optional crystal load capacitors are recommended. They should be included in the layout but not inserted unless needed. Connections to VDD: 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 Ground 3.3V Power Route = Routed Power = Ground Connection Key (component side copper) = Ground Plane Connection = Power Route Connection = Solder Pads = Clock Load 15 ICS9248-90 Ordering Information ICS9248yF-90-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device 16 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.