IDT709149S HIGH-SPEED 36K (4K x 9-BIT) SYNCHRONOUS PIPELINED DUAL-PORT SRAM Features ◆ ◆ ◆ ◆ ◆ 13ns cycle time, 76MHz operation in pipeline mode Self-timed write allows for fast cycle times TTL-compatible, singles 5V (±10%) power supply Clock Enable feature Guaranteed data output hold times Industrial temperature range (40°C to +85°C) is available for selected speeds. ◆ Architecture based on Dual-Port SRAM cells Allows full simultaneous access from both ports High-speed clock-to-data output times Commercial: 8/10/12ns (max.) Low-power operation IDT709149S Active: 1500mW (typ.) Standby: 75mW (typ.) 4K X 9 bits Synchronous operation 4ns setup to clock, 1ns hold on all control, data, and address inputs Data input, address, and control registers Fast 8ns clock to data out ◆ ◆ ◆ ◆ Description The IDT709149 is a high-speed 4K x 9 bit synchronous Dual-Port SRAM. The memory array is based on Dual-Port memory cells to allow simultaneous access from both ports. Registers on control, data, and address inputs provide low set-up and hold times. The timing latitude provided by this approach will allow systems to be designed with very Functional Block Diagram WRITE LOGIC SENSE AMPS MEMOR MEMORY YARRAY ARRAY DECODER DECODER REG en OEL CLKL WRITE LOGIC REGISTER REGISTER I/O0-8L I/O0-8R FT/PIPEDR 0/1 0 SENSE AMPS 1 REG en OER CLKR CLKENR CLKENL R/WL REG CEL Selftimed Write Logic Selftimed Write Logic A0L-A11L A0R-A11R REG R/WR CER 3494 drw 01 SEPTEMBER 1999 1 ©1999 Integrated Device Technology, Inc. DSC-3494/4 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM short cycle times. This device has been optimized for applications having unidirectional data flow or bi-directional data flow in bursts, by utilizing input data registers. The IDT709149 utilizes a 9-bit wide data path to allow for parity at the user's option. This feature is especially useful in data communication applications where it is necessary to use a parity bit for transmission/reception error checking. Industrial and Commercial Temperature Ranges Fabricated using IDTs CMOS high-performance technology, these Dual-Ports typically operate on only 800mW of power at maximum high-speed clock-to-data output times as fast as 8ns. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. The IDT709149 is packaged in an 80-pin TQFP. N/C N/C A5L A4L A3L A2L A1L A0L CLKENL CLKL CLKR CLKENR A0R A1R A2R A3R A4R A5R A6R N/C Pin Configurations(1,2,3) Reference N/C A6L A7L A8L A9L A10L A11L N/C OEL VCC VCC R/WL N/C N/C CEL GND I/O8L I/O7L I/O6L N/C 1 2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 3 58 4 57 5 56 6 55 7 IDT709149PF PN80-1(4) 8 9 10 80-Pin TQFP Top View(5) 11 12 54 53 52 51 50 49 13 48 14 47 15 46 16 45 17 44 18 43 19 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 N/C A7R A8R A9R A10R A11R N/C , OER FT/PIPEDR GND GND R/WR N/C N/C CER GND I/O8R I/O7R I/O6R N/C N/C N/C I/O5L VCC I/O4L I/O3L I/O2L I/O1L I/O0L GND GND I/O0R I/O1R I/O2R I/O3R VCC I/O4R I/O5R N/C N/C 3494 drw 02 NOTES: 1. All VCC pins must be connected to power supply. 2. All ground pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4, This package code is used to reference the package diagram. 5. This text does not indicate the orientaion of the actual part-marking. 6.42 2 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Absolute Maximum Ratings(1) Symbol Rating Commercial & Industrial Unit Terminal Voltage with Respect to GND -0.5 to +7.0 V V TERM(2) Terminal Voltage -0.5 to VCC V TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o IOUT DC Output Current V TERM(2) Industrial and Commercial Temperature Ranges Maximum Operating Temperature and Supply Voltage(1,2) Grade GND Vcc 0OC to +70OC 0V 5.0V + 10% -40OC to +85OC 0V 5.0V + 10% Ambient Temperature Commercial 50 Industrial C 3494 tbl 02 NOTES: 1. This is the parameter TA. 2. Industrial temperature: for specific speeds, packages and powers contact your sales office. C mA 3494 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%. Recommended DC Operating Conditions Symbol VCC Supply Voltage GND Ground V IH Input High Voltage V IL Capacitance (TA = +25°C, f = 1.0MHz) Symbol Parameter Conditions Max. Unit CIN Input Capacitance VIN = 3dV 8 pF COUT Output Capacitance VOUT = 3dV 9 pF Parameter Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ (1) -0.5 (2) 6.0 0.8 ____ V V 3494 tbl 03 NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%. 3494 tbl 04 NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V ± 10%) 709149S Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current(1) V CC = 5.5V, VIN = 0V to V CC ___ 10 µA |ILO| Output Leakage Current VOUT = 0V to V CC ___ 10 µA V OL Output Low Voltage IOL = +4mA ___ 0.4 V V OH Output High Voltage IOH = -4mA 2.4 ___ V 3494 tbl 05 NOTE: 1. At V CC < 2.0V, input leakages are undefined 6.42 3 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4,5) (VCC = 5V ± 10%) 709149S8 Com'l Only Symbol Parameter ICC ISB 1 ISB 2 ISB 3 ISB 4 Test Condition Version 709149S10 Com'l Only 709149S12 Com'l Only Typ. Max. Typ. Max. Typ. Max. Unit COM'L ____ 320 ____ 310 ____ 300 mA IND ____ ____ ____ ____ ____ ____ Dynamic Operating Current (Both Ports Active) CEL and CER = VIL, Outputs Open f = fMA X(1) Standby Current (Both Ports - TTL Level Inputs) CEL and CER = VIH f = fMA X(1) COM'L ____ 150 ____ 150 ____ 140 IND ____ ____ ____ ____ ____ ____ Standby Current (One Port - TTL Level Inputs) CE"A " = VIL and CE"B" = VIH(3) Active Port Outputs Open, f=fMA X(1) COM'L ____ 230 ____ 220 ____ 210 IND ____ ____ ____ ____ ____ ____ Full Standby Current (Both Ports - All CMOS Level Inputs) CEL and CER > VCC - 0.2V, V IN > V CC - 0.2V or V IN < 0.2V, f = 0(2) COM'L ____ 15 ____ 15 ____ 15 IND ____ ____ ____ ____ ____ ____ Full Standby Current (One Port - All CMOS Level Inputs) CE"A " < 0.2V and CE"B " > VCC - 0.2V(3) V IN > V CC - 0.2V or V IN < 0.2V Active Port Outputs Open, f = fMA X(1) COM'L ____ 220 ____ 210 ____ 200 IND ____ ____ ____ ____ ____ ____ mA mA mA mA 3494 tbl 0 6 NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCLK, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. ICC DC = 150mA (Typ). 5. Industrial temperature: for specific speeds, packages and powers contact your sales office. AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Max. Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Figures 1,2 and 3 8 3494 tbl 07 7 9pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance 6 5V 5V 893Ω ∆tCD (Typical, ns) 893Ω 347Ω 30pF 4 3 2 DATAOUT DATAOUT 5 347Ω 1 5pF* 0 3494 drw 03 Figure 1. AC Output Test load. 3494 drw 04 , Figure 2. Output Test Load (For tCKLZ , tCKHZ, tOLZ, and tOHZ). *Including scope and jig. 6.42 4 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF) 3494 drw 05 Figure 3. Typical Output Derating (Lumped Capacitive Load). , IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing)(4) (Commercial: V CC = 5V ± 10%, TA = 0°C to +70°C) 709149S8 Com'l Only Symbol tCYC1 tCYC2 tCH1 Parameter Clock Cycle Time (Flow-Through) (3) Clock Cycle Time (Pipelined) (3) 709149S10 Com'l Only 709124S12 Com'l Only Min. Max. Min. Max. Min. Max. Unit 16 ____ 20 ____ 20 ____ ns ns 13 ____ 15 ____ 16 ____ (3) 6 ____ 7 ____ 8 ____ ns (3) 6 ____ 7 ____ 8 ____ ns Clock High Time (Flow-Through) tCL1 Clock Low Time (Flow-Through) tCH2 Clock High Time (Pipelined) (3) 6 ____ 6 ____ 6 ____ ns tCL2 (3) 6 ____ 6 ____ 6 ____ ns ____ 12 ____ 15 ____ 20 ns ____ 8 ____ 10 ____ 12 ns tCD1 Clock Low Time (Pipelined) Clock to Data Valid (Flow-Through) (3) (3) tCD2 Clock to Data Valid (Pipelined) tS Registered Signal Set-up Time 4 ____ 4 ____ 5 ____ ns tH Registered Signal Hold Time 1 ____ 1 ____ 1 ____ ns tDC Data Output Hold After Clock High 1 ____ 1 ____ 1 ____ ns 2 ____ 2 ____ 2 ____ ns ____ 7 ____ 7 ____ 9 ns ____ 8 ____ 8 ____ 10 ns 0 ____ 0 ____ 0 ____ ns ____ 7 ____ 7 ____ 9 ns 4 ____ 5 ____ ns ns tCKLZ Clock High to Output Low-Z (1,2) (1,2) tCKHZ Clock High to Output High-Z tOE Output Enable to Output Valid tOLZ (1,2) Output Enable to Output Low-Z (1,2) tOHZ Output Disable to Output High-Z tSCK Clock Enable, Disable Set-Up Time 4 ____ tHCK Clock Enable, Disable Hold Time 1 ____ 1 ____ 1 ____ tCWDD Write Port Clock High to Read Data Delay ____ 25 ____ 30 ____ 35 ns 3494 tbl 08 NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. The Pipelined output parameters (tCYC2, t CD2) always apply to the Left Port. The Right Port uses the Pipelined tCYC2 and tCD2 when FT/PIPEDR = VIH and the FlowThrough parameters (t CYC1, tCD1 ) when FT/PIPEDR = VIL. 4. Industrial temperature: for specific speeds, packages and powers contact your sales office. 6.42 5 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Flow-Through Output on Right Port (FT/PipedR = VIL) tCYC1 tCH1 CLK tCL1 tSCK tHCK tSCK CLKEN tS tH CE R/W ADDRESS An An + 1 An + 2 An + 3 tCKHZ (1) tDC tCD1 DATAOUT Qn Qn + 1 tCKLZ (1) tOHZ Qn + 1 (1) tOLZ (1) tOE OE 3494 drw 06 Timing Waveform of Left Port Write to Flow-Through Right Port Read (FT/Piped R = V IL)(2,3) CLK "L" R/W "L" ADDR "L" DATA IN "L" MATCH NO MATCH VALID VALID tCCS CLK "R" R/W "R" ADDR "R" NO MATCH MATCH tCWDD tCD1 DATA OUT "R" VALID VALID tDC 3494 drw 07 NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. CEL = CER = VIL, CLKENL = CLKENR = VIL 3. OE = VIL for the reading port, port 'R'. 6.42 6 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Read Cycle for Pipelined Operation (Left Port; Right Port when FT/PipedR = VIH)(3) tCYC2 tCH2 tCL2 CLK CE tS tH tS tH tS tH R/W An ADDRESS An + 1 (1 Latency) An + 2 tDC tCD2 DATAOUT Qn tCKLZ OE An + 3 tCD2 Qn + 1 (1) tOHZ Qn + 2 (1) tOLZ (1) (2) tOE 3494 drw 08 NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. CLKEN L and CLKENR = V IL. 6.42 7 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL) tCYC2 tCH2 tCL2 CLK CE tS tH tS R/W ADDRESS tS tH tH An tS tH An +1 An + 2 tS DATAIN An + 4 An + 3 An + 2 tH Dn + 2 tCD2 (2) tCKHZ (1) (1) tCKLZ tCD2 Qn + 3 Qn DATAOUT (3) READ NOP WRITE READ 3494 drw 09 Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled) tCH2 tCYC2 tCL2 CLK tS tH CE tS R/W tS tH An ADDRESS tS tH An +1 An + 2 tH tS DATAIN Dn + 3 Dn + 2 tCD2 (2) An + 3 An + 4 An + 5 tH tCKLZ(1) tCD2 Qn DATAOUT Qn + 4 (1) tOHZ OE WRITE READ NOTES: 1. Transition is measured ±200mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 3. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity. 6.42 8 READ 3494 drw 10 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Functional Description The IDT709149 provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide very short set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal. An asynchronous output enable is provided to ease asynchronous bus interfacing. The internal write pulse width is dependent only on the low to high transitions of the clock signal to initiate a write allowing the shortest Industrial and Commercial Temperature Ranges possible realized cycle times. Clock enable inputs are provided to stall the operation of the address and data input registers without introducing clock skew for very fast interleaved memory applications. A HIGH on the CE input for one clock cycle will power down the internal circuitry to reduce static power consumption. When piplelined mode is enabled, two cycles are required with CE LOW to reactivate the outputs. Truth Table I: Read/Write Control(1) Inputs Synchronous(3) Outputs Asynchronous Mode CLK CE R/W OE I/O 0-8 ↑ H X X High-Z DeselectedPower Down ↑ L L X DATAIN Selected and Write Enable ↑ L H L DATA OUT ↑ X X H High-Z Read Selected and Data Output Enabled Read (1 Latency) Data I/O Disabled 3494 tbl 09 Truth Table II: Clock Enable Function Table(1) Inputs Register Outputs(4) Register Inputs Operating Mode CLK(3) CLKEN(2) ADDR DATAIN ADDR DATAOUT Load "1" ↑ L H H H H Load "0" ↑ L L L L L Hold (do nothing) ↑ H X X NC NC X H X X NC NC 3494 tbl 10 NOTES: 1. 'H' = HIGH voltage level steady state, 'h' = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'L' = LOW voltage level steady state 'l' = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition, 'X' = Don't care, 'NC' = No change 2. CLKEN = VIL must be clocked in during Power-Up. 3. Control signals are initialted and terminated on the rising edge of the CLK, depending on their input level. When R/W and CE are LOW, a write cycle is initiated on the LOWto-HIGH transition of the CLK. Termination of a write cycle is done on the next LOW-to-HIGH transistion of the CLK. 4. The register outputs are internal signals from the register inputs being clocked in or disabled by CLKEN. 6.42 9 IDT709149S High-Speed 36K (4K x 9-bit) Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Ordering Information IDT XXXX A 999 A A Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to +70°C) PF 80-pin TQFP (PN80-1) 8 10 12 Commercial Only Commercial Only Commercial Only S Standard Power 709149 36K (4K x 9-Bit) Synchronous Pipelined Dual-Port RAM Speed in nanoseconds 3494 drw 11 NOTE: 1. Industrial temperature range is available. For specific speeds, packages and poewrs contact your sales office. Datasheet Document History 3/8/99: 6/3/99: 9/1/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Added additional notes to pin configurations Changed drawing format Removed Preliminary CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 6.42 10 for Tech Support: 831-754-4613 [email protected]