IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • First-ln/First-Out Dual-Port memory—45MHz • 64 x 5 organization • Low-power consumption — Active: 200mW (typical) • RAM-based internal structure allows for fast fall-through time • Asynchronous and simultaneous read and write • Expandable by bit width • Cascadable by word depth • Half-Full and Almost-Full/Empty status flags • IDT72413 is pin and functionally compatible with the MMI67413 • High-speed data communications applications • Bidirectional and rate buffer applications • High-performance CMOS technology • Available in plastic DIP, CERDIP and SOIC • Military product compliant to MIL-STD-883, Class B • Industrial temperature range (-40oC to +85oC) is available, tested to military electrical specifications The IDT72413 is a 64 x 5, high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis. It is expandable in bit width. All speed versions are cascadable in depth. The FIFO has a Half-Full Flag, which signals when it has 32 or more words in memory. The Almost-Full/Empty Flag is active when there are 56 or more words in memory or when there are 8 or less words in memory. The IDT72413 is pin and functionally compatible to the MMI67413. It operates at a shift rate of 45MHz. This makes it ideal for use in high-speed data buffering applications. The IDT72413 can be used as a rate buffer, between two digital systems of varying data rates, in high-speed tape drivers, hard disk controllers, data communications controllers and graphics controllers. The IDT72413 is fabricated using IDTs high-performance CMOS process. This process maintains the speed and high output drive capability of TTL circuits in low-power CMOS. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B. FUNCTIONAL BLOCK DIAGRAM OUPUT ENABLE (OE) DATA IN (D 0-4 ) FIFO INPUT STAGE 64 x 5 MEMORY ARRAY FIFO OUTPUT STAGE INPUT CONTROL LOGIC REGISTER CONTROL LOGIC OUTPUT CONTROL LOGIC DATA OUT (Q 0-4 ) (MR) MASTER RESET INPUT READY SHIFT IN (IR) (SO) (SI) (OR) FLAG CONTROL LOGIC SHIFT OUT OUPUT READY HALF-FULL (HF) ALMOST-FULL/ EMPTY (AF/E) 2748 drw 01 The IDT logo is a registered trademark of Integrated Device Technology,Inc. FAST is a trademark of National Semiconductor, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. 5.02 DECEMBER 1996 DSC-2748/7 1 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION OE HF IR SI D0 D1 D2 D3 D4 GND 1 20 2 19 3 4 5 6 7 18 P20-1, C20-1, & SO20-2 17 16 15 14 8 13 9 12 10 11 Vcc AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR 2748 drw 02 DIP/SOIC TOP VIEW Symbol Rating Commercial Military Unit VTERM Terminal Voltage with Respect to GND -0.5 to +7.0 -0.5 to +7.0 V TA Operating Temperature 0 to +70 -55 to +125 °C TBIAS Temperature Under Bias -55 to +125 -65 to +135 °C TSTG Storage Temperature -55 to +125 -65 to +150 °C IOUT DC Output Current 50 50 mA NOTE: 2748 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE (TA = +25°C, f = 1.0MHz) Symbol Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 0V 5 pF COUT Output Capacitance VOUT = 0V 7 pF NOTE: 1. This parameter is sampled and not 100% tested. 2. Characterized values, not currently listed. 2748 tbl 02 RECOMMENDED OPERATING CONDITIONS Symbol Min. Typ. VCC Military Supply Voltage Parameter 4.5 5.0 5.5 V VCC Commercial Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.0 — — V VIL(1) Input Low Voltage — — 0.8 V NOTE: 1. 1.5V undershoots are allowed for 10ns once per cycle. Max. Unit 2748 tbl 03 5.02 2 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Symbol Test Conditions Min. Max. Unit IIL Low-Level Input Current Parameter VCC = Max., GND ≤ VI ≤ VCC -10 — µA IIH High-Level Input Current VCC = Max., GND ≤ VI ≤ VCC — 10 µA VOL Low-Level Output Current VCC = Min. IOL (Q0-4) Mil. — 0.4 V 2.4 — V -20 -110 mA µA 12mA Com'l. 24mA IOL (IR, OR)(1) 8mA IOL (HF, AF/E) VOH IOS (2) IHZ High-Level Output Current –4mA IOH (IR, OR) –4mA IOH (HF, AF/E) –4mA Output Short-Circuit Current VCC = Max. VO = 0V Off-State Output Current VCC = Max. VO = 2.4V — 20 VCC = Max. VO = 0.4V -20 — VCC = Max., OE=HIGH Mil. Inputs LOW, f=25MHz Com'l. — — 70 60 ILZ ICC(3) 8mA VCC = Min. IOH (Q0-4) Supply Current mA NOTES: 2748 tbl 04 1. Care should be taken to minimize as much as possible the DC and capactive load on IR and OR when operating at frequencies above 25mHz. 2. Not more than one output should be shorted at a time and duration of the short circuit should not exceed one second. Guaranteed by design, but not currently tested. 3. For frequencies greater than 25MHz, ICC = 60mA + (1.5mA x [f - 25MHz]) commercial and ICC = 70mA + (1.5mA x [f - 25MHz]) military. OPERATING CONDITIONS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Commercial Symbol Parameters Figure IDT72413L45 Min. Max. Military & Commercial Military & Commercial IDT72413L35 Min. Max. IDT72413L25 Min. Max. Unit (1) Shift in HIGH Time 2 9 — 9 — 16 — ns tSIL(1) Shift in LOW TIme 2 11 — 17 — 20 — ns tIDS Input Data Set-up 2 0 — 0 — 0 — ns tIDH Input Data Hold Time 2 13 — 15 — 25 — ns tSOH(1) Shift Out HIGH Time 5 9 — 9 — 16 — ns tSOL Shift Out LOW Time 5 11 — 17 — 20 — ns tMRW Master Reset Pulse 8 20 — 30 — 35 — ns tMRS Master Reset Pulse to SI 8 20 — 35 — 35 — ns tSIH NOTE: 2748 tbl 05 1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. 5.02 3 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES AC ELECTRICAL CHARACTERISTICS (Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C) Symbol Parameters Figure Commercial Mil. & Com'l IDT72413L45 Min. Max. IDT72413L35 Min. Max. Mil. & Com'l IDT72413L25 Min. Max. Unit fIN Shift In Rate 2 — 45 — 35 — 25 MHz tIRL(1) Shift In ↑ to Input Ready LOW 2 — 18 — 18 — 28 ns tIRH(1) Shift In ↓ to Input Ready HIGH 2 — 18 — 20 — 25 ns fOUT Shift Out Rate 5 — 45 — 35 — 25 MHz tORL(1) Shift Out ↓ to Output Ready LOW 5 — 18 — 18 — 28 ns (1) Shift Out ↓ to Output Ready HIGH 5 — 19 — 20 — 25 ns tODH(1) Output Data Hold Previous Word 5 5 — 5 — 5 — ns tODS Output Data Shift Next Word 5 — 19 — 20 — 20 ns tPT Data Throughput or "Fall-Through" 4, 7 — 25 — 28 — 40 ns tMRORL Master Reset ↓ to Output Ready LOW 8 — 25 — 28 — 30 ns 8 — 25 — 28 — 30 ns tORH tMRIRH(3) Master Reset ↑ to Input Ready HIGH tMRIRL(2) Master Reset ↓ to Input Ready LOW 8 — 25 — 28 — 30 ns tMRQ Master Reset ↓ to Outputs LOW 8 — 20 — 25 — 35 ns tMRHF Master Reset ↓ to Half-Full Flag 8 — 25 — 28 — 40 ns tMRAFE Master Reset ↓ to AF/E Flag 8 — 25 — 28 — 40 ns Input Ready Pulse HIGH 4 5 — 5 — 5 — ns Ouput Ready Pulse HIGH 7 5 — 5 — 5 — ns Output Ready ↑ HIGH to Valid Data 5 — 5 — 5 — 7 ns tAEH Shift Out ↑ to AF/E HIGH 9 — 28 — 28 — 40 ns tAEL Shift In ↑ to AF/E 9 — 28 — 28 — 40 ns tAFL Shift Out ↑ to AF/E LOW 10 — 28 — 28 — 40 ns tAFH Shift In ↑ to AF/E HIGH 10 — 28 — 28 — 40 ns tHFH Shift In ↑ to HF HIGH 11 — 28 — 28 — 40 ns tHFL Shif Out ↑ to HF LOW 11 — 28 — 28 — 40 ns tPHZ(3) Output Disable Delay 12 — 12 — 12 — 15 ns 12 — 12 — 12 — 15 12 — 15 — 15 — 20 12 — 15 — 15 — 20 tIPH (3) tOPH(3) t ORD (3) tPLZ (3) tPLZ (3) tPHZ(3) Output Enable Delay ns NOTES: 2748 tbl 06 1. Since the FIFO is a very high-speed device, care must be taken in the design of the hardware and the timing utilized within the design. Device grounding and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding. A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended. 2. If the FIFO is full, (IR = HIGH), MR ↓ forces IR to go LOW, and MR ↑ causes IR to go HIGH. 3. Guaranteed by design but not currently tested. 5.02 4 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES STANDARD TEST LOAD AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels Output Load DESIGN TEST LOAD 5V 5V 2KΩ R1 1.5V TEST POINT OUTPUT See Figure 1 2748 tbl 07 R2 30pF* 30pF* 2748 drw 03 or equivalent circuit *Including scope and jig RESISTOR VALUES FOR STANDARD TEST LOAD IOL R1 R2 24mA 200Ω 300Ω 12mA 390Ω 760Ω 8mA 600Ω 1200Ω 2748 tbl 08 Figure 1. Output Load FUNCTIONAL DESCRIPTION: DATA OUTPUT The IDT72413, 65 x 5 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control; the read pointer is incremented by the falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO has an available memory location; Output Ready (OR) signals when there is valid data on the output. Output Enable (OE) provides the capability of three-stating the FIFO outputs. Data is shifted out on the HIGH-to-LOW transition of Shift Out (SO). This causes the internal read pointer to be advanced to the next word location. If data is present, valid data will appear on the outputs and Output Ready (OR) will go HIGH. If data is not present, Output Ready will stay LOW indicating the FIFO is empty. The last valid word read from the FIFO will remain at the FlFOs output when it is empty. When the FIFO is not empty Output Ready (OR) goes LOW on the LOW-to-HlGH transition of Shift Out. FIFO RESET The FIFO operates in a Fall-Through Mode when data gets shifted into an empty FIFO. After the fall-through delay the data propagates to the output. When the data reaches the output, the Output Ready (OR) goes HIGH. A Fall-Through Mode also occurs when the FIFO is completely full. When data is shifted out of the full FIFO a location is available for new data. After a fall-through delay, the lnput Ready goes HlGH. If Shift In is HIGH, the new data can be written to the FIFO. The fall-through delay of a RAMbased FIFO (one clock cycle) is far less than the delay of a Shift register-based FIFO. The FIFO must be reset upon power up using the Master Reset (MR) signal. This causes the FIFO to enter an empty state signified by Output Ready (OR) being LOW and Input Ready (IR) being HIGH. In this state, the data outputs (Q0-4) will be LOW. DATA INPUT Data is shifted in on the LOW-to-HIGH transition of Shift In (Sl). This loads input data into the first word location of the FIFO and causes the lnput Ready to go LOW. On the HlGHto-LOW transition of Shift In, the write pointer is moved to the next word position and Input Ready (lR) goes HlGH indicating the readiness to accept new data. If the FIFO is full, Input Ready will remain LOW until a word of data is shifted out. FALL-THROUGH MODE 5.02 5 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES INPUT READY(IR) When Input Ready is HIGH, the FIFO is ready for new input data to be written to it. When IR is LOW, the FIFO is unavailable for new input data, Input Ready is also used to cascade many FIFOs together, as shown in Figure 13 in the Applications section. SIGNAL DESCRIPTIONS: INPUTS: DATA INPUT (D0-4) Data input lines. The IDT72413 has a 5-bit data input. CONTROLS: SHIFT IN (SI) Shift In controls the input of the data into the FIFO. When SI is HIGH, data can be written to the FIFO via the D0-4 lines. The data has to meet set-up and hold time requirements with respect to the rising edge of SI. SHIFT OUT (SO) Shift Out controls the outputs data from the FIFO. MASTER RESET (MR) Master Reset clears the FIFO of any data stored within. Upon power up, the FIFO should be cleared with a Master Reset. Master Reset is active LOW. HALF-FULL FLAG (HF) Half-Full Flag signals when the FIFO has 32 or more words in it. OUTPUT READY (OR) When Output Ready is HIGH, the output (Q0-4) contains valid data. When OR is LOW, the FIFO is unavailable for new output data. Output Ready is also used to cascade many FIFOs together, as shown in Figure 13 in the Applications section. OUTPUT ENABLE (OE) Output Enable is used to enable the FIFO outputs onto a bus. Output Enable is active LOW. ALMOST-FULL/EMPTY FLAG (AFE) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words). OUTPUTS: DATA OUTPUT (Q0-4) Data output lines, three-state. The IDT72413 has a 5-bit output. TIMING DIAGRAMS 1/f IN t SIH SHIFT IN 1/f IN t SIL t IRH INPUT READY t IDH t IRL INPUT DATA t IDS 2748 drw 04 Figure 2. Input Timing (7) (2) SHIFT IN (4) (1) (5) (3) INPUT READY INPUT DATA (6) STABLE DATA 2748 drw 05 Figure 3. The Machanism of Shifting Data Into the FIFO NOTES: 1. Input Ready HIGH indicates space is available and a Shift In pulse may be applied. 2. Input Data is loaded into the FIFO. 3. Input Ready goes LOW indicating the FIFO is unavailable for new data. 4. The write pointer is incremented. 5. The FIFO is ready for the next word. 6. If the FIFO is full, then the Input Ready remains LOW. 7. Shift In pulses applied while Input Ready is LOW will be ignored (see Figure 4). 5.02 6 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING DIAGRAMS (Continued) (2) SHIFT OUT (3) (5) SHIFT IN (4) INPUT READY t PT (1) t IPH STABLE DATA INPUT DATA NOTES: 1. FIFO is initially full. 2. Shift Out pulse is applied. 3. Shift In is held HIGH. 4. As soon as Input Ready becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. Shift In should not go LOW until (tPT + tIPH). 2748 drw 06 Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH 1/f OUT t SOH SHIFT OUT 1/f OUT t SOL (2) t RH OUTPUT READY t ORD t ODS t ORL t ODH OUTPUT DATA A-DATA B-DATA C-DATA (1) 2748 drw 07 NOTES: 1. This data is loaded consecutively A, B, C. 2. Output data changes on the falling edge of SO after a valid Shift Out sequence, i.e., OR and SO are both high together. Figure 5. Output TIming SHIFT OUT (7) (2) (4) (1) (5) (3) OUTPUT READY OUTPUT DATA (6) A-DATA B-DATA A or B 2748 drw 08 NOTES: 1. Output Ready HIGH indicates that data is available and a Shift Out pulse may be applied. 2. Shift Out goes HIGH causing the next step. 3. Output Ready goes LOW. 4. Read pointer is incremented. 5. Output Ready goes HIGH indicating that new data (B) will be available at the FIFO outputs after tORD ns. 6. If the FIFO has only one word loaded (A DATA) , Output Ready stays LOW and the A-DATA remains unchanged at the outputs. 7. Shift Out pulses applied when Output Ready is LOW will be ignored. Figure 6. The Mechanism of Shifting Data Out of the FIFO 5.02 7 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING DIAGRAMS (Continued) SHIFT IN SHIFT OUT t PT OUTPUT READY (1) t OPH 2748 drw 09 NOTE: 1. FIFO initailly empty. Figure 7. tPT and tOPH Specification MASTER RESET (1) t MRW INPUT READY t MRIRL t MRIRH (1) OUTPUT READY t MRORL t MRS SHIFT IN DATA OUTPUTS t MRQ HALF-FULL FLAG t MRHF ALMOST FULL/ EMPTY FLAG 2748 drw 10 t MRAFE NOTE: 1. FIFO is partially full.. Figure 8. Master Reset Timing 5.02 8 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES TIMING DIAGRAMS (Continued) SHIFT OUT t SOH ALMOST FULL/EMPTY (1) t SIH t AEH SHIFT IN t AEL NOTE: 1. FIFO contains 9 words (one more than Almost-Empty). 2748 drw 11 Figure 9. tAEH and tAEL Specifications SHIFT IN t SIH ALMOST FULL/EMPTY (1) t SOH t AFH SHIFT OUT t AFL NOTE: 1. FIFO contains 55 words (one short of Almost-Full). 2748 drw 12 Figure 10. tAFH and tAFL Specifications SHIFT IN t SIH HALF-FULL (1) t SOH t HFH SHIFT OUT t HFL NOTE: 1. FIFO contains 31 words (one short of Half-Full). 2748 drw 13 Figure 11. tHFL and tHFH Specifications 3V VT OE VT 0V t PZL 4.5V (1) WAVEFORM 1 t PLZ 0.5V VT t PZH 1.5V V OL t PHZ (2) V OH 1.5V VT WAVEFORM 2 0V 0.5V 2748 drw 14 NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. 2. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. Figure 12. Enable and Disable 5.02 9 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS MILITARY AND COMMERCIAL TEMPERATURE RANGES APPLICATIONS OUTPUT ENABLE COMPOSITE INPUT READY SHIFT IN HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR HF IR SI D0 D1 D2 D3 D4 OE AF/E SO OR Q0 Q1 Q2 Q3 Q4 MR SHIFT OUT COMPOSITE OUTPUT READY MASTER RESET 2748 drw 15 NOTE: 1. FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs. Figure 13. 64 x 15 FIFO with IDT72413 8-BITS 8-BITS SYSTEM 1 ENBL SI TWO IDT72413 64 x 8 SI SO OR IR SYSTEM 2 IO RDY ALMOST-FULL/ EMPTY INTERRUPT INTERRUPT HALF-FULL FLAG 2748 drw 16 NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13. Figure 14. Application for IDT72413 for Two Asynchronous Systems 5.02 10 IDT72413 CMOS PARALLEL 64 x 5-BIT FIFO WITH FLAGS SHIFT IN INPUT READY DATA IN SI IR D0 D1 D2 D3 D4 MR MILITARY AND COMMERCIAL TEMPERATURE RANGES OR SO Q0 Q1 Q2 Q3 Q4 SI IR D0 D1 D2 D3 D4 MR OR SO Q0 Q1 Q2 Q3 Q4 MR OUTPUT READY SHIFT OUT DATA OUT 2748 drw 17 NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices. Figure 15. 128 x 5 Depth Expansion ORDERING INFORMATION IDT XXXXX X X X X Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0°C to+70°C) B Military (–55°C to+125°C)Compliant to MIL-STD-883, Class B P D SO Plastic DIP (300 mils wide) Cerdip (300 mils wide) Small Outline IC 45 35 25 Com’l. Only Com'l. and Mil Com’l. and Mil L Low Power 72413 64 x 5 FIFO 5.02 Shift Frequency (fs)Speed in MHz 2748 drw 18 11