IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: IDT74ALVCH16260 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK(o) (Output Skew) < 250ps • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • VCC = 3.3V ± 0.3V, Normal Range • VCC = 2.7V to 3.6V, Extended Range • VCC = 2.5V ± 0.2V µ W typ. static) • CMOS power levels (0.4µ • Rail-to-Rail output swing for increased noise margin • Available in SSOP and TSSOP packages This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology. The ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B direction. Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latchenable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high. The ALVCH16260 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance. The ALVCH16260 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors. DRIVE FEATURES: • High Output Drivers: ±24mA • Suitable for heavy loads APPLICATIONS: • 3.3V high speed systems • 3.3V and lower voltage computing systems FUNCTIONAL BLOCK DIAGRAM OE1B LEA1B LE1B 29 30 A-1B LATCH 2 1B-A LATCH 12 SEL 1 B 1:12 12 12 12 28 1 OEA A 1:12 12 M U X 1 0 12 27 2B-A LATCH 55 A-2B LATCH 12 LE2B LEA2B 12 2 B 1:12 12 56 O E2B The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE JANUARY 2004 1 © 2004 Integrated Device Technology, Inc. DSC-4737/2 IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol Description VTERM(2) Max Unit Terminal Voltage with Respect to GND –0.5 to +4.6 V OEA 1 56 OE2B VTERM(3) Terminal Voltage with Respect to GND –0.5 to VCC+0.5 V LE1B 2 55 LEA2B TSTG Storage Temperature –65 to +150 °C 2B3 3 54 2B4 –50 to +50 mA GND 4 53 GND ±50 mA 2B2 5 52 2B1 6 VCC A1 A2 IOUT DC Output Current IIK Continuous Clamp Current, VI < 0 or VI > VCC 2B5 IOK Continuous Clamp Current, VO < 0 –50 mA 51 2B6 mA 50 VCC Continuous Current through each VCC or GND ±100 7 ICC ISS 8 49 2B7 9 48 2B8 A3 10 47 2B9 GND 11 46 GND A4 12 45 2B10 A5 13 44 2B11 A6 14 43 2B12 A7 15 42 1B12 Symbol Conditions Typ. Max. Unit A8 16 41 1B11 CIN Input Capacitance VIN = 0V 5 7 pF A9 17 40 1B10 COUT Output Capacitance VOUT = 0V 7 9 pF GND 18 39 GND CI/O I/O Port Capacitance VIN = 0V 7 9 pF A10 19 38 1B9 A11 20 37 1B8 A12 21 36 1B7 VCC 22 35 VCC 1B1 23 34 1B6 1B2 24 33 1B5 GND 25 32 GND 1B3 26 31 1B4 LE2B 27 30 LEA1B SEL 28 29 OE1B NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VCC terminals. 3. All terminals except VCC. CAPACITANCE (TA = +25°C, F = 1.0MHz) Parameter(1) NOTE: 1. As applicable to the device type. FUNCTION TABLES(1) B-TO-A (OEB = H) Inputs SSOP/ TSSOP TOP VIEW 2 Output 1Bx 2Bx SEL LE1B LE2B OEA Ax H X H H X L H L X H H X L L X X H L X L A0 X H L X H L H X L L X H L L X X L X L L A0 X X X X X H Z (2) (2) IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE FUNCTION TABLES (CONTINUED)(1) A-TO-B (OEA = H) Inputs Outputs Ax LEA1B LEA2B OE1B OE2B 1Bx 2Bx H H H L L H H L H H L L L L H H L L L H 2B0 L H L L L L 2B0 H L H L L 1B0 L L H L L 1B0 (2) (2) (2) H (2) L (2) (2) X L L L L 1B0 2B0 X X X H H Z Z X X X L H Active Z X X X H L Z Active X X X L L Active Active NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don’t Care Z = High Impedance 2. Output level before the indicated steady-state input conditions were established. PIN DESCRIPTION Pin Names I/O Description Ax(1:12) I/O Bidirectional Data Port A. Usually connected to the CPU's address/data bus. 1Bx(1:12) I/O Bidirectional Data Port 1B. Usually connected to the even path or even bank of memory. 2Bx(1:12) I/O Bidirectional Data Port 2B. Usually connected to the odd path or odd bank of memory. LEA1B I Latch Enable Input for A-1B Latch. The latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA1B. LEA2B I Latch Enable Input for A-2B Latch. The latch is open when LEA2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LEA2B. LE1B I Latch Enable Input for 1B-A Latch. The latch is open when LE1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LE1B. LE2B I Latch Enable Input for 2B-A Latch. The latch is open when LE2B is HIGH. Data from the A-port is latched on the HIGH to LOW transition of LE2B. SEL I 1B or 2B Port Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port to A Port. OEA I Output Enable for A Port (Active LOW) OE1B I Output Enable for 1B Port (Active LOW) OE2B I Output Enable for 2B Port (Active LOW) (1) (1) (1) NOTE: 1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os. 3 IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition: TA = –40°C to +85°C Symbol VIH VIL Min. Typ.(1) Max. Unit VCC = 2.3V to 2.7V 1.7 — — V VCC = 2.7V to 3.6V 2 — — VCC = 2.3V to 2.7V — — 0.7 VCC = 2.7V to 3.6V — — 0.8 Parameter Input HIGH Voltage Level Input LOW Voltage Level Test Conditions V IIH Input HIGH Current VCC = 3.6V VI = VCC — — ±5 µA IIL Input LOW Current VCC = 3.6V VI = GND — — ±5 µA IOZH High Impedance Output Current VCC = 3.6V VO = VCC — — ±10 µA IOZL (3-State Output pins) VO = GND — — ±10 VIK Clamp Diode Voltage VCC = 2.3V, IIN = –18mA — –0.7 –1.2 V VH ICCL ICCH ICCZ ∆ICC Input Hysteresis Quiescent Power Supply Current VCC = 3.3V VCC = 3.6V VIN = GND or VCC — — 100 0.1 — 40 mV µA Quiescent Power Supply Current Variation One input at VCC - 0.6V, other inputs at VCC or GND — — 750 µA Min. Typ.(2) Max. Unit – 75 — — µA VI = 0.8V 75 — — VI = 1.7V – 45 — — 45 — — — ±500 NOTE: 1. Typical values are at VCC = 3.3V, +25°C ambient. BUS-HOLD CHARACTERISTICS Symbol IBHH Parameter(1) Test Conditions Bus-Hold Input Sustain Current VCC = 3V Bus-Hold Input Sustain Current VCC = 2.3V Bus-Hold Input Overdrive Current VCC = 3.6V VI = 2V IBHL IBHH IBHL IBHHO VI = 0.7V VI = 0 to 3.6V IBHLO NOTES: 1. Pins with Bus-Hold are identified in the pin description. 2. Typical values are at VCC = 3.3V, +25°C ambient. 4 — µA µA IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE OUTPUT DRIVE CHARACTERISTICS Symbol VOH VOL Test Conditions(1) Parameter Output HIGH Voltage Output LOW Voltage Min. Max. Unit V VCC = 2.3V to 3.6V IOH = – 0.1mA VCC – 0.2 — VCC = 2.3V IOH = – 6mA 2 — VCC = 2.3V IOH = – 12mA 1.7 — VCC = 2.7V 2.2 — VCC = 3V 2.4 — VCC = 3V IOH = – 24mA 2 — VCC = 2.3V to 3.6V IOL = 0.1mA — 0.2 VCC = 2.3V IOL = 6mA — 0.4 IOL = 12mA — 0.7 VCC = 2.7V IOL = 12mA — 0.4 VCC = 3V IOL = 24mA — 0.55 V NOTE: 1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = – 40°C to + 85°C. OPERATING CHARACTERISTICS, TA = 25°C Symbol Parameter CPD Power Dissipation Capacitance Outputs enabled CPD Power Dissipation Capacitance Outputs disabled VCC = 2.5V ± 0.2V VCC = 3.3V ± 0.3V Test Conditions Typical Typical Unit CL = 0pF, f = 10Mhz 37 41 pF 4 7 SWITCHING CHARACTERISTICS(1) VCC = 2.5V ± 0.2V Symbol Parameter VCC = 2.7V VCC = 3.3V ± 0.3V Min. Max. Min. Max. Min. Max. Unit 1 5.4 — 5.1 1.2 4.3 ns 1 5.4 — 5.1 1.2 4.3 ns 1 5.6 — 5.2 1 4.4 ns 1 5.6 — 5.2 1 4.4 ns 1 6.9 — 6.6 1.1 5.6 ns 1 6.7 — 6.4 1 5.4 ns 1 5.7 — 5 1.3 4.6 ns tPLH Propagation Delay tPHL Ax to 1Bx or Ax to 2Bx tPLH Propagation Delay tPHL 1Bx to Ax or 2Bx to Ax tPLH Propagation Delay tPHL LEXB to Ax tPLH Propagation Delay tPHL LE1B to 1BX or LEA2B to 2Bx tPLH Propagation Delay tPHL SEL to Ax tPZH Output Enable Time tPZL OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx tPHZ Output Disable Time tPLZ OEA to Ax, OE1B to 1Bx, or OE2B to 2Bx tSU Set-up Time, data before LE1B, LE2B, LEA1B, LEA2B 1.4 — 1.1 — 1.1 — ns tH Hold Time, data after LE1B, LE2B, LEA1B, LEA2B 1.6 — 1.9 — 1.5 — ns tW Pulse Width, LE1B, LE2B, LEA1B, or LEA2B HIGH 3.3 — 3.3 — 3.3 — ns Output Skew(2) — — — — — 500 ps tSK(O) NOTES: 1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C. 2. Skew between any two outputs of the same package and switching in the same direction. 5 IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS VCC(1)= 3.3V±0.3V VCC(1)= 2.7V Symbol VCC(2)= 2.5V±0.2V Unit VLOAD 6 6 2 x Vcc V VIH 2.7 2.7 Vcc V VT 1.5 1.5 Vcc / 2 V VLZ 300 300 150 mV VHZ 300 300 150 mV CL 50 50 30 pF (1, 2) VIN tPHL VIH VT 0V ALVC Link DISABLE ENABLE CONTROL INPUT GND tPZL D.U.T. OUTPUT SWITCH NORMALLY CLOSED LOW tPZH OUTPUT SWITCH NORMALLY OPEN HIGH 500Ω CL ALVC Link Test Circuit for All Outputs tPLH Propagation Delay VOUT RT tPHL OPPOSITE PHASE INPUT TRANSITION Open 500Ω tPLH OUTPUT VLOAD VCC Pulse Generator VIH VT 0V VOH VT VOL SAME PHASE INPUT TRANSITION tPLZ VLOAD/2 VT VIH VT 0V VLOAD/2 VLZ VOL tPHZ VOH VHZ 0V VT 0V ALVC Link DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Enable and Disable Times NOTE: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. NOTES: 1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns. 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns. DATA INPUT SWITCH POSITION Test GND All Other Tests Open INPUT OUTPUT 1 tPLH1 SYNCHRONOUS CONTROL VIH VT 0V VOH VT VOL tSK (x) OUTPUT 2 LOW-HIGH-LOW PULSE VT tW HIGH-LOW-HIGH PULSE VT ALVC Link tPHL2 Pulse Width tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1 Output Skew - tSK(X) tH Set-up, Hold, and Release Times VOH VT VOL tPLH2 tSU ALVC Link tPHL1 tSK (x) tREM ASYNCHRONOUS CONTROL VLOAD Disable High Enable High tH TIMING INPUT Switch Open Drain Disable Low Enable Low tSU VIH VT 0V VIH VT 0V VIH VT 0V VIH VT 0V ALVC Link NOTES: 1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs. 2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank. 6 IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE ORDERING INFORMATION IDT ALVC X XX Bus-Hold Temp. Range XX Family XX XXX Device Type Package CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 PV PA Shrink Small Outline Package Thin Shrink Small Outline Package 260 12-Bit to 24-Bit Multiplexed D-Type Latch with 3-State Outputs 16 Double-Density, ±24mA H Bus-Hold 74 –40°C to +85°C for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459