Integrated Device Technology, Inc. FEATURES: • • • • • • • • • • • IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY 0.5 MICRON CMOS Technology Typical tsk(o) (Output Skew) < 250ps, clocked mode Low input and output leakage ≤1µA (max) ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack Extended commercial range of –40°C to +85°C VCC = 5V ±10% Balanced Output Drivers: ±24mA (commercial) ±16mA (military) Series current limiting resistors Generate/Check, Check/Check modes Open drain parity error allows wire-OR DESCRIPTION: The FCT162511AT/CT 16-bit registered/latched transceiver with parity is built using advanced dual metal CMOS technology. This high-speed, low-power transceiver combines D- type latches and D-type flip-flops to allow data flow in transparent, latched or clocked modes. The device has a parity generator/cheker in the A-to-B direction and a parity checker in the B-to-A direction. Error checking is done at the byte level with separate parity bits for each byte. Separate error flags exits for each direction with a single error flag indicating an error for either byte in the A-to-B direction and a second error flag indicating an error for either byte in the B-to-A direction. The parity error flags are open drain outputs which can be tied together and/or tied with flags from other devices to form a single error flag or interrupt. The parity error flags are enabled by the OExx control pins allowing the designer to disable the error flag during combinational transitions. The control pins LEAB, CLKAB and OEAB control operation in the A-to-B direction while LEBA, CLKBA and OEBA control the B-to-A direction. GEN/CHK is only for the selection of A-to-B operation, the B-to-A direction is always in checking mode. The ODD/EVEN select is common between the two directions. Except for the ODD/EVEN control, independent operation can be achieved between the two directions by using the corresponding control lines. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM: LEAB CLKAB OEAB Data Parity, data 16 18 Parity GEN/CHK A0-15 Byte Parity Generator/ Checker Latch/ Register 2 B0-15 PB1,2 PERB (Open Drain) PA1,2 ODD/EVEN LEBA CLKBA Parity, Data Parity, data 18 18 OEBA Latch/ Register Byte Parity Checking PERA (Open Drain) 2916 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES 1996 Integrated Device Technology, Inc. 5.11 AUGUST 1996 DSC–2916/5 1 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES FUNCTIONAL BLOCK DIAGRAM ODD/EVEN OEAB LEBA CLKBA CLKAB LEAB A 0 - A7 C C D D C B0 - B 7 C D D OEBA P O PA1 C C D D PB1 I P C C D D A8 - A15 C C D D C C D P O PA2 B8 - B15 D C C D D PB2 I C C D GEN/CHK C C D D C PERA (Open Drain) D D PERB (Open Drain) C D P 2916 drw 02 5.11 2 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES PIN CONFIGURATIONS OEAB 1 56 GEN/CHK OEAB 1 56 GEN/CHK LEAB 2 55 CLKAB LEAB 2 55 CLKAB PA1 3 54 PB1 PA1 3 54 PB1 GND 4 53 GND GND 4 53 GND A0 5 52 B0 A0 5 52 B0 A1 6 51 B1 A1 6 51 B1 VCC 7 50 VCC VCC 7 50 VCC A2 8 49 B2 A2 8 49 B2 A3 9 48 B3 A3 9 48 B3 A4 10 47 B4 A4 10 47 B4 A5 11 46 B5 A5 11 46 B5 A6 12 45 B6 A6 12 45 B6 A7 13 44 B7 A7 13 44 B7 43 PERB GND 14 SO56-1 43 SO56-2 15 SO56-3 42 PERB GND 14 GND PERA 15 42 GND A8 16 41 B8 A8 16 41 B8 A9 17 40 B9 A9 17 40 B9 A10 18 39 B10 A10 18 39 B10 A11 19 38 B11 A11 19 38 B11 A12 20 37 B12 A12 20 37 B12 A13 21 36 B13 A13 21 36 B13 VCC 22 35 VCC VCC 22 35 VCC A14 23 34 B14 A14 23 34 B14 A15 24 33 B15 A15 24 33 B15 GND 25 32 GND GND 25 32 GND PA2 26 31 PB2 PA2 26 31 PB2 OEBA 27 30 CLKBA OEBA 27 30 CLKBA LEBA 28 29 ODD/EVEN LEBA 28 29 ODD/EVEN PERA SSOP/ TSSOP/TVSOP TOP VIEW E56-1 CERPACK TOP VIEW 2916 drw 03 2916 drw 04 5.11 3 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY ABSOLUTE MAXIMUM RATINGS(1) PIN DESCRIPTION Symbol Description Max. VTERM(2) Terminal Voltage with Respect to –0.5 to +7.0 GND VTERM(3) Terminal Voltage with Respect to –0.5 to GND VCC +0.5 TSTG Storage Temperature –65 to +150 I OUT DC Output Current –60 to +120 Pin Names Unit V OEAB OEBA V LEAB Ax X X X Z L H X L L L H X H H L L ↑ L L L L ↑ H H L L L X B(2) L L H X B(3) B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input mA CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input Ax A-to-B Data Inputs or B-to-A 3-State Outputs Bx B-to-A Data Inputs or A-to-B 3-State Outputs PERA PERB Parity Error (Open Drain) on A Outputs Parity Error (Open Drain) on B Outputs PAx(1) A-to-B Parity Input, B-to-A Parity Output PBx ODD/EVEN GEN/CHK B-to-A Parity Input, A-to-B Parity Output Parity Mode Selection Input A to B Port Generate or Check Mode Input 2916 tbl 03 NOTES: 1. The PAx pin input is internally disabled during parity generation. This means that when generating parity in the A to B direction there is no need to add a pull up resistor to guarantee state. The pin will still function properly as the parity output for the B to A direction. Outputs Bx H A-to-B Output Enable Input (Active LOW) LEBA FUNCTION TABLE(1,4) Inputs LEAB CLKAB Description °C 2916 lnk 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Open drain and all device terminals except FCT162XXXT Output and I/O terminals. 3. Output and I/O terminals for FCT162XXXT. OEAB MILITARY AND COMMERCIAL TEMPERATURE RANGES NOTES: 2916 tbl 02 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and CLKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance ↑ = LOW-to-HIGH Transition 5.11 4 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY CAPACITANCE (TA = +25°C, f = 1.0MHz) Parameter(1) Symbol CIN Input Capacitance CI/O I/O Capacitance CO Open Drain Capacitance Conditions VIN = 0V Typ. 3.5 Max. 6.0 Unit pF VOUT = 0V 3.5 8.0 pF VOUT = 0V 3.5 6.0 NOTE: 1. This parameter is measured at characterization but not tested. FUNCTION TABLE (PARITY GENERATION)(1, 2, 3, 4, 5) A0 - A7, Total Number of inputs that are high pF 2916 lnk 04 ODD/EVEN PB1 1, 3, 5 or 7 L H 1, 3, 5 or 7 H L 0, 2, 4, 6 or 8 L L 0, 2, 4, 6 or 8 H H 2916 tbl 06 NOTES: 1. Conditions shown are for GEN/CHK = L, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B is performing generation. B-to-A will not generate parity. 3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 4. Conditions shown are for the byte A0-A7 . The byte A8-A15 is similiar but will output the parity on PB2. 5. The error flag PERB will remain in a high state during parity generation. FUNCTION TABLE (PARITY CHECKING)(1, 2, 3, 4) A0 - A7 and PA1 (5), Total Number of inputs that are high MILITARY AND COMMERCIAL TEMPERATURE RANGES ODD/EVEN PERB 1, 3, 5, 7 or 9 L L 1, 3, 5, 7 or 9 H H(6) 0, 2, 4, 6 or 8 L H(6) 0, 2, 4, 6 or 8 H L 2916 tbl 05 NOTES: 1. Conditions shown are for GEN/CHK = H, OEAB = L, OEBA = H. 2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses OEBA = L, OEAB = H and errors will be indicated on PERA. 3. In parity checking mode the parity bits will be transmitted unchanged along with the corresponding data regardless of parity errors. (PB1 = PA1). 4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered clock. 5. Conditions shown are for the byte A0-A7 and PA1. The byte A8-A15 and PA2 is similiar. 6. The parity error flag PERB is a combined flag for both bytes A0-A7 and A8A15. If a parity error occurs on either byte PERB will go low. PERB is an open drain output which must be externally pulled up to achieve a logic HIGH. 5.11 5 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = –40°C to +85°C, VCC = 5.0V ± 10%; Military: TA = –55°C to +125°C, VCC = 5.0V ± 10% Parameter Input HIGH Level Test Conditions(1) Guaranteed Logic HIGH Level VIL Input LOW Level II H Input HIGH Current (Input pins)(5) Symbol VIH Min. 2.0 Typ.(2) — Max. Guaranteed Logic LOW Level — — 0.8 V VCC = Max. — — ±1 µA — — ±1 — — ±1 — — ±1 — — ±1 VI = VCC Input HIGH Current (I/O pins)(5) II L Input LOW Current (Input pins)(5) VI = GND Input LOW Current (I/O pins)(5) I OZH High Impedance Output Current VCC = Max. VO = 2.7V pins) (5) I OZL (3-State Output VIK Clamp Diode Voltage I OS Short Circuit Current VH Input Hysteresis I CCL I CCH I CCZ Quiescent Power Supply Current VO = 0.5V VCC = Min., IIN = –18mA VCC = Max., VO = GND (3) — VCC = Max., VIN = GND or VCC — Unit V µA — — ±1 — –0.7 –1.2 V –80 –140 –225 mA — 100 — mV — 5 500 µA 2916 lnk 07 OUTPUT DRIVE CHARACTERISTICS FOR FCT162511T Symbol IODL Parameter Output LOW (I/O pins) Current Test Conditions(1) VCC = 5V, VIN = VIH or VIL, VOUT = 1.5V (3) (Open Drain) IODH Output HIGH Current (I/O pins) VCC = 5V, VIN = VIH or VIL, VOUT = IOFF Output Power Off Leakage Current (Open Drain)(5) Output HIGH Voltage (I/O pins) VCC = 0, VO ≤ 5.5V VOH VOL Output LOW Voltage (I/O pins) VCC = Min. VIN = VIH or VIL VCC = Min. VIN = VIH or VIL (Open Drain) 1.5V (3) IOH = –16mA MIL. IOH = –24mA COM'L. IOL = 16mA MIL. IOL = 24mA COM'L. IOL = 48mA MIL. IOL = 64mA COM'L. Min. 60 Typ.(2) 115 Max. 200 Unit — 250 — mA –60 –115 –200 mA — — ±1 µA 2.4 3.3 — V — 0.3 0.55 V — 0.3 0.55 V NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5.0V, +25°C ambient. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. Duration of the condition can not exceed one second. 5. The test limit for this parameter is ± 5µA at TA = –55°C. 5.11 mA 2916 tbl 08 6 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol Parameter ∆ICC Quiescent Power Supply Current TTL Inputs HIGH ICCD Dynamic Power Supply Current(4) Test Conditions(1) Typ.(2) Max. Unit — — 0.5 1.0 1.5 2.5 mA VIN = VCC VIN = GND — 75 120 µA/ MHz VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND One Bit Toggling fi = 5MHz 50% Duty Cycle VIN = VCC VIN = GND — 0.8 1.7 mA VIN = 3.4V VIN = GND — 1.3 3.2 VCC = Max., Outputs Open fCP = 10MHz (CLKAB) 50% Duty Cycle OEAB = GND, OEBA = VCC LEAB = GND Eighteen Bits Toggling fi = 2.5MHz 50% Duty Cycle VIN = VCC VIN = GND — 3.8 6.5(5) VIN = 3.4V VIN = GND — 9.0 21.8(5) VCC = Max. VIN = 3.4V(3) Min. All other Input Pins Parity Input Pins (PAx, PBx) VCC = Max., Outputs Open OEAB = GND, OEBA = VCC One Input Toggling 50% Duty Cycle IC Total Power Supply Current(6) NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25°C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fCPNCP/2 + fiNi) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for Register Devices (Zero for Non-Register Devices) NCP = Number of Clock Inputs at fCP fi = Input Frequency Ni = Number of Inputs at fi 5.11 2916 tbl 09 7 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE (PROPAGATION DELAYS) FCT162511AT Com'l. Com'l. Mil. Min.(2) Max. Min.(2) Max. Min.(2) Max. Min.(2) Max. Unit 1.5 5.0 1.5 5.3 1.5 4.2 1.5 4.5 ns 1.5 7.5 1.5 8.0 1.5 6.5 1.5 6.8 ns Propagation Delay 1.5 9.0 1.5 9.0 1.5 7.5 1.5 7.8 ns Ax to PERB, PAx to PERB 1.5 8.0 1.5 8.0 1.5 6.5 1.5 6.8 tPLH(3) Propagation Delay 1.5 9.0 1.5 9.0 1.5 7.5 1.5 7.8 tPHL Bx to PERA, PBx to PERA 1.5 8.0 1.5 8.0 1.5 6.5 1.5 6.8 1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.5 ns 1.5 7.0 1.5 7.0 1.5 6.0 1.5 6.3 ns 1.5 6.0 1.5 6.0 1.5 5.0 1.5 5.3 1.5 5.6 1.5 6.0 1.5 5.3 1.5 5.5 ns 1.5 7.0 1.5 7.0 1.5 6.0 1.5 6.3 ns 1.5 6.0 1.5 6.0 1.5 5.0 1.5 5.3 1.5 6.0 1.5 6.5 1.5 5.6 1.5 5.8 ns 1.5 5.6 1.5 6.0 1.5 5.2 1.5 5.5 ns 1.5 6.0 1.5 6.3 1.5 6.0 1.5 6.3 ns Symbol Parameter Condition(1) FCT162511CT Mil. tPLH tPHL tPLH Propagation Delay, PAx to PBx CL = 50pF Ax to Bx or Bx to Ax, PBx to PAx RL = 500Ω Propagation Delay GEN/CHK LOW tPHL Ax to PBx tPLH(3) tPHL tPLH tPHL tPLH(3) Propagation Delay LEBA to Ax and PAx LEAB to Bx and PBx Propagation Delay tPHL LEBA to PERA, LEAB to PERB tPLH tPHL tPLH(3) Propagation Delay CLKBA to Ax and PAx CLKAB to Bx and PBx Propagation Delay tPLZ(3) tPZL CLKBA to PERA CLKAB to PERB Output Enable Time OEBA to Ax and PAx OEAB to BX and PBx Output Disable Time OEBA to Ax and PAx OEAB to Bx and PBx Parity ERROR Enable OEBA to PERA, OEAB to PERB tPLH(3) ODD/EVEN to PERx tPHL tPZH tPZL tPHZ tPLZ tPHL tPLH ODD/EVEN to PBx 1.5 6.0 1.5 6.3 1.5 6.0 1.5 6.3 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 1.5 10.0 ns ns ns tPHL NOTES: 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. On Open Drain Outputs tPLH is measured at VOUT = VOL + 0.3V. 2916 tbl 10 5.11 8 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES) FCT162511AT Com'l. Symbol tSU Parameter Set-up Time Test Conditions(1,3) GEN/CHK LOW HIGH or LOW Ax to CLKAB tSU Set-up Time GEN/CHK HIGH GEN/CHK HIGH PAx to CLKAB Min. Max. Min. Max. Min. Max. Min. 4 — 4 — 3 — 3.5 — ns PBx not valid RL = 500Ω 3 — 3 — 3 — 3 — ns 4 — 4 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 4 — 4 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 4 — 4 — 3 — 3 — ns 3 — 4 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid tSU Bx to CLKBA, PBx to CLKBA Set-up Time CLKAB LOW PBx valid Ax to LEAB GEN/CHK LOW PBx not valid GEN/CHK HIGH PERB valid PERB not valid CLKAB HIGH PBx valid GEN/CHK LOW PBx not valid GEN/CHK HIGH tSU Set-up Time CLKAB LOW PAx to LEAB GEN/CHK HIGH CLKAB HIGH GEN/CHK HIGH tSU Set-up Time CLKBA LOW Bx to LEBA PBx to LEBA tSK(O) Output CLKBA HIGH Mil. CL = 50pF Set-up Time CLKAB HIGH Com'l. PBx valid tSU CLKAB LOW FCT162511CT Mil. PERB valid PERB not valid PERB valid PERB not valid PERB valid PERB not valid PERA valid PERA not valid PERA valid PERA not valid Skew (4) Max. Unit 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns 3.5 — 3.5 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns — 0.5 — 0.5 — 0.5 — 0.5 ns 2916 tbl 11 SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES) FCT162511AT Com'l. FCT162511CT Mil. Com'l. Mil. Symbol Parameter Condition(1) Min. Max. Min. Max. Min. Max. Min. Max. Unit tH Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA CL = 50pF 1 — 1 — 1 — 1 — ns tH Hold Time HIGH or LOW PAx to LEAB RL = 500Ω 1 — 1 — 1 — 1 — ns tH Hold Time HIGH or LOW PBx to LEBA 1 — 1 — 1 — 1 — ns tH Hold Time Ax to CLKAB, PAx to CLKAB 1 — 1 — 0 — 0 — ns tH Hold Time Bx to CLKBA, PBx to CLKBA 1 — 1 — 0 — 0 — ns 3 — 3 — 3 — 3 — ns 3 — 3 — 3 — 3 — ns tW tW LEAB or LEBA Pulse Width HIGH (2) CLKAB or CLKBA Pulse Width HIGH or LOW(2) 2916 tbl 12 NOTES: 1. See test circuits and waveforms. 2. This parameter is guaranteed but not tested. 3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the A to B or B to A port respective to the indicated direction. 4. Skew between any two outputs of the same package, switching in the same direction, excluding PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/latched mode. This parameter is guaranteed by design. 5.11 9 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION TEST CIRCUITS FOR ALL OUTPUTS V CC 500Ω Switch Open Drain Disable Low Closed Enable Low V OUT VIN Pulse Generator Test 7.0V Open All Other Tests D.U.T. 50pF RT 2916 lnk 13 DEFINITIONS: CL= Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. 500Ω CL 2916 drw 05 SET-UP, HOLD AND RELEASE TIMES DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tH tSU tREM tSU PULSE WIDTH 3V 1.5V 0V 3V 1.5V 0V LOW-HIGH-LOW PULSE 1.5V tW 3V 1.5V 0V HIGH-LOW-HIGH PULSE 1.5V 3V 1.5V 0V tH 2916 drw 07 2916 drw 06 PROPAGATION DELAY ENABLE AND DISABLE TIMES ENABLE SAME PHASE INPUT TRANSITION tPLH tPHL OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL 3V 1.5V 0V DISABLE 3V 1.5V 0V CONTROL INPUT tPZL VOH 1.5V VOL OUTPUT NORMALLY LOW 3V 1.5V 0V SWITCH CLOSED tPLZ tPZH OUTPUT NORMALLY HIGH 2916 drw 08 SWITCH OPEN 3.5V 3.5V 1.5V 0.3V VOL tPHZ 0.3V 1.5V 0V VOH 0V 2916 drw 09 NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 5.11 10 IDT54/74FCT162511AT/CT FAST CMOS 16-BIT REGISTERED/LATCHED TRANSCEIVER WITH PARITY MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT FCT XXXX X Device Temperature Type Range X Package X Process Blank B Commercial MIL-STD-883, Class B PV PA PF E Shrink Small Outline Package (SO56-1) Thin Shrink Small Outline Package (SO56-2) Thin Very Small Outline Package (SO56-3) CERPACK (E56-1) 162511AT 162511CT 54 74 16-Bit Registered Transceiver with Parity –55°C to +125°C –40°C to +85°C 2916 drw 10 5.11 11